 Emil J. Tywoniak
|
7818419608
|
tests: fix rtlil roundtrip test
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
1e1cc5c916
|
design: fix signorm commit connectivity to design
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
b17441aa0d
|
cxxrtl: ignore $input_port
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
375f4600db
|
flatten: redo signormalization to work around fanout issue
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
c3807b4137
|
abstract: fix test signorm
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
7a09c32040
|
signorm: disable passes that use rewrite_sigspecs
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
238bf5905d
|
aiger: ignore $input_port
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
2f37005ada
|
check: stitch info about $connect ports together for driver analysis
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
6dd987ee3c
|
signorm: remove $input cells when leaving
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
5938e03e5d
|
abstract: skip $input_port cells
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
bd4f16fd9e
|
flatten: skip $input_port cells in template module
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
3a606ec48e
|
signorm: skip const when fixing fanout
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
6c048fdfb9
|
signorm: disable in passes that use swap_names
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
db1b0ee8a2
|
opt_expr: fix invert_map
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
41d4c1da36
|
satgen: support $connect
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
8d8a1cb46c
|
rtlil: add dump_sigmap for hacky signorm debugging
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
e6b7a50b30
|
techmap: disable signorm more
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
e4b62727bd
|
techmap: disable signorm
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
01e17a383a
|
opt_hier: disable signorm
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
a55244ee3c
|
timinginfo: disable output wire check due to signorm
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
196cb50038
|
rtlil: forbid rewrite_sigspecs in signorm
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
8a9f038d54
|
opt_merge_inc: re add initvals deletion
|
2026-09-17 14:13:57 +02:00 |
|
|
Emil J. Tywoniak
|
2ccfd2b23b
|
synth_ice40: always read abc9 model to understand port direction
|
2026-09-17 14:13:55 +02:00 |
|
|
Emil J. Tywoniak
|
ba37814053
|
tests: adjust to input_port and init behavior (sketchy)
|
2026-09-17 14:12:38 +02:00 |
|
|
Emil J. Tywoniak
|
fc7f53ba76
|
tests: adjust to input_port and init behavior (sketchy)
|
2026-09-17 14:12:38 +02:00 |
|
|
Emil J. Tywoniak
|
d5f55fcd11
|
tests: adjust to input_port and init behavior (sketchy)
|
2026-09-17 14:12:38 +02:00 |
|
|
Emil J. Tywoniak
|
34b8284bcb
|
wreduce: fixup initvals after setPort
|
2026-09-17 14:12:38 +02:00 |
|
|
Emil J. Tywoniak
|
42a9ec0dba
|
ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire
|
2026-09-17 14:12:38 +02:00 |
|
|
Emil J. Tywoniak
|
33fc543083
|
tests: adjust to input_port and init behavior (sketchy)
|
2026-09-17 14:12:38 +02:00 |
|
|
Emil J. Tywoniak
|
6f27925eff
|
rtlil: fix zero width SigSpec crash in signorm setPort unsetPort
|
2026-09-17 14:12:38 +02:00 |
|
|
Emil J. Tywoniak
|
e2817ef5a1
|
bug2920: disable
|
2026-09-17 14:12:38 +02:00 |
|
|
Emil J. Tywoniak
|
696f7dc173
|
rtlil_bufnorm: fix cell deletion deferral bug
|
2026-09-17 14:12:38 +02:00 |
|
|
Emil J. Tywoniak
|
8cf327c769
|
tests: adjust to input_port and init behavior (sketchy)
|
2026-09-17 14:12:38 +02:00 |
|
|
Emil J. Tywoniak
|
c0a29e2d40
|
check: don't fail on $input_port
|
2026-09-17 14:12:38 +02:00 |
|
|
Emil J. Tywoniak
|
f2fbfbb512
|
mem: fix signorm cell type morph
|
2026-09-17 14:12:38 +02:00 |
|
 Jannis Harder
|
52ec5579fb
|
WIP half broken snapshot
|
2026-09-17 14:12:36 +02:00 |
|
|
Jannis Harder
|
3c2b04a01b
|
WIP remove dead code
|
2026-09-17 14:10:46 +02:00 |
|
|
Emil J. Tywoniak
|
9372741e59
|
select: alias wires don't count for cone depth
|
2026-09-15 12:00:03 +02:00 |
|
 Miodrag Milanović
|
72dc977396
|
Merge pull request #6184 from YosysHQ/mmicko/svelab-update
sv-elab: Update to release 2026-09-08
|
2026-09-08 10:31:12 +00:00 |
|
|
Miodrag Milanovic
|
a80623137a
|
sv-elab: Update to release 2026-09-08
|
2026-09-08 11:58:13 +02:00 |
|
|
Miodrag Milanović
|
f1442ce42e
|
Merge pull request #6182 from YosysHQ/lofty/revert-read_xaiger2
Temporarily revert #6101 and #6077
|
2026-09-08 04:53:08 +00:00 |
|
 Lofty
|
51583d854a
|
Revert "Merge pull request #6077 from YosysHQ/lofty/abc-refactor-8"
This reverts commit fd6367405e, reversing
changes made to 0f2bcb94b7.
|
2026-09-07 17:29:08 +01:00 |
|
 nella
|
7c26ff16c6
|
Merge pull request #6162 from YosysHQ/nella/scl-cache-dir
liberty_cache: per user SCL cache directory [sc-843]
|
2026-09-07 14:52:21 +00:00 |
|
|
Miodrag Milanović
|
95e245f563
|
Merge pull request #6181 from YosysHQ/mmicko/wheels
cmake: fix wheels build
|
2026-09-07 11:18:08 +00:00 |
|
|
Miodrag Milanovic
|
7a29365a3e
|
cmake: fix wheels build
|
2026-09-07 12:38:32 +02:00 |
|
|
Miodrag Milanović
|
c2bf7dc67b
|
Merge pull request #6180 from YosysHQ/mmicko/unused
cmake: replace -Werror=unused with more specific options
|
2026-09-07 10:06:32 +00:00 |
|
|
Miodrag Milanovic
|
756434cc23
|
cmake: replace -Werror=unused with more specific options
|
2026-09-07 11:27:12 +02:00 |
|
|
nella
|
435977e970
|
Merge pull request #6176 from YosysHQ/nella/cell-rank
dfflibmap: rank cells on an explicit tuple [sc-906]
|
2026-09-04 23:24:10 +00:00 |
|
|
nella
|
dbef3ec8a5
|
Merge branch 'main' into nella/cell-rank
|
2026-09-04 16:06:21 -07:00 |
|
|
nella
|
0f87e78af3
|
Merge pull request #6167 from YosysHQ/nella/opt-dff-quadratics
opt_dff: avoid quadratic sigmapping in mux tree feedback search [sc-839]
|
2026-09-04 17:35:08 +00:00 |
|