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15987 Commits

Author SHA1 Message Date
Emil J. Tywoniak 734249a5e6 opt_dff: temporarily disable signorm due to muxtree traversal 2026-03-24 23:22:39 +01:00
Emil J. Tywoniak 49d08591e3 tests: fix rtlil roundtrip test 2026-03-24 23:22:39 +01:00
Emil J. Tywoniak 872c940259 design: fix signorm commit connectivity to design 2026-03-18 00:44:20 +01:00
Emil J. Tywoniak a4398d4d90 fixup! cxxrtl: ignore $input_port 2026-03-17 23:00:22 +01:00
Emil J. Tywoniak b97a8cdfe3 cxxrtl: ignore $input_port 2026-03-17 18:06:07 +01:00
Emil J. Tywoniak 55189bc65c flatten: redo signormalization to work around fanout issue 2026-03-17 18:04:41 +01:00
Emil J. Tywoniak 4c8b7818f4 abstract: fix test signorm 2026-03-17 17:39:05 +01:00
Emil J. Tywoniak c01d88c303 signorm: disable passes that use rewrite_sigspecs 2026-03-17 17:35:57 +01:00
Emil J. Tywoniak 961c9a90d6 aiger: ignore $input_port 2026-03-17 17:32:56 +01:00
Emil J. Tywoniak c5d4b435bd check: stitch info about $connect ports together for driver analysis 2026-03-17 17:29:23 +01:00
Emil J. Tywoniak bbf5b3c738 signorm: remove $input cells when leaving 2026-03-17 16:37:00 +01:00
Emil J. Tywoniak 3257b8ae1e abstract: skip $input_port cells 2026-03-17 16:34:41 +01:00
Emil J. Tywoniak 9d3928c014 flatten: skip $input_port cells in template module 2026-03-17 16:11:32 +01:00
Emil J. Tywoniak debc2c3977 signorm: skip const when fixing fanout 2026-03-17 11:28:10 +01:00
Emil J. Tywoniak 869a7303b0 signorm: disable in passes that use swap_names 2026-03-16 22:45:29 +01:00
Emil J. Tywoniak 3502a51598 opt_expr: fix invert_map 2026-03-13 12:18:48 +01:00
Emil J. Tywoniak aee094e3c4 fixup! fixup! satgen: support $connect 2026-03-12 22:53:31 +01:00
Emil J. Tywoniak 4d1f8fd7d3 fixup! satgen: support $connect 2026-03-12 22:16:06 +01:00
Emil J. Tywoniak 0d353591fe satgen: support $connect 2026-03-12 22:15:34 +01:00
Emil J. Tywoniak ae946a598c rtlil: add dump_sigmap for hacky signorm debugging 2026-03-12 22:13:21 +01:00
Emil J. Tywoniak e7a97360a8 techmap: disable signorm more 2026-03-12 22:11:06 +01:00
Emil J. Tywoniak 04311e3e53 techmap: disable signorm 2026-03-11 21:30:27 +01:00
Emil J. Tywoniak 8bad1a2035 opt_hier: disable signorm 2026-03-11 21:26:12 +01:00
Emil J. Tywoniak 4611e90533 timinginfo: disable output wire check due to signorm 2026-03-11 21:25:00 +01:00
Emil J. Tywoniak 44917f50d9 rtlil: forbid rewrite_sigspecs in signorm 2026-03-11 21:07:06 +01:00
Emil J. Tywoniak d39ce10601 opt_merge_inc: re add initvals deletion 2026-03-11 12:35:16 +01:00
Emil J. Tywoniak 621bb778f5 synth_ice40: always read abc9 model to understand port direction 2026-03-11 12:25:37 +01:00
Emil J. Tywoniak 4c90e26298 tests: adjust to input_port and init behavior (sketchy) 2026-03-10 14:09:31 +01:00
Emil J. Tywoniak 30ac7d271c satgen: cover $input_port 
(cherry picked from commit d199195785)
 2026-03-10 14:06:45 +01:00
Emil J. Tywoniak c3433bced7 tests: adjust to input_port and init behavior (sketchy) 2026-03-10 14:05:37 +01:00
Emil J. Tywoniak 45a254cf61 tests: adjust to input_port and init behavior (sketchy) 2026-03-10 14:02:46 +01:00
Emil J. Tywoniak 8375f11fa5 wreduce: fixup initvals after setPort 2026-03-10 14:01:57 +01:00
Emil J. Tywoniak 298b755fb7 modtools: fix database sanity on wire name swap 
(cherry picked from commit c75d80905a)
 2026-03-09 23:46:53 +01:00
Emil J. Tywoniak 58ba984498 ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire 2026-03-09 23:38:10 +01:00
Emil J. Tywoniak 25edde1c3c tests: adjust to input_port and init behavior (sketchy) 2026-03-09 21:21:45 +01:00
Emil J. Tywoniak d2bc970ef9 rtlil: fix zero width SigSpec crash in signorm setPort unsetPort 2026-03-09 21:20:23 +01:00
Emil J. Tywoniak bdce610f3d bug2920: disable 2026-03-09 16:37:30 +01:00
Emil J. Tywoniak b206223c40 rtlil_bufnorm: fix cell deletion deferral bug 2026-03-07 01:10:04 +01:00
Emil J. Tywoniak b7c97ba743 tests: adjust to input_port and init behavior (sketchy) 2026-03-07 01:08:57 +01:00
Emil J. Tywoniak 7c5128a08a check: don't fail on $input_port 2026-03-07 00:42:01 +01:00
Emil J. Tywoniak c6b9f5d8ff mem: fix signorm cell type morph 2026-03-07 00:41:24 +01:00
Jannis Harder eae87b3161 WIP half broken snapshot 2025-10-06 14:39:25 +02:00
Jannis Harder ea0ee069fb WIP remove dead code 2025-10-04 14:40:08 +02:00
Emil J 7719beb4ae
Merge pull request #5349 from rocallahan/cleanup-hashops 
Reduce hashops verbiage in `OptMergePass`
 2025-09-30 19:34:44 +02:00
Emil J 60c551f961
Merge pull request #5400 from YosysHQ/emil/github-contribution-template-update 
Update contribution templates
 2025-09-30 11:03:49 +02:00
Emil J. Tywoniak dc7764e247 .github: typos 2025-09-30 11:03:19 +02:00
Miodrag Milanović 330a5fc101
Merge pull request #5402 from YosysHQ/micko/extensions 
Force linking log_compat when extensions are linked
 2025-09-30 09:10:04 +02:00
Miodrag Milanovic e6fa0223c8 Force linking log_compat when extensions are linked 2025-09-30 08:44:31 +02:00
github-actions[bot] 5fd2aecd90 Bump version 2025-09-30 00:23:05 +00:00
Emil J. Tywoniak b86cc0d9b3 docs: replace Slack with Discourse in extensions writing guide 2025-09-29 23:20:06 +02:00