luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

synth_ice40: always read abc9 model to understand port direction

This commit is contained in:
Emil J. Tywoniak 2026-03-11 12:25:37 +01:00
parent 4c90e26298
commit 621bb778f5
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
techlibs/ice40/synth_ice40.cc
View File

@ -379,6 +379,7 @@ struct SynthIce40Pass : public ScriptPass
run("techmap");
else {
run("ice40_wrapcarry");
run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v");
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
}
run("opt -fast");
@ -415,7 +416,6 @@ struct SynthIce40Pass : public ScriptPass
}
if (!noabc) {
if (abc9) {
run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_ice40.abc9.W";
if (active_design && active_design->scratchpad.count(k))