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timinginfo: disable output wire check due to signorm

This commit is contained in:
Emil J. Tywoniak 2026-03-11 21:25:00 +01:00
parent 44917f50d9
commit 4611e90533
1 changed files with 4 additions and 3 deletions
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7
kernel/timinginfo.h
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@ -106,9 +106,10 @@ struct TimingInfo
for (const auto &c : src.chunks())
if (!c.wire || !c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
for (const auto &c : dst.chunks())
if (!c.wire || !c.wire->port_output)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
// TODO disabled check because signorm breaks this assumption
// for (const auto &c : dst.chunks())
// if (!c.wire || !c.wire->port_output)
// log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
int max = std::max(rise_max,fall_max);