passes: leave signorm mode where the index cannot be maintained

passes/cmds/autoname.cc

@@ -283,6 +283,8 @@ struct AutonamePass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		design->sigNormalize(false);
+
 		log_header(design, "Executing AUTONAME pass.\n");
 
 		for (auto module : design->selected_modules())

passes/cmds/blackbox.cc

@@ -46,6 +46,8 @@ struct BlackboxPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		design->sigNormalize(false);
+
 		for (auto module : design->selected_whole_modules_warn(true))
 		{
 			module->makeblackbox();

passes/cmds/delete.cc

@@ -64,6 +64,7 @@ struct DeletePass : public Pass {
 			break;
 		}
 		extra_args(args, argidx, design);
+		design->sigNormalize(false);
 
 		std::vector<RTLIL::Module *> delete_mods;
 		for (auto module : design->modules())

passes/cmds/timeest.cc

@@ -417,6 +417,8 @@ struct TimeestPass : Pass {
 		}
 		extra_args(args, argidx, d);
 
+		d->sigNormalize(false);
+
 		if (select && d->selected_modules().size() > 1)
 			log_cmd_error("The -select option operates on a single selected module\n");
 

passes/fsm/fsm_extract.cc

@@ -436,6 +436,8 @@ struct FsmExtractPass : public Pass {
 		log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");
 		extra_args(args, 1, design);
 
+		design->sigNormalize(false);
+
 		CellTypes ct(design);
 
 		for (auto mod : design->selected_modules())

passes/hierarchy/submod.cc

@@ -379,6 +379,8 @@ struct SubmodPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		design->sigNormalize(false);
+
 		if (opt_name.empty())
 		{
 			Pass::call(design, "opt_clean");

passes/techmap/extract.cc

@@ -183,6 +183,8 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
 	if (max_fanout > 0)
 		for (auto cell : mod->cells())
 		{
+			if (cell->type == ID($input_port))
+				continue;
 			if (!sel || sel->selected(mod, cell))
 				for (auto &conn : cell->connections()) {
 					RTLIL::SigSpec conn_sig = conn.second;
@@ -198,6 +200,8 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
 	{
 		if (sel && !sel->selected(mod, cell))
 			continue;
+		if (cell->type == ID($input_port))
+			continue;
 
 		std::string type = cell->type.str();
 		if (sel == nullptr && type.compare(0, 2, "\\$") == 0)
@@ -252,6 +256,8 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
 	// mark external signals (used in non-selected cells)
 	for (auto cell : mod->cells())
 	{
+		if (cell->type == ID($input_port))
+			continue;
 		if (sel && !sel->selected(mod, cell))
 			for (auto &conn : cell->connections())
 			{