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tests: ignore $input_port and $connect in cell counts

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This commit is contained in:
Emil J. Tywoniak
2026-09-18 17:37:03 +02:00
parent f925de7dc4
commit 9d93aa275a
5 changed files with 11 additions and 10 deletions
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tests/arch/ice40/ice40_opt.ys
+1 -1
View File
@@ -24,7 +24,7 @@ EOT
read_verilog -icells -lib +/ice40/abc9_model.v +/ice40/cells_sim.v
equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt
design -load postopt
select -assert-count 1 t:*
select -assert-count 1 t:* t:$*_port %d t:$public %d
select -assert-count 1 t:$lut
# https://github.com/YosysHQ/yosys/issues/1543
tests/memlib/generate_mk.py
+2 -1
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@@ -1566,7 +1566,8 @@ for t in TESTS:
for kk, vv in ca.items():
sf.write("select -assert-count {} t:{} r:{}={} %i\n".format(cc, k, kk, vv))
else:
sf.write("select -assert-count {} t:{}\n".format(v, k))
suffix = " t:$*_port %d t:$public %d" if k.startswith("$") else ""
sf.write("select -assert-count {} t:{}{}\n".format(v, k, suffix))
def create_tests():
for t in TESTS:
tests/proc/yosys_latch.ys
+1 -1
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@@ -13,7 +13,7 @@ select -assert-count 1 t:$_DLATCH_P_
select -assert-count 1 t:$_DLATCH_N_
select -assert-count 1 t:$_DLATCH_PN0_
select -assert-count 1 t:$_DLATCH_NN0_
select -assert-count 4 t:*
select -assert-count 4 t:* t:$*_port %d t:$public %d
design -load gold
equiv_opt -assert -multiclock simplemap
tests/various/muxcover.ys
+1 -1
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@@ -539,7 +539,7 @@ simplemap t:\$mux
muxcover
opt_clean -purge
select -assert-count 1 t:$_MUX8_
select -assert-none t:$_MUX8_ %% t:* %D
select -assert-none t:$_MUX8_ %% t:* %D t:$*_port %d
techmap -map +/simcells.v t:$_MUX8_
design -stash gate
tests/various/peepopt.ys
+6 -6
View File
@@ -9,7 +9,7 @@ equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 1 t:$bmux
select -assert-count 0 t:$bmux t:* %D
select -assert-count 0 t:$bmux t:* %D t:$*_port %d t:$public %d
####################
@@ -26,7 +26,7 @@ design -load postopt
clean
select -assert-count 1 t:$shr
select -assert-count 1 t:$mul
select -assert-count 0 t:$shr t:$mul %% t:* %D
select -assert-count 0 t:$shr t:$mul %% t:* %D t:$*_port %d t:$public %d
####################
@@ -50,7 +50,7 @@ sat -verify -show-public -enable_undef -prove-asserts miter
cd gate
select -assert-count 1 t:$shr
select -assert-count 1 t:$mul
select -assert-count 0 t:$shr t:$mul %% t:* %D
select -assert-count 0 t:$shr t:$mul %% t:* %D t:$*_port %d t:$public %d
####################
@@ -92,7 +92,7 @@ prep -nokeepdc
equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 0 t:*
select -assert-count 0 t:* t:$*_port %d t:$public %d
####################
@@ -109,7 +109,7 @@ equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 1 t:$bmux
select -assert-count 0 t:$bmux t:* %D
select -assert-count 0 t:$bmux t:* %D t:$*_port %d t:$public %d
####################
@@ -244,4 +244,4 @@ equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 1 t:$bmux
select -assert-count 0 t:$bmux t:* %D
select -assert-count 0 t:$bmux t:* %D t:$*_port %d t:$public %d