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5050 Commits

Author SHA1 Message Date
Emil J. Tywoniak b6d656e932 csa_tree: move to techmap 2026-04-13 12:48:05 +02:00
Emil J. Tywoniak b6a8feec22 csa_tree: refactor 2026-04-13 12:48:05 +02:00
nella 67e145618b Replace utf arrow with ascii arrow. 2026-04-13 12:48:05 +02:00
nella 5d90bcc792 CSA add support for macc and alu cells. 2026-04-13 12:48:05 +02:00
nella 335cce4895 Add sub chain support for csa trees. 2026-04-13 12:48:05 +02:00
nella e69914b8be better balancing. 2026-04-13 12:48:05 +02:00
nella 46df888191 impl csa tree. 2026-04-13 12:48:05 +02:00
Lofty 564c617721
Merge pull request #5790 from Eiko-Eira/main 
Fixed typos and incorrect grammar
 2026-04-11 03:26:55 +00:00
Emil J 86448c0001
Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef 
Undefine set&reset behavior of $dffsr
 2026-04-08 14:22:34 +00:00
Emil J. Tywoniak 41b69df2cb abc_new: stable TopoSort 2026-04-06 15:09:52 +02:00
Noah Van Dijk 52243e10fb
Fix typo in pmgen/README.md 
Line 161:
calulated > calculated
 2026-04-02 10:24:31 -05:00
Emil J cede13a742
Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port 
muxpack: fix wide Y port handling
 2026-03-31 10:49:39 +00:00
tondapusili 5b22e64d19 sim: cache sigmap in register_output_step_values 2026-03-24 16:10:11 -07:00
Miodrag Milanović 66306a8ca3
Merge pull request #5769 from Silimate/optimize_sim_pass 
sim: early return from checkSignals in sim mode
 2026-03-23 17:19:26 +00:00
Emil J b44188110b
Merge pull request #5764 from YosysHQ/emil/constmap-error 
constmap: error if no -cell set
 2026-03-23 15:15:04 +00:00
tondapusili 69219e6be0 sim: early-return from checkSignals in sim mode 2026-03-20 12:32:49 -07:00
Lofty f560cba952
Merge pull request #5757 from YosysHQ/lofty/abc9-refactor-3 
abc9: remove -fast [sc-269]
 2026-03-19 08:41:45 +00:00
Lofty 27210627e5 abc9: remove -fast 2026-03-19 07:30:23 +00:00
Lofty 8d1d5a25e5
Merge pull request #5760 from YosysHQ/lofty/abc-refactor-2 
abc: remove -S [sc-269]
 2026-03-19 07:26:54 +00:00
Lofty 05de1c4ae2
Merge pull request #5759 from YosysHQ/lofty/abc9-refactor-4 
abc9: remove abc9.if.C [sc-269]
 2026-03-19 07:26:37 +00:00
Emil J. Tywoniak 4f4672d17b muxpack: fix wide Y port handling 2026-03-19 00:12:49 +01:00
Emil J. Tywoniak 7aaa0621d3 constmap: error if no -cell set 2026-03-19 00:01:14 +01:00
Emil J 9746bd3897
Merge pull request #5724 from abhinavputhran/fix/setundef-respect-selection 
setundef: respect selection for cells, processes, and connections
 2026-03-18 22:53:06 +00:00
Lofty f9d930ba5a
Revert "abc: remove -fast [sc-269]" 2026-03-18 17:55:17 +00:00
Lofty e05ed6b850
Merge pull request #5758 from YosysHQ/lofty/abc-refactor-1 
abc: remove -fast [sc-269]
 2026-03-18 15:09:36 +00:00
Lofty 0b3f103745 abc: remove -S 2026-03-18 14:40:23 +00:00
Lofty 93c762c7c1 abc9: remove abc9.if.C 2026-03-18 14:27:27 +00:00
Lofty 926814f1e4 abc9: cleanup commented code 2026-03-18 14:16:31 +00:00
Lofty 0ea739b7d9 abc: remove -fast 2026-03-18 14:15:42 +00:00
Lofty e78690fc47 abc9_exe: fix typo 2026-03-18 11:44:13 +00:00
Emil J c8f715fed8
Merge pull request #5664 from rocallahan/parallel-opt-clean 
Parallelize `opt_clean` pass
 2026-03-16 09:52:34 +00:00
Emil J. Tywoniak 498cb79abe async2sync: explain dffsr control signal variable polarity 2026-03-09 20:18:56 +01:00
Emil J. Tywoniak 43ef4d2901 fixup! async2sync: $dffsr has undef output on S&R 2026-03-09 20:12:24 +01:00
abhinavputhran 47c2257f82 setundef: more tests! and wire selection in -init mode 2026-03-08 19:41:31 -04:00
abhinavputhran 5048dac854 setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer 2026-03-06 18:12:03 -05:00
abhinavputhran 9e666c727f setundef: respect selection in -undriven mode 2026-03-06 10:37:59 -05:00
Miodrag Milanovic 52533b0d1c Update opt_lut_ins and stat for analogdevices and remove ecp5 2026-03-06 09:10:36 +01:00
Robert O'Callahan 9c51ba1b09 Reduce opt_clean parallelism 2026-03-06 02:20:16 +00:00
Robert O'Callahan 8d8c05b338 Fix `OptCleanPass` usage of `CleanRunContext` to avoid constructing extra `KeepCache` and `ParallelDispatchThreadPool` 2026-03-06 02:20:16 +00:00
Robert O'Callahan 32f5044eaf Clarify "Not passing module as function argument" comment 
This correct in terms of intent, it's just not fully enforced due to const laundering.
 2026-03-06 02:20:16 +00:00
Emil J. Tywoniak 70cc2d67fd opt_clean: refactor 2026-03-06 02:20:14 +00:00
Robert O'Callahan 3603cd52a0 Pass the module `Subpool` to `rmunused_module_signals` and parallelize that function 2026-03-06 02:20:08 +00:00
Robert O'Callahan 19a7c8fcf3 Pass the module `Subpool` to `rmunused_module_cells` and parallelize that function 2026-03-06 02:20:08 +00:00
Robert O'Callahan 8e044d1045 Pass the module `Subpool` to `rmunused_module_init` and parallelize that function 2026-03-06 02:20:06 +00:00
Robert O'Callahan a7437c636d Pass the toplevel thread pool to `rmunused_module`, create a `Subpool`, and parallelize `remove_temporary_cells` 2026-03-06 02:05:46 +00:00
Robert O'Callahan 887c32cb54 Create a toplevel `ParallelDispatchThreadPool` and parallelize `keep_cache_t::scan_module()` with it 2026-03-06 02:05:46 +00:00
Robert O'Callahan 72a21fe01d Introduce `RmStats` struct to encapsulate removal statistics 
Turns out this is not strictly necessary for this PR but it's
still a good thing to do and makes it clearer that the stats
are not modified in a possibly racy way.
 2026-03-06 02:05:43 +00:00
Robert O'Callahan c2bb7d6a82 Make `keep_cache_t` process all modules up-front instead of on-demand 
We will want to query `keep_cache` from parallel threads. If we compute
the results on-demand, that means we need synchronization for cache
access in those queries, which adds complexity and overhead. Instead, prefill
the cache with the status of all relevant modules. Note that this doesn't
actually do more work --- we always consult `keep_cache` for all cells of
all selected modules, so scanning all those cells and determining the kept
status of all dependency modules is always required.

Later in this PR we're going to parallelize `scan_module` itself, and that's also
much easier to do when no other parallel threads are running.
 2026-03-06 02:05:04 +00:00
abhinavputhran 6cd66aed47 setundef: rename process loop variable and respect selection in -init mode 2026-03-05 17:51:01 -05:00
abhinavputhran df283fa1c9 setundef: use selected_processes() per review feedback 2026-03-05 11:22:00 -05:00
abhinavputhran 4e54853e35 setundef: use selected_processes() per review feedback 2026-03-05 11:16:07 -05:00
abhinavputhran 94c789e9c8 setundef: respect selection for cells, processes, and connections 
Previously, setundef would rewrite sigspecs in all cells, processes,
and connections regardless of the active selection. Only modules and
memories were correctly filtered by selection.

Fix by using module->selected_cells() for cells, adding a
module->selected() check for processes, and checking wire selection
on the lhs of each connection before rewriting.

Fixes #5624
 2026-03-04 17:48:35 -05:00
Emil J 0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 
celltypes: compile-time lookup tables for internal cells
 2026-03-04 14:47:57 +00:00
nella 66bd4716cf rtlil use newcelltypes. 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak ecb8b20f62 yosys: use newcelltypes for yosys_celltypes users 2026-03-04 12:39:44 +01:00
Emil J. Tywoniak 4ab22cbb97 abc: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 07ec8708e4 share: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 9e59f05c25 newcelltypes: wrap design celltypes support 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 35ccaa60d7 newcelltypes: TurboCellTypes -> StaticCellTypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 6adc08b0e5 opt_expr: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 3671d577a0 opt_clean: use newcelltypes 2026-03-04 12:22:14 +01:00
Miodrag Milanović 05d1d56b9d
Merge pull request #5704 from apullin/apullin/abc9-no-loops-fix 
abc9: preserve topological-loop asserts with targeted SCC fallback
 2026-03-04 11:09:38 +01:00
Miodrag Milanovic b7d013e6bf Fix help message for equiv passes 2026-03-04 07:46:40 +01:00
Tianji Liu 750d536bba abc: new option to pass ABC read_lib args 2026-03-04 11:24:24 +08:00
Emil J. Tywoniak 6f74c54c02 async2sync: $dffsr has undef output on S&R 2026-03-03 10:34:29 +01:00
Emil J. Tywoniak a53104379d clk2fflogic: $dffsr has undef output on S&R 2026-03-03 10:34:29 +01:00
KrystalDelusion 1d3f9b7905
Merge pull request #5687 from YosysHQ/nella/pdr-doc 
Update help text for rename -witness and write_aiger -ywmap
 2026-03-02 09:29:25 +13:00
Andrew Pullin 5970be33fb abc9: preserve topological-loop asserts with targeted SCC fallback 
A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion.

Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops).

To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion.

Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
 2026-02-26 22:30:32 -08:00
Emil J 5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors 
equiv_induct: error on missing model
 2026-02-25 15:39:31 +01:00
Gus Smith 366f98ae25 ADd clarification 2026-02-23 11:51:54 -08:00
Gus Smith b454582f54 Detect undriven and error/warn 2026-02-20 11:00:59 -08:00
Gus Smith cdc728b6f0 Suggest use of YW when possible 2026-02-20 09:33:51 -08:00
Miodrag Milanović 0ed7c5ad53
Merge pull request #5620 from YosysHQ/lofty/abc9-verify 
abc9: verify post-mapping equivalence by default
 2026-02-20 13:41:11 +01:00
Krystine Sherwin 094481739f memory_libmap: Add -force-params 
Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
 2026-02-20 10:57:00 +00:00
nella 01e89a8f9e Remove cell mentions. 2026-02-18 09:29:35 +01:00
nella 2b4f481850 Cleanup docs. 2026-02-18 09:24:41 +01:00
Emil J. Tywoniak 77f64de997 satgen: move report_missing_model here from equiv.h 2026-02-16 17:01:09 +01:00
Emil J. Tywoniak 81ea922512 sat: use the same cell import warnings as equiv 2026-02-16 16:54:26 +01:00
nella e6e57b33e3 document abc --keep-going pdr [sc-220]. 2026-02-15 09:00:04 +01:00
Gus Smith 8ab105ac28
Merge pull request #4303 from Coloquinte/sat_choice 
Infrastructure to run a Sat solver as a command
 2026-02-11 06:54:53 -08:00
Emil J fba29ea8f1
Merge pull request #5679 from YosysHQ/emil/abc9-remove-liberty 
abc9: remove -liberty
 2026-02-11 12:36:29 +01:00
Emil J. Tywoniak 915912cc76 abc9: remove -dont_use 2026-02-11 11:39:09 +01:00
Emil J. Tywoniak c4094e457b abc9: remove -genlib, -constr 2026-02-11 11:34:54 +01:00
Emil J. Tywoniak 5a46106a46 abc9: remove -liberty 2026-02-11 01:04:50 +01:00
Gus Smith 6f6fa49d3c Typo 2026-02-09 09:05:56 -08:00
Gus Smith 1502e23371 Set solver from scratchpad or command line 2026-02-06 19:26:32 -08:00
Gus Smith f062a0c8d6 Typo 2026-02-06 17:26:08 -08:00
Robert O'Callahan 34f8582725
Sanitize ABC global and per-run temporary directory names in logs 2026-02-07 12:12:13 +13:00
Emil J 1717fa0180
Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift 
opt_expr: fix const lhs of $pow to $shl
 2026-02-05 13:09:01 +01:00
Emil J 8bbde80e02
Merge pull request #5631 from rocallahan/cleanup-compare-signals 
Clean up `compare_signals()` in `opt_clean`
 2026-02-04 17:45:05 +01:00
Emil J 992e64342c
Merge pull request #5621 from rocallahan/remove-opt-sort 
Remove `Design::sort()` calls from optimization passes
 2026-02-04 16:55:56 +01:00
Robert O'Callahan 7326bb7d66
Only reuse ABC processes if we're using yosys-abc and it was built with ENABLE_READLINE 
(cherry picked from commit 5054fd17d7b70f2df97360bb0f0cc1c92a6ffe72)
 2026-02-04 17:19:10 +13:00
Emil J. Tywoniak ed53ff2f49 equiv_simple, equiv_induct: fix config 2026-02-03 18:37:39 +01:00
Emil J. Tywoniak 8d1c1faf82 equiv_simple, equiv_induct: error by default on missing model, add -ignore-unknown-cells 2026-02-03 18:10:29 +01:00
Emil J. Tywoniak 8e73e2a306 sat: add -ignore-unknown-cells instead of -ignore_unknown_cells for consistency 2026-02-03 18:10:29 +01:00
Emil J. Tywoniak 000be270ca equiv_simple, equiv_induct: refactor 2026-02-03 17:54:46 +01:00
Emil J. Tywoniak 3bfeaee8ca opt_expr: fix const lhs of $pow to $shl 2026-02-03 11:59:00 +01:00
KrystalDelusion 414b1b6019
Merge pull request #5651 from rocallahan/abc-error-nonfatal 
Handle ABC nonfatal "Error:" messages
 2026-02-03 08:55:05 +13:00
Miodrag Milanović ac427a79b0
Merge pull request #5644 from nataliakokoromyti/upstream-linux-perf-unistd 
Add unistd header for Linux
 2026-01-30 08:17:43 +01:00
Robert O'Callahan 9c56c93632 Add missing newlines to some 'log_error's 2026-01-30 01:52:19 +00:00
Robert O'Callahan 6af1b5b19c Don't treat ABC 'Error:' output as indicating a fatal error, since these messages aren't necessarily fatal 2026-01-30 01:52:19 +00:00
Emil J a68fee1115
Merge pull request #5646 from rocallahan/debug-design_equal 
Dump module details when `design_equal` fails
 2026-01-29 18:57:24 +01:00
Robert O'Callahan 139c38ecfa Dump module details when design_equal fails 2026-01-28 18:32:12 +00:00
nella 8f6c4d40e4
Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite 
opt_dff restructure.
 2026-01-28 14:41:40 +01:00
Natalia 6a6e5f0f54 linux_perf: only include unistd on Linux 2026-01-28 03:44:33 -08:00
Natalia fc2b7c317f linux_perf: include unistd for POSIX I/O 2026-01-28 03:14:20 -08:00
Emil J 75008b70e5
Merge pull request #5638 from YosysHQ/emil/linux_perf-fix-help 
linux_perf: mark internal, fix help formatting
 2026-01-28 11:06:08 +01:00
Krystine Sherwin 8ed7ac04d8
linux_perf.cc: Fix overlength codeblock 2026-01-28 08:17:56 +13:00
Krystine Sherwin 4031310ebb
linux_perf.cc: Use formatted_help 
Gets the codeblock formatting better.

Also fold the on|off into a single usage.
 2026-01-28 08:10:31 +13:00
Gus Smith 09ceadfde7
Merge pull request #4269 from povik/icells_not_derived 
Avoid `module_not_derived` on internal cells in techmap result
 2026-01-26 14:48:40 -08:00
Emil J. Tywoniak ef3b2b0380 linux_perf: mark internal, fix help formatting 2026-01-26 22:59:20 +01:00
nella 9367090763 OptDff more accurate ctrl/pattern desc. 2026-01-26 22:19:36 +01:00
nella 5803461c24 opt_dff pattern extraction. 2026-01-26 22:10:10 +01:00
Emil J 29a9e42b64
Merge pull request #5628 from rocallahan/linux-perf-ctl 
Add `linux_perf` command to turn Linux perf recording on and off.
 2026-01-26 19:32:55 +01:00
nella 8576055dea Fix tests. 2026-01-26 18:41:41 +01:00
Emil J 673c8d1ae7
Merge pull request #5615 from rocallahan/remove-used-signals-updates 
Don't update `used_signals` for retained wires in `rmunused_module_signals`.
 2026-01-26 15:47:25 +01:00
nella a75e0b2e92 opt_dff minor cleanup, added tests for comp var. 2026-01-26 14:24:01 +01:00
Robert O'Callahan 32e96605d4 Don't update `used_signals` for retained wires in `rmunused_module_signals`. 
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
 2026-01-24 03:41:18 +00:00
Robert O'Callahan 7d53d64a47 Make the call to `compare_signals()` easier to read. 
The negation here is confusing. The intent of the code is "if `s1` is preferred
over `s2` as the canonical `SigBit` for this signal, make `s1` the canonical `SigBit`
in `assign_map`", so write the code that way instead of "if `s2` is not preferred
over `s1` ...".

This doesn't change any behavior now that `compare_signals()` is a total order,
i.e. `s1` is preferred over `s2`, `s2` is preferred over `s1`, or `s1` and `s2` are equal.
Now, when `s1` and `s2` are equal, we don't call `assign_map.add(s1)`, but that's
already a noop in that case.
 2026-01-24 02:01:05 +00:00
Robert O'Callahan 2468b391bf Make `compare_signals` produce a total order. 
Currently when `s1` and `s2` are different bits of the same wire,
it is possible for both `compare_signals(s1, s2)` and `compare_signals(s2, s1)` to
return false. This means the calling code will call `assign_map.add()` for
both `s1` and `s2`, which doesn't make much sense --- one of `s1` or `s2`
should be consistently preferred.

So fix that by preferring the `SigBit` with the smaller bit offset.
 2026-01-24 02:00:33 +00:00
Emil J f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word 
lut2mux: add -word option
 2026-01-23 17:24:41 +01:00
nella 0e4282d442 Add more opt_dff documentation. 2026-01-23 09:17:14 +01:00
Robert O'Callahan 4f53612725 Add `linux_perf` command to turn Linux perf recording on and off. 
This is extremely useful for profiling specific passes.
 2026-01-23 01:44:57 +00:00
Robert O'Callahan e87bb65956 Move `Design::sort()` calls out of `opt` and `opt_clean` passes into the synth passes that need them. 2026-01-23 01:14:35 +00:00
KrystalDelusion 125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix 
abc: handle ABC script errors instead of hanging
 2026-01-23 07:16:48 +13:00
Emil J 317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon 
Add debugon pass for persistent debug logging
 2026-01-21 17:34:30 +01:00
Emil J 5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree 
Add opt_balance_tree pass
 2026-01-21 17:34:08 +01:00
nella f6eba53d1f Fix copyright header. 2026-01-21 14:52:19 +01:00
nella 2c12545cf3 opt_dff restructure. 2026-01-21 10:08:44 +01:00
Lofty 5a9d73369a abc9: verify post-mapping equivalence by default 2026-01-20 09:58:35 +00:00
Martin Povišer 90673cb0a2 techmap: Use `-icells` mode of frontend instead of type fixup 2026-01-19 16:49:49 -08:00
Emil J. Tywoniak c3f36afe7f opt_balance_tree: mark experimental 2026-01-19 12:01:25 +01:00
Robert O'Callahan 28c199fbbd Fix warning about unused variable in `dffunmap`. 2026-01-19 03:25:09 +00:00
KrystalDelusion 8da8d681d0
Merge pull request #5544 from YosysHQ/krys/sim_check_eval_err 
Improve error handling in sim
 2026-01-19 09:51:12 +13:00
Natalia ed64df737b Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
Natalia 305b6c81d7 Refine width check to allow Y_WIDTH >= natural width 
Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).

This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
 2026-01-14 14:58:53 -08:00
Natalia 60ac3670cb Fix truncation issue in opt_balance_tree pass 
Only allow rebalancing of cells with "natural" output widths (no truncation).
This prevents equivalence failures when moving operands between adders
with different intermediate truncation points.

For each operation type, the natural width is:
- Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
- Multiplication: A_WIDTH + B_WIDTH
- Logic ops: max(A_WIDTH, B_WIDTH)

Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit
intermediate wire was intentionally truncating adder results, and
rebalancing would change where that truncation occurred.
 2026-01-14 13:14:56 -08:00
Natalia Kokoromyti 6aef8ea8ab Add missing <deque> include for MSVC compatibility 2026-01-13 15:31:46 -08:00
nataliakokoromyti 8a596f330a Update lut2mux.cc 2026-01-13 15:02:17 -08:00
nataliakokoromyti 40f9e235de
Update lut2mux.cc 2026-01-13 14:45:46 -08:00
nataliakokoromyti 6a93a94d9f
fix line 2026-01-13 14:44:51 -08:00
nataliakokoromyti c305c426eb
restore extra_args 2026-01-13 14:43:52 -08:00
Natalia Kokoromyti 8b6925c5b0 Add opt_balance_tree pass for timing optimization 
This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.

The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.

Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases

Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
 2026-01-13 14:20:11 -08:00
Emil J. Tywoniak 8e2038c419 Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
Miodrag Milanović 51b210c93c
Merge pull request #5600 from YosysHQ/fix_musllinux 
musllinux fix so wheels build can work
 2026-01-13 07:08:04 +01:00
Emil J cc25ccfcd7
Merge pull request #5559 from nataliakokoromyti/upstream-lut2bmux 
add lut2bmux
 2026-01-12 16:09:13 +01:00
Miodrag Milanovic b3b71df07c musllinux fix so wheels build can work 2026-01-12 15:38:45 +01:00
Miodrag Milanović 72690062a1
Merge pull request #5599 from YosysHQ/musllinux_fix 
musllinux fix so wheels build can work
 2026-01-12 14:00:00 +01:00
Emil J f193dd0a28
Merge pull request #5594 from rocallahan/sdc-workaround 
Check for missing port in SDC code to work around compiler bug
 2026-01-12 11:22:25 +01:00
Miodrag Milanovic 2b12b74121 musllinux fix so wheels build can work 2026-01-11 15:23:38 +01:00
Robert O'Callahan 37347aacb2 Check for missing port in SDC code 
I am getting weird crashes on `main` in `tests/sdc/alu_sub.ys` which I traced to a null `Wire*`
in `SdcObjects::constrained_ports`. The null `Wire*` is being set in the `SdcObjects`
constructor. I don't understand what's going on here, so I added this check to detect the
missing wire early ... and that made the crash go away. Compiler bug maybe? I have
`Debian clang version 19.1.7 (3+build5)`, default build configuration.

Anyway this code seems fine to have.
 2026-01-10 04:00:17 +00:00
KrystalDelusion cc3d569ade
Merge pull request #5591 from YosysHQ/krys/clean_empty_switch 
Improve handling of empty switches
 2026-01-09 11:52:27 +13:00
Robert O'Callahan 8da919587d Parallelize `opt_merge`. 
I'm not sure why but this is actually faster than existing `opt_merge` even with
YOSYS_MAX_THREADS=1, for the jpeg synthesis test. 16.0s before, 15.5s after for
end-to-end synthesis.
 2026-01-08 04:21:39 +00:00
Roland Coeurjoly f1fc704c84 abc: handle ABC script errors instead of hanging 2026-01-07 23:46:33 +01:00
Krystine Sherwin c0e29ef57c
proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
Emil J 0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz 
Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
 2026-01-06 20:07:31 +01:00
Emil J 5c630a366d
Merge pull request #5555 from rocallahan/defer-redirects 
Defer redirecting cell outputs when merging cells in `opt_merge` untill after we've done a full pass over the cells.
 2026-01-06 18:48:16 +01:00
Robert O'Callahan 042ec1cf60 Defer redirecting cell outputs when merging cells in `opt_merge` until after we've done a full pass over the cells. 
This avoids changing `assign_map` and `initvals`, which are inputs to the hash function for `known_cells`,
while `known_cells` exists. Changing the hash function for a hashtable while it exists leads to
confusing behavior. That also means the exact behavior of `opt_merge` cannot be reproduced by a
parallel implementation.
 2026-01-06 16:21:48 +00:00
Natalia 11b0e7ad92 add lut2bmux 2026-01-06 14:48:16 +01:00
Miodrag Milanović aa9991d3ee
Merge pull request #5571 from YosysHQ/micko/warning 
remove unused variable
 2025-12-23 16:32:10 +01:00
Miodrag Milanovic 4bc4e4eb41 remove unused variable 2025-12-23 15:47:35 +01:00
Natalia 721b504479 lut2mux: add -word option and test 2025-12-23 05:57:40 -08:00
Miodrag Milanović 09f9e0e8d1
Merge pull request #5568 from rocallahan/abc-spawn-errno 
Print `errno` to help diagnose failure to spawn ABC
 2025-12-23 08:09:14 +01:00
Robert O'Callahan 0e61f57458 Print errno to help diagnose failure to spawn ABC 2025-12-22 21:58:15 +00:00
N. Engelhardt d5b38af4a7
Merge pull request #5550 from YosysHQ/nak/dont_merge_properties 2025-12-22 16:54:43 +01:00
Robert O'Callahan 48cdb499f2 Remove `IdString::id_string()`. 
This was needed for the short time when `ID()` could return a value of `StaticIdString`.
That is no longer a problem.
 2025-12-22 01:57:30 +00:00
Robert O'Callahan 46cb05c471 Pass IdString by value instead of by const reference. 
When IdString refcounting was expensive, it made sense to pass it by const reference
instead of by value, to avoid refcount churn. Now that IdString is not refcounted,
it's slightly more efficient to pass it by value.
 2025-12-22 01:52:59 +00:00
Robert O'Callahan 914e14946d Implement design_equal command 2025-12-21 21:47:40 +00:00
N. Engelhardt 45d654e2d7 avoid merging formal properties 2025-12-17 20:25:24 +01:00
Krystine Sherwin 5b317ee03c
sim.cc: Check eval err 
Some cells (e.g. $macc_v2) are marked evaluable, but will raise an abort if called with `CellTypes::eval()`.
Instead of falling through to the abort, we can pass a pointer to a boolean to check for errors.
Use said check to catch `CellTypes::eval()` errors and treat them as unevaluable but otherwise continue.
Reflows the series of if checks into `if ... else if ... else` so that we can check for errors and set state in one place.
 2025-12-15 12:08:07 +13:00
Krystine Sherwin 9d3d8bf502
Switch posix_spawn to posix_spawnp 2025-12-15 09:40:04 +13:00
Emil J f003eca615
Merge pull request #5526 from YosysHQ/emil/fix-cellaigs-function-arg-eval-order 
cellaigs: fix function argument evaluation order
 2025-12-12 10:00:09 +01:00
Robert O'Callahan 638e904f91 Remove cover() coverage tracking 2025-12-04 16:27:13 +01:00
Krystine Sherwin 9ec361beab
test_cell.cc: Generate .aag for all compatible cells 
Skips (with warning) on cells that didn't convert to avoid `write_aiger` from raising an error.
 2025-12-02 14:03:36 +13:00
Emil J 9871e9b17e
Merge pull request #5496 from YosysHQ/emil/liberty-flop-loops 
read_liberty: support loopy retention cells
 2025-12-01 22:50:20 +01:00
Emil J 510f9ef63d
Merge pull request #5499 from mikesinouye/abc_new 
Enable abc_new pass when not in NDEBUG
 2025-11-24 16:57:29 +01:00
Emil J. Tywoniak e8cbc92462 abc_new: sorted -> is_sorted 2025-11-24 11:46:09 +01:00
Robert O'Callahan 53614a37a1 Use `Tcl_Size` instead of `int` to fix build errors 
Fixes these build errors I'm getting locally with `tcl-devel-9.0.0-7.fc42.x86_64`.
I guess Tcl 9 broke this.

```
passes/cmds/sdc/sdc.cc:438:6: error: no matching function for call to 'Tcl_ListObjLength'
  438 |         if (Tcl_ListObjLength(interp, listObj, &listLength) == TCL_OK) {
      |             ^~~~~~~~~~~~~~~~~
/usr/include/tclDecls.h:1788:13: note: candidate function not viable: no known conversion from 'int *' to 'Tcl_Size *' (aka 'long *') for 3rd argument
 1788 | EXTERN int              Tcl_ListObjLength(Tcl_Interp *interp,
      |                         ^
 1789 |                                 Tcl_Obj *listPtr, Tcl_Size *lengthPtr);
      |                                                   ~~~~~~~~~~~~~~~~~~~
passes/cmds/sdc/sdc.cc:446:8: error: no matching function for call to 'Tcl_ListObjLength'
  446 |                         if (Tcl_ListObjLength(interp, subListObj, &subListLength) == TCL_OK) {
      |                             ^~~~~~~~~~~~~~~~~
/usr/include/tclDecls.h:1788:13: note: candidate function not viable: no known conversion from 'int *' to 'Tcl_Size *' (aka 'long *') for 3rd argument
 1788 | EXTERN int              Tcl_ListObjLength(Tcl_Interp *interp,
      |                         ^
 1789 |                                 Tcl_Obj *listPtr, Tcl_Size *lengthPtr);
      |                                                   ~~~~~~~~~~~~~~~~~~~
```
 2025-11-24 18:46:56 +13:00
Mike Inouye 615e338acd
Fix abc_new pass when not in NDEBUG 2025-11-21 14:10:05 -08:00
Robert O'Callahan e33ca17388 Force a newline to appear before YOSYS_ABC_DONE 2025-11-21 03:50:07 +00:00
Emil J. Tywoniak b3112bf025 filterlib: prefer using precedence over unsynthesizable verilog 2025-11-21 00:43:54 +01:00
Emil J. Tywoniak 6eb9e823e0 sdc: use Tcl memory management functionality 2025-11-20 00:21:15 +01:00
Emil J 2eff366e8c
Merge branch 'main' into emil/sdc_expand 2025-11-19 16:29:37 +01:00
Emil J. Tywoniak 920f4793fb sdc: error on unknown getters 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak 229123eb87 sdc: disable without YOSYS_ENABLE_TCL 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak 033a2d5a67 sdc: remove vestigial code for tracked constraint followup work 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak f56e121ddb sdc: add help 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak 650392d4ec sdc: specialize stubs for the call graph 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak 224ed524fa sdc: move to directory 2025-11-19 15:26:01 +01:00
Emil J. Tywoniak 94dd248dfb sdc: graph mode only 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 8a54e51300 sdc: add -keep_hierarchy 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak d4228efae8 sdc: keep_hiearchy 2025-11-19 15:25:24 +01:00
Emil Jiří Tywoniak 075237f73b sdc: refactor more 2025-11-19 15:25:24 +01:00
Emil Jiří Tywoniak 48ff9d4950 sdc: refactor find_matching 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak ae1235210d sdc: functional graph 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak c6491629d8 sdc: start graph 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 24a6412ea8 sdc: bit selections 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 21c68e0022 sdc: unknown handler experiment 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 420a083d9b sdc: simple mode, remove per-tool stubs 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 834125a076 sdc: return resolved patterns 2025-11-19 15:25:24 +01:00