Merge pull request #5526 from YosysHQ/emil/fix-cellaigs-function-arg-eval-order

cellaigs: fix function argument evaluation order
This commit is contained in:
Emil J 2025-12-12 10:00:09 +01:00 committed by GitHub
commit f003eca615
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45 changed files with 820 additions and 19 deletions

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@ -185,50 +185,68 @@ struct AigMaker
int or_gate(int A, int B)
{
return nand_gate(not_gate(A), not_gate(B));
int not_a = not_gate(A);
int not_b = not_gate(B);
return nand_gate(not_a, not_b);
}
int nor_gate(int A, int B)
{
return and_gate(not_gate(A), not_gate(B));
int not_a = not_gate(A);
int not_b = not_gate(B);
return and_gate(not_a, not_b);
}
int xor_gate(int A, int B)
{
return nor_gate(and_gate(A, B), nor_gate(A, B));
int a_and_b = and_gate(A, B);
int a_nor_b = nor_gate(A, B);
return nor_gate(a_and_b, a_nor_b);
}
int xnor_gate(int A, int B)
{
return or_gate(and_gate(A, B), nor_gate(A, B));
int a_and_b = and_gate(A, B);
int a_nor_b = nor_gate(A, B);
return or_gate(a_and_b, a_nor_b);
}
int andnot_gate(int A, int B)
{
return and_gate(A, not_gate(B));
int not_b = not_gate(B);
return and_gate(A, not_b);
}
int ornot_gate(int A, int B)
{
return or_gate(A, not_gate(B));
int not_b = not_gate(B);
return or_gate(A, not_b);
}
int mux_gate(int A, int B, int S)
{
return or_gate(and_gate(A, not_gate(S)), and_gate(B, S));
int not_s = not_gate(S);
int a_active = and_gate(A, not_s);
int b_active = and_gate(B, S);
return or_gate(a_active, b_active);
}
vector<int> adder(const vector<int> &A, const vector<int> &B, int carry, vector<int> *X = nullptr, vector<int> *CO = nullptr)
vector<int> adder(const vector<int> &A, const vector<int> &B, int carry_in, vector<int> *X = nullptr, vector<int> *CO = nullptr)
{
vector<int> Y(GetSize(A));
log_assert(GetSize(A) == GetSize(B));
for (int i = 0; i < GetSize(A); i++) {
Y[i] = xor_gate(xor_gate(A[i], B[i]), carry);
carry = or_gate(and_gate(A[i], B[i]), and_gate(or_gate(A[i], B[i]), carry));
int a_xor_b = xor_gate(A[i], B[i]);
int a_or_b = or_gate(A[i], B[i]);
int a_and_b = and_gate(A[i], B[i]);
Y[i] = xor_gate(a_xor_b, carry_in);
int tmp = and_gate(a_or_b, carry_in);
int carry_out = or_gate(a_and_b, tmp);
if (X != nullptr)
X->at(i) = xor_gate(A[i], B[i]);
X->at(i) = a_xor_b;
if (CO != nullptr)
CO->at(i) = carry;
CO->at(i) = carry_out;
carry_in = carry_out;
}
return Y;
}
@ -307,13 +325,13 @@ Aig::Aig(Cell *cell)
int A = mk.inport(ID::A, i);
int B = mk.inport(ID::B, i);
int Y = cell->type.in(ID($and), ID($_AND_)) ? mk.and_gate(A, B) :
cell->type.in(ID($_NAND_)) ? mk.nand_gate(A, B) :
cell->type.in(ID($_NAND_)) ? mk.nand_gate(A, B) :
cell->type.in(ID($or), ID($_OR_)) ? mk.or_gate(A, B) :
cell->type.in(ID($_NOR_)) ? mk.nor_gate(A, B) :
cell->type.in(ID($_NOR_)) ? mk.nor_gate(A, B) :
cell->type.in(ID($xor), ID($_XOR_)) ? mk.xor_gate(A, B) :
cell->type.in(ID($xnor), ID($_XNOR_)) ? mk.xnor_gate(A, B) :
cell->type.in(ID($_ANDNOT_)) ? mk.andnot_gate(A, B) :
cell->type.in(ID($_ORNOT_)) ? mk.ornot_gate(A, B) : -1;
cell->type.in(ID($_ANDNOT_)) ? mk.andnot_gate(A, B) :
cell->type.in(ID($_ORNOT_)) ? mk.ornot_gate(A, B) : -1;
mk.outport(Y, ID::Y, i);
}
goto optimize;
@ -465,7 +483,8 @@ Aig::Aig(Cell *cell)
int B = mk.inport(ID::B);
int C = mk.inport(ID::C);
int D = mk.inport(ID::D);
int Y = mk.nor_gate(mk.and_gate(A, B), mk.and_gate(C, D));
int a_and_b = mk.and_gate(A, B);
int Y = mk.nor_gate(a_and_b, mk.and_gate(C, D));
mk.outport(Y, ID::Y);
goto optimize;
}
@ -476,7 +495,8 @@ Aig::Aig(Cell *cell)
int B = mk.inport(ID::B);
int C = mk.inport(ID::C);
int D = mk.inport(ID::D);
int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D));
int a_or_b = mk.or_gate(A, B);
int Y = mk.nand_gate(a_or_b, mk.or_gate(C, D));
mk.outport(Y, ID::Y);
goto optimize;
}

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@ -1143,7 +1143,29 @@ struct TestCellPass : public Pass {
else
uut = create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv);
if (!write_prefix.empty()) {
Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix, cell_type.c_str()+1, i));
string writer = "write_rtlil";
string suffix = "il";
if (techmap_cmd.compare("aigmap") == 0) {
// try to convert to aiger
Pass::call(design, techmap_cmd);
bool is_unconverted = false;
for (auto *mod : design->selected_modules())
for (auto *cell : mod->selected_cells())
if (!cell->type.in(ID::$_NOT_, ID::$_AND_)) {
is_unconverted = true;
break;
}
if (is_unconverted) {
// skip unconverted cells
log_warning("Skipping %s\n", cell_type);
delete design;
break;
} else {
writer = "write_aiger -ascii";
suffix = "aag";
}
}
Pass::call(design, stringf("%s %s_%s_%05d.%s", writer, write_prefix, cell_type.c_str()+1, i, suffix));
} else if (edges) {
Pass::call(design, "dump gold");
run_edges_test(design, verbose);

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@ -1,2 +1,3 @@
/*_ref.v
/neg.out/
/gate/

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@ -0,0 +1,7 @@
aag 3 2 0 1 1
2
4
6
6 5 2
c
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@ -0,0 +1,7 @@
aag 3 2 0 1 1
2
4
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6 4 2
c
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@ -0,0 +1,9 @@
aag 5 3 0 1 2
2
4
6
10
8 4 2
10 9 7
c
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@ -0,0 +1,11 @@
aag 7 4 0 1 3
2
4
6
8
14
10 4 2
12 8 6
14 13 11
c
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@ -0,0 +1,5 @@
aag 1 1 0 1 0
2
2
c
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@ -0,0 +1,10 @@
aag 6 3 0 1 3
2
4
6
13
8 7 2
10 6 4
12 11 9
c
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@ -0,0 +1,7 @@
aag 3 2 0 1 1
2
4
7
6 4 2
c
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@ -0,0 +1,10 @@
aag 6 3 0 1 3
2
4
6
12
8 7 2
10 6 4
12 11 9
c
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@ -0,0 +1,7 @@
aag 3 2 0 1 1
2
4
6
6 5 3
c
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@ -0,0 +1,5 @@
aag 1 1 0 1 0
2
3
c
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@ -0,0 +1,9 @@
aag 5 3 0 1 2
2
4
6
11
8 5 3
10 9 6
c
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@ -0,0 +1,11 @@
aag 7 4 0 1 3
2
4
6
8
15
10 5 3
12 9 7
14 13 11
c
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@ -0,0 +1,7 @@
aag 3 2 0 1 1
2
4
7
6 4 3
c
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@ -0,0 +1,7 @@
aag 3 2 0 1 1
2
4
7
6 5 3
c
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@ -0,0 +1,9 @@
aag 5 2 0 1 3
2
4
11
6 4 2
8 5 3
10 9 7
c
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@ -0,0 +1,9 @@
aag 5 2 0 1 3
2
4
10
6 4 2
8 5 3
10 9 7
c
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@ -0,0 +1,62 @@
aag 51 4 0 8 47
2
4
6
8
14
30
42
54
66
78
90
102
10 6 2
12 7 3
14 13 11
16 6 2
18 8 4
20 9 5
22 21 19
24 22 16
26 21 19
28 27 11
30 29 25
32 21 16
34 33 19
36 35 22
38 33 19
40 38 27
42 41 37
44 35 21
46 45 19
48 47 22
50 45 19
52 50 27
54 53 49
56 47 21
58 57 19
60 59 22
62 57 19
64 62 27
66 65 61
68 59 21
70 69 19
72 71 22
74 69 19
76 74 27
78 77 73
80 71 21
82 81 19
84 83 22
86 81 19
88 86 27
90 89 85
92 83 21
94 93 19
96 95 22
98 93 19
100 98 27
102 101 97
c
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@ -0,0 +1,45 @@
aag 33 5 0 9 28
2
4
6
8
10
27
35
36
38
40
8
48
58
66
12 8 6
14 9 7
16 15 13
18 16 2
20 15 13
22 21 3
24 23 10
26 25 19
28 8 4
30 9 5
32 31 27
34 33 29
36 35 8
38 23 19
40 31 29
42 38 10
44 23 19
46 45 11
48 47 43
50 40 27
52 31 29
54 25 19
56 54 53
58 57 51
60 35 8
62 33 29
64 62 9
66 65 61
c
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@ -0,0 +1,28 @@
aag 17 11 0 8 6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
34
34
24 14 2
26 16 4
28 18 6
30 20 8
32 22 10
34 22 12
c
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@ -0,0 +1,15 @@
aag 6 6 0 6 0
2
4
6
8
10
12
2
4
6
8
10
12
c
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@ -0,0 +1,46 @@
aag 38 11 0 5 27
2
4
6
8
10
12
14
16
18
20
22
76
0
0
0
0
24 10 2
26 11 3
28 27 25
30 12 4
32 13 5
34 33 31
36 35 29
38 14 6
40 15 7
42 41 39
44 43 36
46 16 8
48 17 9
50 49 47
52 51 44
54 18 8
56 19 9
58 57 55
60 59 52
62 20 8
64 21 9
66 65 63
68 67 60
70 22 8
72 23 9
74 73 71
76 75 68
c
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@ -0,0 +1,9 @@
aag 3 2 0 3 1
2
4
7
0
0
6 4 3
c
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@ -0,0 +1,48 @@
aag 43 10 0 2 33
2
4
6
8
10
12
14
16
18
20
86
0
22 20 7
24 21 6
26 25 23
28 18 7
30 16 7
32 14 7
34 12 7
36 10 5
38 9 2
40 8 3
42 41 38
44 11 4
46 45 43
48 47 37
50 13 6
52 51 49
54 53 35
56 15 6
58 57 55
60 59 33
62 17 6
64 63 61
66 65 31
68 19 6
70 69 67
72 71 29
74 73 25
76 75 23
78 77 26
80 25 23
82 75 23
84 82 81
86 85 79
c
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@ -0,0 +1,52 @@
aag 47 12 0 2 35
2
4
6
8
10
12
14
16
18
20
22
24
94
0
26 25 8
28 24 9
30 29 27
32 23 8
34 21 8
36 19 8
38 17 8
40 15 6
42 13 4
44 11 2
46 12 5
48 47 44
50 49 43
52 14 7
54 53 51
56 55 41
58 16 9
60 59 57
62 61 39
64 18 9
66 65 63
68 67 37
70 20 9
72 71 69
74 73 35
76 22 9
78 77 75
80 79 33
82 81 29
84 83 27
86 85 30
88 29 27
90 83 27
92 90 89
94 93 87
c
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@ -0,0 +1,30 @@
aag 21 11 0 6 10
2
4
6
8
10
12
14
16
18
20
22
42
0
0
0
0
0
24 5 3
26 24 7
28 26 9
30 28 11
32 30 13
34 17 15
36 34 19
38 36 21
40 38 23
42 41 33
c
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@ -0,0 +1,15 @@
aag 7 4 0 5 3
2
4
6
8
14
0
0
0
0
10 5 3
12 10 7
14 12 9
c
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@ -0,0 +1,29 @@
aag 21 11 0 5 10
2
4
6
8
10
12
14
16
18
20
22
43
0
0
0
0
24 5 3
26 24 7
28 26 9
30 28 11
32 30 13
34 17 15
36 34 19
38 36 21
40 38 23
42 40 32
c
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@ -0,0 +1,43 @@
aag 34 9 0 6 25
2
4
6
8
10
12
14
16
18
68
0
0
0
0
0
20 19 10
22 18 11
24 23 21
26 19 8
28 17 6
30 15 4
32 12 3
34 13 2
36 35 32
38 14 5
40 39 37
42 41 31
44 16 7
46 45 43
48 47 29
50 18 9
52 51 49
54 53 27
56 55 23
58 57 21
60 59 24
62 23 21
64 57 21
66 64 63
68 67 61
c
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@ -0,0 +1,10 @@
aag 6 3 0 1 3
2
4
6
13
8 7 2
10 6 4
12 11 9
c
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@ -0,0 +1,40 @@
aag 29 10 0 8 19
2
4
6
8
10
12
14
16
18
20
59
0
0
0
0
0
0
0
22 12 2
24 13 3
26 25 23
28 14 4
30 15 5
32 31 29
34 33 27
36 16 6
38 17 7
40 39 37
42 41 34
44 18 8
46 19 9
48 47 45
50 49 42
52 20 10
54 21 11
56 55 53
58 57 50
c
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@ -0,0 +1,11 @@
aag 6 6 0 2 0
2
4
6
8
10
12
3
5
c
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@ -0,0 +1,11 @@
aag 6 4 0 2 2
2
4
6
8
11
13
10 5 3
12 7 3
c
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@ -0,0 +1,9 @@
aag 1 1 0 5 0
2
2
2
2
2
2
c
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@ -0,0 +1,7 @@
aag 1 1 0 3 0
2
2
0
0
c
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@ -0,0 +1,13 @@
aag 7 4 0 3 3
2
4
6
8
15
0
0
10 5 3
12 10 7
14 12 9
c
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@ -0,0 +1,7 @@
aag 3 2 0 1 1
2
4
7
6 5 3
c
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@ -0,0 +1,30 @@
aag 25 6 0 2 19
2
4
6
8
10
12
51
0
14 4 2
16 5 3
18 17 15
20 18 6
22 17 15
24 23 7
26 25 21
28 26 8
30 25 21
32 31 9
34 33 29
36 34 10
38 33 29
40 39 11
42 41 37
44 42 12
46 41 37
48 47 13
50 49 45
c
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@ -0,0 +1,9 @@
aag 5 2 0 1 3
2
4
10
6 4 2
8 5 3
10 9 7
c
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@ -0,0 +1,20 @@
aag 16 13 0 1 3
2
4
6
8
10
12
14
16
18
20
22
24
26
33
28 17 2
30 16 3
32 31 29
c
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@ -0,0 +1,17 @@
aag 10 4 0 4 6
2
4
6
8
15
21
21
21
10 6 2
12 7 3
14 13 11
16 8 4
18 9 5
20 19 17
c
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@ -0,0 +1,12 @@
aag 8 5 0 1 3
2
4
6
8
10
16
12 8 2
14 9 3
16 15 13
c
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@ -58,3 +58,13 @@ for y in *.ys; do
echo "Running $y."
../../yosys -ql ${y%.*}.log $y
done
# compare aigmap with reference
# make gold with: rm gold/*; yosys --no-version -p "test_cell -aigmap -w gold/ -n 1 -s 1 all"
rm -rf gate; mkdir gate
../../yosys --no-version -p "test_cell -aigmap -w gate/ -n 1 -s 1 all"
(
set -o pipefail
diff --brief gold gate | tee aigmap.err
)
rm aigmap.err