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async2sync: explain dffsr control signal variable polarity

This commit is contained in:
Emil J. Tywoniak 2026-03-09 20:18:56 +01:00
parent 43ef4d2901
commit 498cb79abe
1 changed files with 3 additions and 0 deletions
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3
passes/sat/async2sync.cc
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@ -178,6 +178,9 @@ struct Async2syncPass : public Pass {
sig_clr = module->NotGate(NEW_ID, sig_clr);
}
// At this point, sig_set and sig_clr are now unconditionally
// active-high, and sig_clr_inv is inverted sig_clr
SigSpec set_and_clr;
if (!ff.is_fine)
set_and_clr = module->And(NEW_ID, sig_set, sig_clr);