mirror of https://github.com/YosysHQ/yosys.git
async2sync: $dffsr has undef output on S&R
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857bc02710
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6f74c54c02
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@ -157,33 +157,49 @@ struct Async2syncPass : public Pass {
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SigSpec sig_set = ff.sig_set;
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SigSpec sig_clr = ff.sig_clr;
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SigSpec sig_clr_inv = ff.sig_clr;
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if (!ff.pol_set) {
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if (!ff.is_fine)
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if (!ff.is_fine || sig_set.size() > 1)
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sig_set = module->Not(NEW_ID, sig_set);
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else
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sig_set = module->NotGate(NEW_ID, sig_set);
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}
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if (ff.pol_clr) {
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if (!ff.is_fine)
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if (!ff.is_fine || sig_clr.size() > 1)
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sig_clr_inv = module->Not(NEW_ID, sig_clr);
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else
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sig_clr_inv = module->NotGate(NEW_ID, sig_clr);
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} else {
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if (!ff.is_fine || sig_clr.size() > 1)
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sig_clr = module->Not(NEW_ID, sig_clr);
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else
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sig_clr = module->NotGate(NEW_ID, sig_clr);
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}
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SigSpec set_and_clr;
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if (!ff.is_fine || sig_clr.size() > 1 || sig_set.size() > 1)
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set_and_clr = module->And(NEW_ID, sig_set, sig_clr);
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else
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set_and_clr = module->AndGate(NEW_ID, sig_set, sig_clr);
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if (!ff.is_fine) {
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SigSpec tmp = module->Or(NEW_ID, ff.sig_d, sig_set);
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module->addAnd(NEW_ID, tmp, sig_clr, new_d);
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tmp = module->And(NEW_ID, tmp, sig_clr_inv);
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module->addBwmux(NEW_ID, tmp, Const(State::Sx, ff.width), set_and_clr, new_d);
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tmp = module->Or(NEW_ID, new_q, sig_set);
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module->addAnd(NEW_ID, tmp, sig_clr, ff.sig_q);
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tmp = module->And(NEW_ID, tmp, sig_clr_inv);
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module->addBwmux(NEW_ID, tmp, Const(State::Sx, ff.width), set_and_clr, ff.sig_q);
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} else {
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SigSpec tmp = module->OrGate(NEW_ID, ff.sig_d, sig_set);
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module->addAndGate(NEW_ID, tmp, sig_clr, new_d);
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tmp = module->AndGate(NEW_ID, tmp, sig_clr_inv);
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module->addMuxGate(NEW_ID, tmp, State::Sx, set_and_clr, new_d);
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tmp = module->OrGate(NEW_ID, new_q, sig_set);
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module->addAndGate(NEW_ID, tmp, sig_clr, ff.sig_q);
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tmp = module->AndGate(NEW_ID, tmp, sig_clr_inv);
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module->addMuxGate(NEW_ID, tmp, State::Sx, set_and_clr, ff.sig_q);
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}
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ff.sig_d = new_d;
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