mirror of https://github.com/YosysHQ/yosys.git
setundef: respect selection in -undriven mode
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parent
6cd66aed47
commit
9e666c727f
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@ -310,6 +310,8 @@ struct SetundefPass : public Pass {
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RTLIL::SigSpec sig = undriven_signals.export_all();
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for (auto &c : sig.chunks()) {
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if (!design->selected(module, c.wire))
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continue;
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RTLIL::Wire * wire;
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if (c.wire->width == c.width) {
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wire = c.wire;
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@ -343,6 +345,8 @@ struct SetundefPass : public Pass {
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RTLIL::SigSpec sig = undriven_signals.export_all();
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for (auto &c : sig.chunks()) {
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if (!design->selected(module, c.wire))
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continue;
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RTLIL::SigSpec bits;
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if (worker.next_bit_mode == MODE_ANYSEQ)
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bits = module->Anyseq(NEW_ID, c.width);
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