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Introduce `RmStats` struct to encapsulate removal statistics 

Turns out this is not strictly necessary for this PR but it's
still a good thing to do and makes it clearer that the stats
are not modified in a possibly racy way.
This commit is contained in:
Robert O'Callahan 2026-01-28 19:27:09 +00:00
parent c2bb7d6a82
commit 72a21fe01d
1 changed files with 25 additions and 22 deletions
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47
passes/opt/opt_clean.cc
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@ -146,9 +146,19 @@ static constexpr auto ct_reg = StaticCellTypes::Categories::join(
StaticCellTypes::Compat::mem_ff,
StaticCellTypes::categories.is_anyinit);
NewCellTypes ct_all;
int count_rm_cells, count_rm_wires;
void rmunused_module_cells(Module *module, bool verbose, keep_cache_t &keep_cache)
struct RmStats {
int count_rm_cells = 0;
int count_rm_wires = 0;
void log()
{
if (count_rm_cells > 0 || count_rm_wires > 0)
YOSYS_NAMESPACE_PREFIX log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
}
};
void rmunused_module_cells(Module *module, bool verbose, RmStats &stats, keep_cache_t &keep_cache)
{
SigMap sigmap(module);
dict<IdString, pool<Cell*>> mem2cells;
@ -253,7 +263,7 @@ void rmunused_module_cells(Module *module, bool verbose, keep_cache_t &keep_cach
if (cell->is_builtin_ff())
ffinit.remove_init(cell->getPort(ID::Q));
module->remove(cell);
count_rm_cells++;
stats.count_rm_cells++;
}
for (auto it : mem_unused)
@ -345,7 +355,7 @@ bool check_public_name(RTLIL::IdString id)
return true;
}
bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbose)
bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbose, RmStats &stats)
{
// `register_signals` and `connected_signals` will help us decide later on
// on picking representatives out of groups of connected signals
@ -547,7 +557,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
}
module->remove(del_wires_queue);
count_rm_wires += GetSize(del_wires_queue);
stats.count_rm_wires += GetSize(del_wires_queue);
if (verbose && del_temp_wires_count)
log_debug(" removed %d unused temporary wires.\n", del_temp_wires_count);
@ -637,7 +647,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose)
return did_something;
}
void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool rminit, keep_cache_t &keep_cache)
void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool rminit, RmStats &stats, keep_cache_t &keep_cache)
{
if (verbose)
log("Finding unused cells or wires in module %s..\n", module->name);
@ -694,11 +704,11 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
if (!delcells.empty())
module->design->scratchpad_set_bool("opt.did_something", true);
rmunused_module_cells(module, verbose, keep_cache);
while (rmunused_module_signals(module, purge_mode, verbose)) { }
rmunused_module_cells(module, verbose, stats, keep_cache);
while (rmunused_module_signals(module, purge_mode, verbose, stats)) { }
if (rminit && rmunused_module_init(module, verbose))
while (rmunused_module_signals(module, purge_mode, verbose)) { }
while (rmunused_module_signals(module, purge_mode, verbose, stats)) { }
}
struct OptCleanPass : public Pass {
@ -746,15 +756,11 @@ struct OptCleanPass : public Pass {
ct_all.setup(design);
count_rm_cells = 0;
count_rm_wires = 0;
RmStats stats;
for (auto module : selected_modules) {
rmunused_module(module, purge_mode, true, true, keep_cache);
rmunused_module(module, purge_mode, true, true, stats, keep_cache);
}
if (count_rm_cells > 0 || count_rm_wires > 0)
log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
stats.log();
design->optimize();
design->check();
@ -806,16 +812,13 @@ struct CleanPass : public Pass {
ct_all.setup(design);
count_rm_cells = 0;
count_rm_wires = 0;
RmStats stats;
for (auto module : selected_modules) {
rmunused_module(module, purge_mode, ys_debug(), true, keep_cache);
rmunused_module(module, purge_mode, ys_debug(), true, stats, keep_cache);
}
log_suppressed();
if (count_rm_cells > 0 || count_rm_wires > 0)
log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
stats.log();
design->optimize();
design->check();