mirror of https://github.com/YosysHQ/yosys.git
opt_clean: refactor
This commit is contained in:
Emil J. Tywoniak
Robert O'Callahan
parent
1260fda83a
commit
70cc2d67fd
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@ -42,7 +42,7 @@ runs:
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if: runner.os == 'Linux' && inputs.get-build-deps == 'true'
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uses: awalsh128/cache-apt-pkgs-action@v1.6.0
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with:
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packages: bison clang flex libffi-dev libfl-dev libreadline-dev pkg-config tcl-dev zlib1g-dev libgtest-dev
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packages: bison clang flex libffi-dev libfl-dev libreadline-dev pkg-config tcl-dev zlib1g-dev libgtest-dev libgmock-dev
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version: ${{ inputs.runs-on }}-buildys
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- name: Linux docs dependencies
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@ -9,7 +9,6 @@ OBJS += passes/opt/opt_muxtree.o
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OBJS += passes/opt/opt_reduce.o
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OBJS += passes/opt/opt_dff.o
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OBJS += passes/opt/opt_share.o
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OBJS += passes/opt/opt_clean.o
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OBJS += passes/opt/opt_expr.o
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OBJS += passes/opt/opt_hier.o
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@ -40,3 +39,5 @@ PEEPOPT_PATTERN += passes/opt/peepopt_formal_clockgateff.pmg
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passes/opt/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
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$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^)
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endif
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include $(YOSYS_SRC)/passes/opt/opt_clean/Makefile.inc
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,10 @@
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OPT_CLEAN_OBJS =
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OPT_CLEAN_OBJS += passes/opt/opt_clean/cells_all.o
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OPT_CLEAN_OBJS += passes/opt/opt_clean/cells_temp.o
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OPT_CLEAN_OBJS += passes/opt/opt_clean/wires.o
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OPT_CLEAN_OBJS += passes/opt/opt_clean/inits.o
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OPT_CLEAN_OBJS += passes/opt/opt_clean/opt_clean.o
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$(OPT_CLEAN_OBJS): passes/opt/opt_clean/opt_clean.h
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OBJS += $(OPT_CLEAN_OBJS)
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@ -0,0 +1,373 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/ffinit.h"
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#include "kernel/yosys_common.h"
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#include "passes/opt/opt_clean/opt_clean.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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unsigned int hash_bit(const SigBit &bit) {
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return static_cast<unsigned int>(hash_ops<SigBit>::hash(bit).yield());
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}
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SigMap wire_sigmap(const RTLIL::Module* mod) {
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SigMap map;
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for (auto &it : mod->connections_) {
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for (int i = 0; i < GetSize(it.second); i++) {
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if (it.second[i].wire != nullptr)
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map.add(it.first[i], it.second[i]);
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}
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}
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return map;
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}
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struct WireDrivers;
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// Maps from a SigBit to a unique driver cell.
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struct WireDriver {
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using Accumulated = WireDrivers;
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SigBit bit;
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int driver_cell;
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};
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// Maps from a SigBit to one or more driver cells.
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struct WireDrivers {
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WireDrivers() : driver_cell(0) {}
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WireDrivers(WireDriver driver) : bit(driver.bit), driver_cell(driver.driver_cell) {}
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WireDrivers(SigBit bit) : bit(bit), driver_cell(0) {}
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WireDrivers(WireDrivers &&other) = default;
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class const_iterator {
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public:
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const_iterator(const WireDrivers &drivers, bool end)
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: driver_cell(drivers.driver_cell), in_extra_cells(end) {
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if (drivers.extra_driver_cells) {
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if (end) {
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extra_it = drivers.extra_driver_cells->end();
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} else {
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extra_it = drivers.extra_driver_cells->begin();
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}
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}
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}
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int operator*() const {
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if (in_extra_cells)
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return **extra_it;
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return driver_cell;
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}
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const_iterator& operator++() {
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if (in_extra_cells)
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++*extra_it;
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else
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in_extra_cells = true;
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return *this;
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}
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bool operator!=(const const_iterator &other) const {
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return !(*this == other);
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}
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bool operator==(const const_iterator &other) const {
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return in_extra_cells == other.in_extra_cells &&
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extra_it == other.extra_it;
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}
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private:
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std::optional<pool<int>::iterator> extra_it;
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int driver_cell;
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bool in_extra_cells;
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};
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const_iterator begin() const { return const_iterator(*this, false); }
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const_iterator end() const { return const_iterator(*this, true); }
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SigBit bit;
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int driver_cell;
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std::unique_ptr<pool<int>> extra_driver_cells;
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};
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struct WireDriversKeyEquality {
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bool operator()(const WireDrivers &a, const WireDrivers &b) const {
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return a.bit == b.bit;
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}
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};
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struct WireDriversCollisionHandler {
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void operator()(WireDrivers &incumbent, WireDrivers &new_value) const {
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log_assert(new_value.extra_driver_cells == nullptr);
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if (!incumbent.extra_driver_cells)
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incumbent.extra_driver_cells.reset(new pool<int>());
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incumbent.extra_driver_cells->insert(new_value.driver_cell);
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}
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};
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using Wire2Drivers = ShardedHashtable<WireDriver, WireDriversKeyEquality, WireDriversCollisionHandler>;
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struct ConflictLogs {
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ShardedVector<std::pair<SigBit, std::string>> logs;
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ConflictLogs(ParallelDispatchThreadPool::Subpool &subpool) : logs(subpool) {}
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void print_warnings(pool<SigBit>& used_raw_bits, const SigMap& wire_map, const RTLIL::Module* mod, CleanRunContext &clean_ctx) {
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if (!logs.empty()) {
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// We could do this in parallel but hopefully this is rare.
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for (auto [_, cell] : mod->cells_) {
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for (auto &[port, sig] : cell->connections()) {
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if (clean_ctx.ct_all.cell_known(cell->type) && !clean_ctx.ct_all.cell_input(cell->type, port))
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continue;
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for (auto raw_bit : wire_map(sig))
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used_raw_bits.insert(raw_bit);
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}
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}
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for (std::pair<SigBit, std::string> &it : logs) {
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if (used_raw_bits.count(it.first))
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log_warning("%s\n", it.second);
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}
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}
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}
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};
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struct CellTraversal {
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ConcurrentWorkQueue<int> queue;
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Wire2Drivers wire2driver;
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dict<std::string, pool<int>> mem2cells;
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CellTraversal(int num_threads) : queue(num_threads), wire2driver(), mem2cells() {}
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};
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struct CellAnalysis {
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ShardedVector<Wire*> keep_wires;
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std::vector<std::atomic<bool>> unused;
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CellAnalysis(AnalysisContext& actx)
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: keep_wires(actx.subpool), unused(actx.mod->cells_size()) {}
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pool<SigBit> analyze_kept_wires(CellTraversal& traversal, const SigMap& sigmap, const SigMap& wire_map, int num_threads) {
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// Also enqueue cells that drive kept wires into cell_queue
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// and mark those cells as used
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// and mark all bits of those wires as used
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pool<SigBit> used_raw_bits;
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int i = 0;
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for (Wire *wire : keep_wires) {
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for (auto bit : sigmap(wire)) {
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const WireDrivers *drivers = traversal.wire2driver.find({{bit}, hash_bit(bit)});
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if (drivers != nullptr)
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for (int cell_index : *drivers)
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if (unused[cell_index].exchange(false, std::memory_order_relaxed)) {
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ThreadIndex fake_thread_index = {i++ % num_threads};
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traversal.queue.push(fake_thread_index, cell_index);
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}
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}
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for (auto raw_bit : SigSpec(wire))
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used_raw_bits.insert(wire_map(raw_bit));
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}
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return used_raw_bits;
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}
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void mark_used_and_enqueue(int cell_idx, ConcurrentWorkQueue<int>& queue, const ParallelDispatchThreadPool::RunCtx &ctx) {
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if (unused[cell_idx].exchange(false, std::memory_order_relaxed))
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queue.push(ctx, cell_idx);
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}
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};
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ConflictLogs explore(CellAnalysis& analysis, CellTraversal& traversal, const SigMap& wire_map, AnalysisContext& actx, CleanRunContext &clean_ctx) {
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ConflictLogs logs(actx.subpool);
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Wire2Drivers::Builder wire2driver_builder(actx.subpool);
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ShardedVector<std::pair<std::string, int>> mem2cells_vector(actx.subpool);
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// Enqueue kept cells into traversal.queue
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// Prepare input cone traversal into traversal.wire2driver
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// Prepare "input cone" traversal from memory to write port or meminit as analysis.mem2cells
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// Also check driver conflicts
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// Also mark cells unused to true unless keep (we override this later)
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actx.subpool.run([&analysis, &traversal, &logs, &wire_map, &mem2cells_vector, &wire2driver_builder, &actx, &clean_ctx](const ParallelDispatchThreadPool::RunCtx &ctx) {
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for (int i : ctx.item_range(actx.mod->cells_size())) {
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Cell *cell = actx.mod->cell_at(i);
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if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2)))
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mem2cells_vector.insert(ctx, {cell->getParam(ID::MEMID).decode_string(), i});
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for (auto &it2 : cell->connections()) {
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if (clean_ctx.ct_all.cell_known(cell->type) && !clean_ctx.ct_all.cell_output(cell->type, it2.first))
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continue;
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for (auto raw_bit : it2.second) {
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if (raw_bit.wire == nullptr)
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continue;
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auto bit = actx.assign_map(raw_bit);
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if (bit.wire == nullptr && clean_ctx.ct_all.cell_known(cell->type)) {
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std::string msg = stringf("Driver-driver conflict "
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"for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
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log_signal(raw_bit), cell->name.unescape(), it2.first.unescape(), log_signal(bit), actx.mod->name.unescape());
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logs.logs.insert(ctx, {wire_map(raw_bit), msg});
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}
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if (bit.wire != nullptr)
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wire2driver_builder.insert(ctx, {{bit, i}, hash_bit(bit)});
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}
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}
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bool keep = clean_ctx.keep_cache.query(cell);
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analysis.unused[i].store(!keep, std::memory_order_relaxed);
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if (keep)
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traversal.queue.push(ctx, i);
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}
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for (int i : ctx.item_range(actx.mod->wires_size())) {
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Wire *wire = actx.mod->wire_at(i);
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if (wire->port_output || wire->get_bool_attribute(ID::keep))
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analysis.keep_wires.insert(ctx, wire);
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}
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});
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// Finish by merging per-thread collected data
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actx.subpool.run([&wire2driver_builder](const ParallelDispatchThreadPool::RunCtx &ctx) {
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wire2driver_builder.process(ctx);
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});
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traversal.wire2driver = wire2driver_builder;
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for (std::pair<std::string, int> &mem2cell : mem2cells_vector)
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traversal.mem2cells[mem2cell.first].insert(mem2cell.second);
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return logs;
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}
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struct MemAnalysis {
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std::vector<std::atomic<bool>> unused;
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dict<std::string, int> indices;
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MemAnalysis(const RTLIL::Module* mod) : unused(mod->memories.size()), indices() {
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for (int i = 0; i < GetSize(mod->memories); ++i) {
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indices[mod->memories.element(i)->first.str()] = i;
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unused[i].store(true, std::memory_order_relaxed);
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}
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}
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};
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void fixup_unused_cells_and_mems(CellAnalysis& analysis, MemAnalysis& mem_analysis, CellTraversal& traversal, AnalysisContext& actx, CleanRunContext &clean_ctx) {
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// Processes the cell queue in batches, traversing input cones by enqueuing more cells
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// Discover and mark used memories and cells
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actx.subpool.run([&analysis, &mem_analysis, &traversal, &actx, &clean_ctx](const ParallelDispatchThreadPool::RunCtx &ctx) {
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pool<SigBit> bits;
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pool<std::string> mems;
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while (true) {
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std::vector<int> cell_indices = traversal.queue.pop_batch(ctx);
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if (cell_indices.empty())
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return;
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for (auto cell_index : cell_indices) {
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Cell *cell = actx.mod->cell_at(cell_index);
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for (auto &it : cell->connections())
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if (!clean_ctx.ct_all.cell_known(cell->type) || clean_ctx.ct_all.cell_input(cell->type, it.first))
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for (auto bit : actx.assign_map(it.second))
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bits.insert(bit);
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if (cell->type.in(ID($memrd), ID($memrd_v2))) {
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std::string mem_id = cell->getParam(ID::MEMID).decode_string();
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if (mem_analysis.indices.count(mem_id)) {
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int mem_index = mem_analysis.indices[mem_id];
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// Memory fixup
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if (mem_analysis.unused[mem_index].exchange(false, std::memory_order_relaxed))
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mems.insert(mem_id);
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}
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}
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}
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for (auto bit : bits) {
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// Cells fixup
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const WireDrivers *drivers = traversal.wire2driver.find({{bit}, hash_bit(bit)});
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if (drivers != nullptr)
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for (int cell_idx : *drivers)
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analysis.mark_used_and_enqueue(cell_idx, traversal.queue, ctx);
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}
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bits.clear();
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for (auto mem : mems) {
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if (traversal.mem2cells.count(mem) == 0)
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continue;
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// Cells fixup
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for (int cell_idx : traversal.mem2cells.at(mem))
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analysis.mark_used_and_enqueue(cell_idx, traversal.queue, ctx);
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}
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mems.clear();
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}
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});
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}
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pool<Cell*> all_unused_cells(const Module *mod, const CellAnalysis& analysis, Wire2Drivers& wire2driver, ParallelDispatchThreadPool::Subpool &subpool) {
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pool<Cell*> unused_cells;
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ShardedVector<int> sharded_unused_cells(subpool);
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subpool.run([mod, &analysis, &wire2driver, &sharded_unused_cells](const ParallelDispatchThreadPool::RunCtx &ctx) {
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// Parallel destruction of `wire2driver`
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wire2driver.clear(ctx);
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for (int i : ctx.item_range(mod->cells_size()))
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if (analysis.unused[i].load(std::memory_order_relaxed))
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sharded_unused_cells.insert(ctx, i);
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});
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for (int cell_index : sharded_unused_cells)
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unused_cells.insert(mod->cell_at(cell_index));
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unused_cells.sort(RTLIL::sort_by_name_id<RTLIL::Cell>());
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return unused_cells;
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}
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void remove_cells(RTLIL::Module* mod, FfInitVals& ffinit, const pool<Cell*>& cells, bool verbose, RmStats& stats) {
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for (auto cell : cells) {
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if (verbose)
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log_debug(" removing unused `%s' cell `%s'.\n", cell->type, cell->name);
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mod->design->scratchpad_set_bool("opt.did_something", true);
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if (cell->is_builtin_ff())
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ffinit.remove_init(cell->getPort(ID::Q));
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mod->remove(cell);
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stats.count_rm_cells++;
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}
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}
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void remove_mems(RTLIL::Module* mod, const MemAnalysis& mem_analysis, bool verbose) {
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for (const auto &it : mem_analysis.indices) {
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if (!mem_analysis.unused[it.second].load(std::memory_order_relaxed))
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continue;
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RTLIL::IdString id(it.first);
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if (verbose)
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log_debug(" removing unused memory `%s'.\n", id.unescape());
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delete mod->memories.at(id);
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mod->memories.erase(id);
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}
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}
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PRIVATE_NAMESPACE_END
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YOSYS_NAMESPACE_BEGIN
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void rmunused_module_cells(Module *module, ParallelDispatchThreadPool::Subpool &subpool, CleanRunContext &clean_ctx)
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{
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AnalysisContext actx(module, subpool);
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// Used for logging warnings only
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SigMap wire_map = wire_sigmap(module);
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CellAnalysis analysis(actx);
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CellTraversal traversal(subpool.num_threads());
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// Mark all unkept cells as unused initially
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// and queue up cell traversal from those cells
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auto logs = explore(analysis, traversal, wire_map, actx, clean_ctx);
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// Mark cells that drive kept wires into cell_queue and those bits as used
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// and queue up cell traversal from those cells
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pool<SigBit> used_raw_bits = analysis.analyze_kept_wires(traversal, actx.assign_map, wire_map, subpool.num_threads());
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// Mark all memories as unused initially
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MemAnalysis mem_analysis(module);
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// Marked all used cells and mems as used by traversing with cell queue
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fixup_unused_cells_and_mems(analysis, mem_analysis, traversal, actx, clean_ctx);
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// Analyses are now fully correct
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// unused_cells.contains(foo) iff analysis.used[foo] == true
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// wire2driver is passed in only to destroy it
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pool<Cell*> unused_cells = all_unused_cells(module, analysis, traversal.wire2driver, subpool);
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FfInitVals ffinit;
|
||||
ffinit.set_parallel(&actx.assign_map, subpool.thread_pool(), module);
|
||||
// Now we know what to kill
|
||||
remove_cells(module, ffinit, unused_cells, clean_ctx.flags.verbose, clean_ctx.stats);
|
||||
remove_mems(module, mem_analysis, clean_ctx.flags.verbose);
|
||||
logs.print_warnings(used_raw_bits, wire_map, module, clean_ctx);
|
||||
}
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "passes/opt/opt_clean/opt_clean.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
bool is_signed(RTLIL::Cell* cell) {
|
||||
return cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
|
||||
}
|
||||
|
||||
bool trim_buf(RTLIL::Cell* cell, ShardedVector<RTLIL::SigSig>& new_connections, const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
RTLIL::SigSpec a = cell->getPort(ID::A);
|
||||
RTLIL::SigSpec y = cell->getPort(ID::Y);
|
||||
a.extend_u0(GetSize(y), is_signed(cell));
|
||||
|
||||
if (a.has_const(State::Sz)) {
|
||||
RTLIL::SigSpec new_a;
|
||||
RTLIL::SigSpec new_y;
|
||||
for (int i = 0; i < GetSize(a); ++i) {
|
||||
RTLIL::SigBit b = a[i];
|
||||
if (b == State::Sz)
|
||||
return false;
|
||||
new_a.append(b);
|
||||
new_y.append(y[i]);
|
||||
}
|
||||
a = std::move(new_a);
|
||||
y = std::move(new_y);
|
||||
}
|
||||
if (!y.empty())
|
||||
new_connections.insert(ctx, {y, a});
|
||||
return true;
|
||||
}
|
||||
|
||||
bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose) {
|
||||
bool did_something = false;
|
||||
for (RTLIL::Cell *cell : cells) {
|
||||
if (verbose) {
|
||||
if (cell->type == ID($connect))
|
||||
log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name,
|
||||
log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
|
||||
else if (cell->type == ID($input_port))
|
||||
log_debug(" removing input port marker cell `%s': %s\n", cell->name,
|
||||
log_signal(cell->getPort(ID::Y)));
|
||||
else
|
||||
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
|
||||
log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
|
||||
}
|
||||
mod->remove(cell);
|
||||
did_something = true;
|
||||
}
|
||||
return did_something;
|
||||
}
|
||||
PRIVATE_NAMESPACE_END
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose)
|
||||
{
|
||||
ShardedVector<RTLIL::Cell*> delcells(subpool);
|
||||
ShardedVector<RTLIL::SigSig> new_connections(subpool);
|
||||
const RTLIL::Module *const_module = module;
|
||||
subpool.run([const_module, &delcells, &new_connections](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
for (int i : ctx.item_range(const_module->cells_size())) {
|
||||
RTLIL::Cell *cell = const_module->cell_at(i);
|
||||
if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
|
||||
if (trim_buf(cell, new_connections, ctx))
|
||||
delcells.insert(ctx, cell);
|
||||
} else if (cell->type.in(ID($connect)) && !cell->has_keep_attr()) {
|
||||
RTLIL::SigSpec a = cell->getPort(ID::A);
|
||||
RTLIL::SigSpec b = cell->getPort(ID::B);
|
||||
if (a.has_const() && !b.has_const())
|
||||
std::swap(a, b);
|
||||
new_connections.insert(ctx, {a, b});
|
||||
delcells.insert(ctx, cell);
|
||||
} else if (cell->type.in(ID($input_port)) && !cell->has_keep_attr()) {
|
||||
delcells.insert(ctx, cell);
|
||||
}
|
||||
}
|
||||
});
|
||||
for (RTLIL::SigSig &connection : new_connections) {
|
||||
module->connect(connection);
|
||||
}
|
||||
if (remove(delcells, module, verbose))
|
||||
module->design->scratchpad_set_bool("opt.did_something", true);
|
||||
}
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "passes/opt/opt_clean/opt_clean.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
ShardedVector<std::pair<SigBit, State>> build_inits(AnalysisContext& actx) {
|
||||
ShardedVector<std::pair<SigBit, State>> results(actx.subpool);
|
||||
actx.subpool.run([&results, &actx](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
for (int i : ctx.item_range(actx.mod->cells_size())) {
|
||||
RTLIL::Cell *cell = actx.mod->cell_at(i);
|
||||
if (StaticCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(ID::Q))
|
||||
{
|
||||
SigSpec sig = cell->getPort(ID::Q);
|
||||
|
||||
for (int i = 0; i < GetSize(sig); i++)
|
||||
{
|
||||
SigBit bit = sig[i];
|
||||
|
||||
if (bit.wire == nullptr || bit.wire->attributes.count(ID::init) == 0)
|
||||
continue;
|
||||
|
||||
Const init = bit.wire->attributes.at(ID::init);
|
||||
|
||||
if (i >= GetSize(init) || init[i] == State::Sx || init[i] == State::Sz)
|
||||
continue;
|
||||
|
||||
results.insert(ctx, {bit, init[i]});
|
||||
}
|
||||
}
|
||||
}
|
||||
});
|
||||
return results;
|
||||
}
|
||||
|
||||
dict<SigBit, State> qbits_from_inits(ShardedVector<std::pair<SigBit, State>>& inits, SigMap& assign_map) {
|
||||
dict<SigBit, State> qbits;
|
||||
for (std::pair<SigBit, State> &p : inits) {
|
||||
assign_map.add(p.first);
|
||||
qbits[p.first] = p.second;
|
||||
}
|
||||
return qbits;
|
||||
}
|
||||
|
||||
ShardedVector<RTLIL::Wire*> deferred_init_transfer(const dict<SigBit, State>& qbits, AnalysisContext& actx) {
|
||||
ShardedVector<RTLIL::Wire*> wire_results(actx.subpool);
|
||||
actx.subpool.run([&actx, &qbits, &wire_results](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
for (int j : ctx.item_range(actx.mod->wires_size())) {
|
||||
RTLIL::Wire *wire = actx.mod->wire_at(j);
|
||||
if (wire->attributes.count(ID::init) == 0)
|
||||
continue;
|
||||
Const init = wire->attributes.at(ID::init);
|
||||
|
||||
for (int i = 0; i < GetSize(wire) && i < GetSize(init); i++)
|
||||
{
|
||||
if (init[i] == State::Sx || init[i] == State::Sz)
|
||||
continue;
|
||||
|
||||
SigBit wire_bit = SigBit(wire, i);
|
||||
SigBit mapped_wire_bit = actx.assign_map(wire_bit);
|
||||
|
||||
if (wire_bit == mapped_wire_bit)
|
||||
goto next_wire;
|
||||
|
||||
if (mapped_wire_bit.wire) {
|
||||
if (qbits.count(mapped_wire_bit) == 0)
|
||||
goto next_wire;
|
||||
|
||||
if (qbits.at(mapped_wire_bit) != init[i])
|
||||
goto next_wire;
|
||||
}
|
||||
else {
|
||||
if (mapped_wire_bit == State::Sx || mapped_wire_bit == State::Sz)
|
||||
goto next_wire;
|
||||
|
||||
if (mapped_wire_bit != init[i]) {
|
||||
log_warning("Initial value conflict for %s resolving to %s but with init %s.\n", log_signal(wire_bit), log_signal(mapped_wire_bit), log_signal(init[i]));
|
||||
goto next_wire;
|
||||
}
|
||||
}
|
||||
}
|
||||
wire_results.insert(ctx, wire);
|
||||
|
||||
next_wire:;
|
||||
}
|
||||
});
|
||||
return wire_results;
|
||||
}
|
||||
|
||||
bool remove_redundant_inits(ShardedVector<RTLIL::Wire*> wires, bool verbose) {
|
||||
bool did_something = false;
|
||||
for (RTLIL::Wire *wire : wires) {
|
||||
if (verbose)
|
||||
log_debug(" removing redundant init attribute on %s.\n", log_id(wire));
|
||||
wire->attributes.erase(ID::init);
|
||||
did_something = true;
|
||||
}
|
||||
return did_something;
|
||||
}
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
bool rmunused_module_init(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose)
|
||||
{
|
||||
AnalysisContext actx(module, subpool);
|
||||
|
||||
ShardedVector<std::pair<SigBit, State>> inits = build_inits(actx);
|
||||
dict<SigBit, State> qbits = qbits_from_inits(inits, actx.assign_map);
|
||||
ShardedVector<RTLIL::Wire*> inits_to_transfer = deferred_init_transfer(qbits, actx);
|
||||
|
||||
bool did_something = remove_redundant_inits(inits_to_transfer, verbose);
|
||||
if (did_something)
|
||||
module->design->scratchpad_set_bool("opt.did_something", true);
|
||||
|
||||
return did_something;
|
||||
}
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
|
@ -0,0 +1,167 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "kernel/rtlil.h"
|
||||
#include "kernel/sigtools.h"
|
||||
#include "kernel/threading.h"
|
||||
#include "kernel/celltypes.h"
|
||||
#include "kernel/yosys_common.h"
|
||||
|
||||
#ifndef OPT_CLEAN_KEEP_CACHE_H
|
||||
#define OPT_CLEAN_KEEP_CACHE_H
|
||||
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
struct KeepCache
|
||||
{
|
||||
dict<Module*, bool> keep_modules;
|
||||
bool purge_mode;
|
||||
|
||||
KeepCache(bool purge_mode, ParallelDispatchThreadPool &thread_pool, const std::vector<RTLIL::Module *> &selected_modules)
|
||||
: purge_mode(purge_mode) {
|
||||
|
||||
std::vector<RTLIL::Module *> scan_modules_worklist;
|
||||
dict<RTLIL::Module *, std::vector<RTLIL::Module*>> dependents;
|
||||
std::vector<RTLIL::Module *> propagate_kept_modules_worklist;
|
||||
for (RTLIL::Module *module : selected_modules) {
|
||||
if (keep_modules.count(module))
|
||||
continue;
|
||||
bool keep = scan_module(module, thread_pool, dependents, ALL_CELLS, scan_modules_worklist);
|
||||
keep_modules[module] = keep;
|
||||
if (keep)
|
||||
propagate_kept_modules_worklist.push_back(module);
|
||||
}
|
||||
|
||||
while (!scan_modules_worklist.empty()) {
|
||||
RTLIL::Module *module = scan_modules_worklist.back();
|
||||
scan_modules_worklist.pop_back();
|
||||
if (keep_modules.count(module))
|
||||
continue;
|
||||
bool keep = scan_module(module, thread_pool, dependents, MINIMUM_CELLS, scan_modules_worklist);
|
||||
keep_modules[module] = keep;
|
||||
if (keep)
|
||||
propagate_kept_modules_worklist.push_back(module);
|
||||
}
|
||||
|
||||
while (!propagate_kept_modules_worklist.empty()) {
|
||||
RTLIL::Module *module = propagate_kept_modules_worklist.back();
|
||||
propagate_kept_modules_worklist.pop_back();
|
||||
for (RTLIL::Module *dependent : dependents[module]) {
|
||||
if (keep_modules[dependent])
|
||||
continue;
|
||||
keep_modules[dependent] = true;
|
||||
propagate_kept_modules_worklist.push_back(dependent);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool query(Cell *cell) const
|
||||
{
|
||||
if (keep_cell(cell, purge_mode))
|
||||
return true;
|
||||
if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
|
||||
return true;
|
||||
if (cell->module && cell->module->design) {
|
||||
RTLIL::Module *cell_module = cell->module->design->module(cell->type);
|
||||
return cell_module != nullptr && keep_modules.at(cell_module);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
private:
|
||||
enum ScanCells {
|
||||
// Scan every cell to see if it uses a module that is kept.
|
||||
ALL_CELLS,
|
||||
// Stop scanning cells if we determine early that this module is kept.
|
||||
MINIMUM_CELLS,
|
||||
};
|
||||
bool scan_module(Module *module, ParallelDispatchThreadPool &thread_pool, dict<RTLIL::Module *, std::vector<RTLIL::Module*>> &dependents,
|
||||
ScanCells scan_cells, std::vector<Module*> &worklist) const
|
||||
{
|
||||
MonotonicFlag keep_module;
|
||||
if (module->get_bool_attribute(ID::keep)) {
|
||||
if (scan_cells == MINIMUM_CELLS)
|
||||
return true;
|
||||
keep_module.set();
|
||||
}
|
||||
|
||||
ParallelDispatchThreadPool::Subpool subpool(thread_pool, ThreadPool::work_pool_size(0, module->cells_size(), 1000));
|
||||
ShardedVector<Module*> deps(subpool);
|
||||
const RTLIL::Module *const_module = module;
|
||||
bool purge_mode = this->purge_mode;
|
||||
subpool.run([purge_mode, const_module, scan_cells, &deps, &keep_module](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
bool keep = false;
|
||||
for (int i : ctx.item_range(const_module->cells_size())) {
|
||||
Cell *cell = const_module->cell_at(i);
|
||||
if (keep_cell(cell, purge_mode)) {
|
||||
if (scan_cells == MINIMUM_CELLS) {
|
||||
keep_module.set();
|
||||
return;
|
||||
}
|
||||
keep = true;
|
||||
}
|
||||
if (const_module->design) {
|
||||
RTLIL::Module *cell_module = const_module->design->module(cell->type);
|
||||
if (cell_module != nullptr)
|
||||
deps.insert(ctx, cell_module);
|
||||
}
|
||||
}
|
||||
if (keep) {
|
||||
keep_module.set();
|
||||
return;
|
||||
}
|
||||
for (int i : ctx.item_range(const_module->wires_size())) {
|
||||
Wire *wire = const_module->wire_at(i);
|
||||
if (wire->get_bool_attribute(ID::keep)) {
|
||||
keep_module.set();
|
||||
return;
|
||||
}
|
||||
}
|
||||
});
|
||||
if (scan_cells == MINIMUM_CELLS && keep_module.load())
|
||||
return true;
|
||||
for (Module *dep : deps) {
|
||||
dependents[dep].push_back(module);
|
||||
worklist.push_back(dep);
|
||||
}
|
||||
return keep_module.load();
|
||||
}
|
||||
|
||||
static bool keep_cell(Cell *cell, bool purge_mode)
|
||||
{
|
||||
if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
|
||||
return true;
|
||||
|
||||
if (cell->type.in(ID($overwrite_tag)))
|
||||
return true;
|
||||
|
||||
if (cell->type == ID($print) || cell->type == ID($check))
|
||||
return true;
|
||||
|
||||
if (cell->has_keep_attr())
|
||||
return true;
|
||||
|
||||
if (!purge_mode && cell->type == ID($scopeinfo))
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
};
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
#endif /* OPT_CLEAN_KEEP_CACHE_H */
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "kernel/register.h"
|
||||
#include "kernel/log.h"
|
||||
#include "passes/opt/opt_clean/opt_clean.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
void rmunused_module(RTLIL::Module *module, bool rminit, CleanRunContext &clean_ctx)
|
||||
{
|
||||
if (clean_ctx.flags.verbose)
|
||||
log("Finding unused cells or wires in module %s..\n", module->name);
|
||||
|
||||
// Use no more than one worker per thousand cells, rounded down, so
|
||||
// we only start multithreading with at least 2000 cells.
|
||||
int num_worker_threads = ThreadPool::work_pool_size(0, module->cells_size(), 1000);
|
||||
ParallelDispatchThreadPool::Subpool subpool(clean_ctx.thread_pool, num_worker_threads);
|
||||
remove_temporary_cells(module, subpool, clean_ctx.flags.verbose);
|
||||
rmunused_module_cells(module, subpool, clean_ctx);
|
||||
while (rmunused_module_signals(module, subpool, clean_ctx)) { }
|
||||
|
||||
if (rminit && rmunused_module_init(module, subpool, clean_ctx.flags.verbose))
|
||||
while (rmunused_module_signals(module, subpool, clean_ctx)) { }
|
||||
}
|
||||
struct OptCleanPass : public Pass {
|
||||
OptCleanPass() : Pass("opt_clean", "remove unused cells and wires") { }
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" opt_clean [options] [selection]\n");
|
||||
log("\n");
|
||||
log("This pass identifies wires and cells that are unused and removes them. Other\n");
|
||||
log("passes often remove cells but leave the wires in the design or reconnect the\n");
|
||||
log("wires but leave the old cells in the design. This pass can be used to clean up\n");
|
||||
log("after the passes that do the actual work.\n");
|
||||
log("\n");
|
||||
log("This pass only operates on completely selected modules without processes.\n");
|
||||
log("\n");
|
||||
log(" -purge\n");
|
||||
log(" also remove internal nets if they have a public name\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
bool purge_mode = false;
|
||||
|
||||
log_header(design, "Executing OPT_CLEAN pass (remove unused cells and wires).\n");
|
||||
log_push();
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
if (args[argidx] == "-purge") {
|
||||
purge_mode = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
std::vector<RTLIL::Module*> selected_modules;
|
||||
for (auto module : design->selected_whole_modules_warn())
|
||||
if (!module->has_processes_warn())
|
||||
selected_modules.push_back(module);
|
||||
int thread_pool_size = 0;
|
||||
for (RTLIL::Module *m : selected_modules)
|
||||
thread_pool_size = std::max(thread_pool_size, ThreadPool::work_pool_size(0, m->cells_size(), 1000));
|
||||
ParallelDispatchThreadPool thread_pool(thread_pool_size);
|
||||
KeepCache keep_cache(purge_mode, thread_pool, selected_modules);
|
||||
|
||||
{
|
||||
CleanRunContext clean_ctx(design, {purge_mode, true});
|
||||
for (auto module : selected_modules)
|
||||
rmunused_module(module, true, clean_ctx);
|
||||
clean_ctx.stats.log();
|
||||
|
||||
design->optimize();
|
||||
design->check();
|
||||
}
|
||||
|
||||
log_pop();
|
||||
|
||||
request_garbage_collection();
|
||||
}
|
||||
} OptCleanPass;
|
||||
|
||||
struct CleanPass : public Pass {
|
||||
CleanPass() : Pass("clean", "remove unused cells and wires") { }
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" clean [options] [selection]\n");
|
||||
log("\n");
|
||||
log("This is identical to 'opt_clean', but less verbose.\n");
|
||||
log("\n");
|
||||
log("When commands are separated using the ';;' token, this command will be executed\n");
|
||||
log("between the commands.\n");
|
||||
log("\n");
|
||||
log("When commands are separated using the ';;;' token, this command will be executed\n");
|
||||
log("in -purge mode between the commands.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
bool purge_mode = false;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
if (args[argidx] == "-purge") {
|
||||
purge_mode = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
{
|
||||
CleanRunContext clean_ctx(design, {purge_mode, ys_debug()});
|
||||
for (auto module : clean_ctx.selected_modules)
|
||||
rmunused_module(module, true, clean_ctx);
|
||||
|
||||
log_suppressed();
|
||||
clean_ctx.stats.log();
|
||||
|
||||
design->optimize();
|
||||
design->check();
|
||||
}
|
||||
|
||||
request_garbage_collection();
|
||||
}
|
||||
} CleanPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "kernel/rtlil.h"
|
||||
#include "kernel/threading.h"
|
||||
#include "passes/opt/opt_clean/keep_cache.h"
|
||||
|
||||
#ifndef OPT_CLEAN_SHARED_H
|
||||
#define OPT_CLEAN_SHARED_H
|
||||
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
struct AnalysisContext {
|
||||
SigMap assign_map;
|
||||
const RTLIL::Module *mod;
|
||||
ParallelDispatchThreadPool::Subpool &subpool;
|
||||
AnalysisContext(RTLIL::Module* m, ParallelDispatchThreadPool::Subpool &p) : assign_map(m), mod(m), subpool(p) {}
|
||||
};
|
||||
|
||||
struct RmStats {
|
||||
int count_rm_cells = 0;
|
||||
int count_rm_wires = 0;
|
||||
|
||||
void log()
|
||||
{
|
||||
if (count_rm_cells > 0 || count_rm_wires > 0)
|
||||
YOSYS_NAMESPACE_PREFIX log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
|
||||
}
|
||||
};
|
||||
|
||||
struct Flags {
|
||||
bool purge = false;
|
||||
bool verbose = false;
|
||||
};
|
||||
struct CleanRunContext {
|
||||
static constexpr auto ct_reg = StaticCellTypes::Categories::join(
|
||||
StaticCellTypes::Compat::mem_ff,
|
||||
StaticCellTypes::categories.is_anyinit);
|
||||
NewCellTypes ct_all;
|
||||
RmStats stats;
|
||||
ParallelDispatchThreadPool thread_pool;
|
||||
std::vector<RTLIL::Module*> selected_modules;
|
||||
KeepCache keep_cache;
|
||||
Flags flags;
|
||||
|
||||
private:
|
||||
// Helper to compute thread pool size
|
||||
static int compute_thread_pool_size(RTLIL::Design* design) {
|
||||
int thread_pool_size = 0;
|
||||
for (auto module : design->selected_unboxed_whole_modules())
|
||||
if (!module->has_processes())
|
||||
thread_pool_size = std::max(thread_pool_size,
|
||||
ThreadPool::work_pool_size(0, module->cells_size(), 1000));
|
||||
return thread_pool_size;
|
||||
}
|
||||
|
||||
static std::vector<RTLIL::Module*> get_selected_modules(RTLIL::Design* design) {
|
||||
std::vector<RTLIL::Module*> modules;
|
||||
for (auto module : design->selected_unboxed_whole_modules())
|
||||
if (!module->has_processes())
|
||||
modules.push_back(module);
|
||||
return modules;
|
||||
}
|
||||
|
||||
public:
|
||||
CleanRunContext(RTLIL::Design* design, Flags f)
|
||||
: thread_pool(compute_thread_pool_size(design)),
|
||||
selected_modules(get_selected_modules(design)),
|
||||
keep_cache(f.purge, thread_pool, selected_modules),
|
||||
flags(f)
|
||||
{
|
||||
ct_all.setup(design);
|
||||
}
|
||||
|
||||
~CleanRunContext() {
|
||||
ct_all.clear();
|
||||
}
|
||||
};
|
||||
|
||||
void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose);
|
||||
void rmunused_module_cells(Module *module, ParallelDispatchThreadPool::Subpool &subpool, CleanRunContext &clean_ctx);
|
||||
bool rmunused_module_signals(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, CleanRunContext &clean_ctx);
|
||||
bool rmunused_module_init(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose);
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
||||
#endif /* OPT_CLEAN_SHARED_H */
|
||||
|
|
@ -0,0 +1,585 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "passes/opt/opt_clean/opt_clean.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
// No collision handler for these, since we will use them such that collisions don't happen
|
||||
struct ShardedSigBit {
|
||||
using Accumulated = ShardedSigBit;
|
||||
RTLIL::SigBit bit;
|
||||
ShardedSigBit() = default;
|
||||
ShardedSigBit(const RTLIL::SigBit &bit) : bit(bit) {}
|
||||
};
|
||||
struct ShardedSigBitEquality {
|
||||
bool operator()(const ShardedSigBit &b1, const ShardedSigBit &b2) const {
|
||||
return b1.bit == b2.bit;
|
||||
}
|
||||
};
|
||||
using ShardedSigPool = ShardedHashtable<ShardedSigBit, ShardedSigBitEquality, SetCollisionHandler<ShardedSigBit>>;
|
||||
|
||||
struct ShardedSigSpec {
|
||||
using Accumulated = ShardedSigSpec;
|
||||
RTLIL::SigSpec spec;
|
||||
ShardedSigSpec() = default;
|
||||
ShardedSigSpec(RTLIL::SigSpec spec) : spec(std::move(spec)) {}
|
||||
ShardedSigSpec(ShardedSigSpec &&) = default;
|
||||
};
|
||||
struct ShardedSigSpecEquality {
|
||||
bool operator()(const ShardedSigSpec &s1, const ShardedSigSpec &s2) const {
|
||||
return s1.spec == s2.spec;
|
||||
}
|
||||
};
|
||||
using ShardedSigSpecPool = ShardedHashtable<ShardedSigSpec, ShardedSigSpecEquality, SetCollisionHandler<ShardedSigSpec>>;
|
||||
|
||||
struct ExactCellWires {
|
||||
const ShardedSigSpecPool &exact_cells;
|
||||
const SigMap &assign_map;
|
||||
dict<RTLIL::Wire *, bool> cache;
|
||||
|
||||
ExactCellWires(const ShardedSigSpecPool &exact_cells, const SigMap &assign_map) : exact_cells(exact_cells), assign_map(assign_map) {}
|
||||
void cache_result_for_bit(const SigBit &bit) {
|
||||
if (bit.wire != nullptr)
|
||||
(void)is_exactly_cell_driven(bit.wire);
|
||||
}
|
||||
bool is_exactly_cell_driven(RTLIL::Wire *wire) {
|
||||
if (wire->port_input)
|
||||
return true;
|
||||
auto it = cache.find(wire);
|
||||
if (it != cache.end())
|
||||
return it->second;
|
||||
SigSpec sig = assign_map(wire);
|
||||
bool direct = exact_cells.find({sig, sig.hash_into(Hasher()).yield()}) != nullptr;
|
||||
cache.insert({wire, direct});
|
||||
return direct;
|
||||
}
|
||||
void cache_all(ShardedVector<RTLIL::SigBit> &bits) {
|
||||
for (RTLIL::SigBit candidate : bits) {
|
||||
cache_result_for_bit(candidate);
|
||||
cache_result_for_bit(assign_map(candidate));
|
||||
}
|
||||
|
||||
}
|
||||
};
|
||||
|
||||
int count_nontrivial_wire_attrs(RTLIL::Wire *w)
|
||||
{
|
||||
int count = w->attributes.size();
|
||||
count -= w->attributes.count(ID::src);
|
||||
count -= w->attributes.count(ID::hdlname);
|
||||
count -= w->attributes.count(ID::scopename);
|
||||
count -= w->attributes.count(ID::unused_bits);
|
||||
return count;
|
||||
}
|
||||
|
||||
// Should we pick `s2` over `s1` to represent a signal?
|
||||
bool compare_signals(const RTLIL::SigBit &s1, const RTLIL::SigBit &s2, const ShardedSigPool ®s, const ShardedSigPool &conns, ExactCellWires &cell_wires)
|
||||
{
|
||||
if (s1 == s2)
|
||||
return false;
|
||||
|
||||
RTLIL::Wire *w1 = s1.wire;
|
||||
RTLIL::Wire *w2 = s2.wire;
|
||||
|
||||
if (w1 == NULL || w2 == NULL)
|
||||
return w2 == NULL;
|
||||
|
||||
if (w1->port_input != w2->port_input)
|
||||
return w2->port_input;
|
||||
|
||||
if ((w1->port_input && w1->port_output) != (w2->port_input && w2->port_output))
|
||||
return !(w2->port_input && w2->port_output);
|
||||
|
||||
if (w1->name.isPublic() && w2->name.isPublic()) {
|
||||
ShardedSigPool::AccumulatedValue s1_val = {s1, s1.hash_top().yield()};
|
||||
ShardedSigPool::AccumulatedValue s2_val = {s2, s2.hash_top().yield()};
|
||||
bool regs1 = regs.find(s1_val) != nullptr;
|
||||
bool regs2 = regs.find(s2_val) != nullptr;
|
||||
if (regs1 != regs2)
|
||||
return regs2;
|
||||
bool w1_exact = cell_wires.is_exactly_cell_driven(w1);
|
||||
bool w2_exact = cell_wires.is_exactly_cell_driven(w2);
|
||||
if (w1_exact != w2_exact)
|
||||
return w2_exact;
|
||||
bool conns1 = conns.find(s1_val) != nullptr;
|
||||
bool conns2 = conns.find(s2_val) != nullptr;
|
||||
if (conns1 != conns2)
|
||||
return conns2;
|
||||
}
|
||||
|
||||
if (w1 == w2)
|
||||
return s2.offset < s1.offset;
|
||||
|
||||
if (w1->port_output != w2->port_output)
|
||||
return w2->port_output;
|
||||
|
||||
if (w1->name[0] != w2->name[0])
|
||||
return w2->name.isPublic();
|
||||
|
||||
int attrs1 = count_nontrivial_wire_attrs(w1);
|
||||
int attrs2 = count_nontrivial_wire_attrs(w2);
|
||||
|
||||
if (attrs1 != attrs2)
|
||||
return attrs2 > attrs1;
|
||||
|
||||
return w2->name.lt_by_name(w1->name);
|
||||
}
|
||||
|
||||
bool check_public_name(RTLIL::IdString id)
|
||||
{
|
||||
if (id.begins_with("$"))
|
||||
return false;
|
||||
const std::string &id_str = id.str();
|
||||
if (id.begins_with("\\_") && (id.ends_with("_") || id_str.find("_[") != std::string::npos))
|
||||
return false;
|
||||
if (id_str.find(".$") != std::string::npos)
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
|
||||
void add_spec(ShardedSigPool::Builder &builder, const ThreadIndex &thread, const RTLIL::SigSpec &spec) {
|
||||
for (SigBit bit : spec)
|
||||
if (bit.wire != nullptr)
|
||||
builder.insert(thread, {bit, bit.hash_top().yield()});
|
||||
}
|
||||
|
||||
bool check_any(const ShardedSigPool &sigs, const RTLIL::SigSpec &spec) {
|
||||
for (SigBit b : spec)
|
||||
if (sigs.find({b, b.hash_top().yield()}) != nullptr)
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
bool check_all(const ShardedSigPool &sigs, const RTLIL::SigSpec &spec) {
|
||||
for (SigBit b : spec)
|
||||
if (sigs.find({b, b.hash_top().yield()}) == nullptr)
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
|
||||
struct UpdateConnection {
|
||||
RTLIL::Cell *cell;
|
||||
RTLIL::IdString port;
|
||||
RTLIL::SigSpec spec;
|
||||
};
|
||||
void fixup_cell_ports(ShardedVector<UpdateConnection> &update_connections)
|
||||
{
|
||||
for (UpdateConnection &update : update_connections)
|
||||
update.cell->connections_.at(update.port) = std::move(update.spec);
|
||||
}
|
||||
|
||||
struct InitBits {
|
||||
dict<SigBit, RTLIL::State> values;
|
||||
// Wires that appear in the keys of the `values` dict
|
||||
pool<Wire*> wires;
|
||||
|
||||
// Set init attributes on all wires of a connected group
|
||||
void apply_normalised_inits() {
|
||||
for (RTLIL::Wire *wire : wires) {
|
||||
bool found = false;
|
||||
Const val(State::Sx, wire->width);
|
||||
for (int i = 0; i < wire->width; i++) {
|
||||
auto it = values.find(RTLIL::SigBit(wire, i));
|
||||
if (it != values.end()) {
|
||||
val.set(i, it->second);
|
||||
found = true;
|
||||
}
|
||||
}
|
||||
if (found)
|
||||
wire->attributes[ID::init] = val;
|
||||
}
|
||||
}
|
||||
};
|
||||
static InitBits consume_inits(ShardedVector<RTLIL::Wire*> &initialized_wires, const SigMap &assign_map)
|
||||
{
|
||||
InitBits init_bits;
|
||||
for (RTLIL::Wire *initialized_wire : initialized_wires) {
|
||||
auto it = initialized_wire->attributes.find(ID::init);
|
||||
RTLIL::Const &val = it->second;
|
||||
SigSpec sig = assign_map(initialized_wire);
|
||||
for (int i = 0; i < GetSize(val) && i < GetSize(sig); i++)
|
||||
if (val[i] != State::Sx && sig[i].wire != nullptr) {
|
||||
init_bits.values[sig[i]] = val[i];
|
||||
init_bits.wires.insert(sig[i].wire);
|
||||
}
|
||||
initialized_wire->attributes.erase(it);
|
||||
}
|
||||
return init_bits;
|
||||
}
|
||||
|
||||
/**
|
||||
* What kinds of things are signals connected to?
|
||||
* Helps pick representatives out of groups of connected signals */
|
||||
struct SigConnKinds {
|
||||
// Wire bits directly driven by registers (with clk2fflogic exception)
|
||||
ShardedSigPool raw_registers;
|
||||
// Wire bits directly connected to any cell port
|
||||
ShardedSigPool raw_cell_connected;
|
||||
|
||||
// Signals exactly driven by a known cell output,
|
||||
// this will influence only our choice of representatives.
|
||||
// A signal is exactly driven by a cell output iff all its bits are driven by this output
|
||||
// and all bits of this output drive a bit of this signal.
|
||||
// Additionally, all signals that sigmap to this signal are exactly driven by the port, too
|
||||
ShardedSigSpecPool exact_cells;
|
||||
|
||||
SigConnKinds(bool purge_mode, const AnalysisContext& actx, CleanRunContext& clean_ctx) {
|
||||
ShardedSigPool::Builder raw_register_builder(actx.subpool);
|
||||
ShardedSigPool::Builder raw_cell_connected_builder(actx.subpool);
|
||||
ShardedSigSpecPool::Builder exact_cell_output_builder(actx.subpool);
|
||||
actx.subpool.run([&exact_cell_output_builder, &raw_register_builder, &raw_cell_connected_builder, purge_mode, &actx, &clean_ctx](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
|
||||
for (int i : ctx.item_range(actx.mod->cells_size())) {
|
||||
RTLIL::Cell *cell = actx.mod->cell_at(i);
|
||||
if (!purge_mode) {
|
||||
if (clean_ctx.ct_reg(cell->type)) {
|
||||
// Improve witness signal naming when clk2fflogic used
|
||||
// see commit message e36c71b5
|
||||
bool clk2fflogic = cell->get_bool_attribute(ID::clk2fflogic);
|
||||
for (auto &[port, sig] : cell->connections())
|
||||
if (clk2fflogic ? port == ID::D : clean_ctx.ct_all.cell_output(cell->type, port))
|
||||
add_spec(raw_register_builder, ctx, sig);
|
||||
}
|
||||
for (auto &[_, sig] : cell->connections())
|
||||
add_spec(raw_cell_connected_builder, ctx, sig);
|
||||
}
|
||||
if (clean_ctx.ct_all.cell_known(cell->type))
|
||||
for (auto &[port, sig] : cell->connections())
|
||||
if (clean_ctx.ct_all.cell_output(cell->type, port)) {
|
||||
RTLIL::SigSpec spec = actx.assign_map(sig);
|
||||
unsigned int hash = spec.hash_into(Hasher()).yield();
|
||||
exact_cell_output_builder.insert(ctx, {std::move(spec), hash});
|
||||
}
|
||||
}
|
||||
});
|
||||
actx.subpool.run([&raw_register_builder, &raw_cell_connected_builder, &exact_cell_output_builder](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
raw_register_builder.process(ctx);
|
||||
raw_cell_connected_builder.process(ctx);
|
||||
exact_cell_output_builder.process(ctx);
|
||||
});
|
||||
raw_registers = raw_register_builder;
|
||||
raw_cell_connected = raw_cell_connected_builder;
|
||||
exact_cells = exact_cell_output_builder;
|
||||
}
|
||||
void clear(const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
raw_registers.clear(ctx);
|
||||
raw_cell_connected.clear(ctx);
|
||||
exact_cells.clear(ctx);
|
||||
}
|
||||
};
|
||||
|
||||
ShardedVector<RTLIL::SigBit> build_candidates(ExactCellWires& cell_wires, const SigConnKinds& sig_analysis, const AnalysisContext& actx) {
|
||||
ShardedVector<RTLIL::SigBit> candidates(actx.subpool);
|
||||
actx.subpool.run([&actx, &sig_analysis, &candidates, &cell_wires](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
std::optional<ExactCellWires> local_cell_wires;
|
||||
ExactCellWires *this_thread_cell_wires = &cell_wires;
|
||||
if (ctx.thread_num > 0) {
|
||||
local_cell_wires.emplace(sig_analysis.exact_cells, actx.assign_map);
|
||||
this_thread_cell_wires = &local_cell_wires.value();
|
||||
}
|
||||
for (int i : ctx.item_range(actx.mod->wires_size())) {
|
||||
RTLIL::Wire *wire = actx.mod->wire_at(i);
|
||||
for (int j = 0; j < wire->width; ++j) {
|
||||
RTLIL::SigBit s1(wire, j);
|
||||
RTLIL::SigBit s2 = actx.assign_map(s1);
|
||||
if (compare_signals(s2, s1, sig_analysis.raw_registers, sig_analysis.raw_cell_connected, *this_thread_cell_wires))
|
||||
candidates.insert(ctx, s1);
|
||||
}
|
||||
}
|
||||
});
|
||||
return candidates;
|
||||
}
|
||||
|
||||
void update_assign_map(SigMap& assign_map, ShardedVector<RTLIL::SigBit>& sigmap_canonical_candidates, ExactCellWires& cell_wires, const SigConnKinds& sig_analysis) {
|
||||
for (RTLIL::SigBit candidate : sigmap_canonical_candidates) {
|
||||
RTLIL::SigBit current_canonical = assign_map(candidate);
|
||||
// Resolves if two threads in build_candidates found different candidates
|
||||
// for the same set
|
||||
// TODO adds effort for single-threaded?
|
||||
if (compare_signals(current_canonical, candidate, sig_analysis.raw_registers, sig_analysis.raw_cell_connected, cell_wires))
|
||||
assign_map.add(candidate);
|
||||
}
|
||||
}
|
||||
|
||||
struct DeferredUpdates {
|
||||
// Deferred updates to the assign_map
|
||||
ShardedVector<UpdateConnection> update_connections;
|
||||
// Wires we should remove init from
|
||||
ShardedVector<RTLIL::Wire*> initialized_wires;
|
||||
DeferredUpdates(ParallelDispatchThreadPool::Subpool &subpool) : update_connections(subpool), initialized_wires(subpool) {}
|
||||
};
|
||||
struct UsedSignals {
|
||||
// here, "connected" means "driven or driving something"
|
||||
// meanwhile, "used" means "driving something"
|
||||
// sigmapped
|
||||
ShardedSigPool connected;
|
||||
// pre-sigmapped
|
||||
ShardedSigPool raw_connected;
|
||||
// sigmapped
|
||||
ShardedSigPool used;
|
||||
|
||||
void clear(ParallelDispatchThreadPool::Subpool &subpool) {
|
||||
subpool.run([this](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
connected.clear(ctx);
|
||||
raw_connected.clear(ctx);
|
||||
used.clear(ctx);
|
||||
});
|
||||
}
|
||||
};
|
||||
|
||||
DeferredUpdates analyse_connectivity(UsedSignals& used, SigConnKinds& sig_analysis, const AnalysisContext& actx, CleanRunContext &clean_ctx) {
|
||||
DeferredUpdates deferred(actx.subpool);
|
||||
ShardedSigPool::Builder conn_builder(actx.subpool);
|
||||
ShardedSigPool::Builder raw_conn_builder(actx.subpool);
|
||||
ShardedSigPool::Builder used_builder(actx.subpool);
|
||||
|
||||
// gather the usage information for cells and update cell connections with the altered sigmap
|
||||
// also gather the usage information for ports, wires with `keep`
|
||||
// also gather init bits
|
||||
actx.subpool.run([&deferred, &conn_builder, &raw_conn_builder, &used_builder, &sig_analysis, &actx, &clean_ctx](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
// Parallel destruction of these sharded structures
|
||||
sig_analysis.clear(ctx);
|
||||
|
||||
for (int i : ctx.item_range(actx.mod->cells_size())) {
|
||||
RTLIL::Cell *cell = actx.mod->cell_at(i);
|
||||
for (const auto &[port, sig] : cell->connections_) {
|
||||
SigSpec spec = actx.assign_map(sig);
|
||||
if (spec != sig)
|
||||
deferred.update_connections.insert(ctx, {cell, port, spec});
|
||||
add_spec(raw_conn_builder, ctx, spec);
|
||||
add_spec(conn_builder, ctx, spec);
|
||||
if (!clean_ctx.ct_all.cell_output(cell->type, port))
|
||||
add_spec(used_builder, ctx, spec);
|
||||
}
|
||||
}
|
||||
for (int i : ctx.item_range(actx.mod->wires_size())) {
|
||||
RTLIL::Wire *wire = actx.mod->wire_at(i);
|
||||
if (wire->port_id > 0) {
|
||||
RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
|
||||
add_spec(raw_conn_builder, ctx, sig);
|
||||
actx.assign_map.apply(sig);
|
||||
add_spec(conn_builder, ctx, sig);
|
||||
if (!wire->port_input)
|
||||
add_spec(used_builder, ctx, sig);
|
||||
}
|
||||
if (wire->get_bool_attribute(ID::keep)) {
|
||||
RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
|
||||
actx.assign_map.apply(sig);
|
||||
add_spec(conn_builder, ctx, sig);
|
||||
}
|
||||
auto it = wire->attributes.find(ID::init);
|
||||
if (it != wire->attributes.end())
|
||||
deferred.initialized_wires.insert(ctx, wire);
|
||||
}
|
||||
});
|
||||
actx.subpool.run([&conn_builder, &raw_conn_builder, &used_builder](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
conn_builder.process(ctx);
|
||||
raw_conn_builder.process(ctx);
|
||||
used_builder.process(ctx);
|
||||
});
|
||||
used = {conn_builder, raw_conn_builder, used_builder};
|
||||
return deferred;
|
||||
}
|
||||
|
||||
struct WireDeleter {
|
||||
pool<RTLIL::Wire*> del_wires_queue;
|
||||
ShardedVector<RTLIL::Wire*> remove_init;
|
||||
ShardedVector<std::pair<RTLIL::Wire*, RTLIL::Const>> set_init;
|
||||
ShardedVector<RTLIL::SigSig> new_connections;
|
||||
ShardedVector<RTLIL::Wire*> remove_unused_bits;
|
||||
ShardedVector<std::pair<RTLIL::Wire*, RTLIL::Const>> set_unused_bits;
|
||||
WireDeleter(UsedSignals& used_sig_analysis, bool purge_mode, const AnalysisContext& actx) :
|
||||
remove_init(actx.subpool),
|
||||
set_init(actx.subpool),
|
||||
new_connections(actx.subpool),
|
||||
remove_unused_bits(actx.subpool),
|
||||
set_unused_bits(actx.subpool) {
|
||||
ShardedVector<RTLIL::Wire*> del_wires(actx.subpool);
|
||||
actx.subpool.run([&actx, purge_mode, &del_wires, &used_sig_analysis, this](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
||||
for (int i : ctx.item_range(actx.mod->wires_size())) {
|
||||
RTLIL::Wire *wire = actx.mod->wire_at(i);
|
||||
SigSpec s1 = SigSpec(wire), s2 = actx.assign_map(s1);
|
||||
log_assert(GetSize(s1) == GetSize(s2));
|
||||
|
||||
Const initval;
|
||||
bool has_init_attribute = wire->attributes.count(ID::init);
|
||||
bool init_changed = false;
|
||||
if (has_init_attribute)
|
||||
initval = wire->attributes.at(ID::init);
|
||||
if (GetSize(initval) != GetSize(wire)) {
|
||||
initval.resize(GetSize(wire), State::Sx);
|
||||
init_changed = true;
|
||||
}
|
||||
|
||||
if (GetSize(wire) == 0) {
|
||||
// delete zero-width wires, unless they are module ports
|
||||
if (wire->port_id == 0)
|
||||
goto delete_this_wire;
|
||||
} else
|
||||
if (wire->port_id != 0 || wire->get_bool_attribute(ID::keep) || !initval.is_fully_undef()) {
|
||||
// do not delete anything with "keep" or module ports or initialized wires
|
||||
} else
|
||||
if (!purge_mode && check_public_name(wire->name) && (check_any(used_sig_analysis.raw_connected, s1) || check_any(used_sig_analysis.connected, s2) || s1 != s2)) {
|
||||
// do not get rid of public names unless in purge mode or if the wire is entirely unused, not even aliased
|
||||
} else
|
||||
if (!check_any(used_sig_analysis.raw_connected, s1)) {
|
||||
// delete wires that aren't used by anything directly
|
||||
goto delete_this_wire;
|
||||
}
|
||||
|
||||
if (0)
|
||||
{
|
||||
delete_this_wire:
|
||||
del_wires.insert(ctx, wire);
|
||||
}
|
||||
else
|
||||
{
|
||||
RTLIL::SigSig new_conn;
|
||||
for (int i = 0; i < GetSize(s1); i++)
|
||||
if (s1[i] != s2[i]) {
|
||||
if (s2[i] == State::Sx && (initval[i] == State::S0 || initval[i] == State::S1)) {
|
||||
s2[i] = initval[i];
|
||||
initval.set(i, State::Sx);
|
||||
init_changed = true;
|
||||
}
|
||||
new_conn.first.append(s1[i]);
|
||||
new_conn.second.append(s2[i]);
|
||||
}
|
||||
if (new_conn.first.size() > 0)
|
||||
new_connections.insert(ctx, std::move(new_conn));
|
||||
if (initval.is_fully_undef()) {
|
||||
if (has_init_attribute)
|
||||
remove_init.insert(ctx, wire);
|
||||
} else
|
||||
if (init_changed)
|
||||
set_init.insert(ctx, {wire, std::move(initval)});
|
||||
|
||||
std::string unused_bits;
|
||||
if (!check_all(used_sig_analysis.used, s2)) {
|
||||
for (int i = 0; i < GetSize(s2); i++) {
|
||||
if (s2[i].wire == NULL)
|
||||
continue;
|
||||
SigBit b = s2[i];
|
||||
if (used_sig_analysis.used.find({b, b.hash_top().yield()}) == nullptr) {
|
||||
if (!unused_bits.empty())
|
||||
unused_bits += " ";
|
||||
unused_bits += stringf("%d", i);
|
||||
}
|
||||
}
|
||||
}
|
||||
if (unused_bits.empty() || wire->port_id != 0) {
|
||||
if (wire->attributes.count(ID::unused_bits))
|
||||
remove_unused_bits.insert(ctx, wire);
|
||||
} else {
|
||||
RTLIL::Const unused_bits_const(std::move(unused_bits));
|
||||
if (wire->attributes.count(ID::unused_bits)) {
|
||||
RTLIL::Const &unused_bits_attr = wire->attributes.at(ID::unused_bits);
|
||||
if (unused_bits_attr != unused_bits_const)
|
||||
set_unused_bits.insert(ctx, {wire, std::move(unused_bits_const)});
|
||||
} else
|
||||
set_unused_bits.insert(ctx, {wire, std::move(unused_bits_const)});
|
||||
}
|
||||
}
|
||||
}
|
||||
});
|
||||
del_wires_queue.insert(del_wires.begin(), del_wires.end());
|
||||
}
|
||||
// Decide for each wire if we should be deleting it
|
||||
// and fix up attributes
|
||||
void commit_changes(RTLIL::Module* mod) {
|
||||
for (RTLIL::Wire *wire : remove_init)
|
||||
wire->attributes.erase(ID::init);
|
||||
for (auto &p : set_init)
|
||||
p.first->attributes[ID::init] = std::move(p.second);
|
||||
for (auto &conn : new_connections)
|
||||
mod->connect(std::move(conn));
|
||||
for (RTLIL::Wire *wire : remove_unused_bits)
|
||||
wire->attributes.erase(ID::unused_bits);
|
||||
for (auto &p : set_unused_bits)
|
||||
p.first->attributes[ID::unused_bits] = std::move(p.second);
|
||||
}
|
||||
int delete_wires(RTLIL::Module* mod, bool verbose) {
|
||||
int deleted_and_unreported = 0;
|
||||
for (auto wire : del_wires_queue) {
|
||||
if (ys_debug() || (check_public_name(wire->name) && verbose))
|
||||
log_debug(" removing unused non-port wire %s.\n", wire->name);
|
||||
else
|
||||
deleted_and_unreported++;
|
||||
}
|
||||
mod->remove(del_wires_queue);
|
||||
return deleted_and_unreported;
|
||||
}
|
||||
};
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
bool rmunused_module_signals(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, CleanRunContext &clean_ctx)
|
||||
{
|
||||
// Passing actx to function == function does parallel work
|
||||
// Not passing module as function argument == function does not modify module
|
||||
// TODO the above sentence is false due to constness laundering in wire_at / cell_at
|
||||
AnalysisContext actx(module, subpool);
|
||||
SigConnKinds conn_kinds(clean_ctx.flags.purge, actx, clean_ctx);
|
||||
|
||||
ExactCellWires cell_wires(conn_kinds.exact_cells, actx.assign_map);
|
||||
// Collect sigmap representative candidates as built in parallel
|
||||
// With parallel runs, this creates redundant candidates that have to resolve in update_assign_map
|
||||
ShardedVector<RTLIL::SigBit> new_sigmap_rep_candidates = build_candidates(cell_wires, conn_kinds, actx);
|
||||
|
||||
// Cache all the cell_wires results that we might possible need. This avoids the results
|
||||
// changing when we update `assign_map` below.
|
||||
cell_wires.cache_all(new_sigmap_rep_candidates);
|
||||
// Modify assign_map to reflect the connectivity we want, not the one we have
|
||||
// this changes representative selection in assign_map
|
||||
update_assign_map(actx.assign_map, new_sigmap_rep_candidates, cell_wires, conn_kinds);
|
||||
|
||||
// Remove all wire-wire connections
|
||||
module->connections_.clear();
|
||||
|
||||
UsedSignals used;
|
||||
DeferredUpdates deferred = analyse_connectivity(used, conn_kinds, actx, clean_ctx);
|
||||
fixup_cell_ports(deferred.update_connections);
|
||||
// Rip up and re-apply init attributes onto representative wires with x-bits
|
||||
// in place of unset init bits
|
||||
consume_inits(deferred.initialized_wires, actx.assign_map).apply_normalised_inits();
|
||||
|
||||
WireDeleter deleter(used, clean_ctx.flags.purge, actx);
|
||||
|
||||
used.clear(subpool);
|
||||
|
||||
deleter.commit_changes(module);
|
||||
int deleted_and_unreported = deleter.delete_wires(module, clean_ctx.flags.verbose);
|
||||
int deleted_total = GetSize(deleter.del_wires_queue);
|
||||
|
||||
clean_ctx.stats.count_rm_wires += deleted_total;
|
||||
|
||||
if (clean_ctx.flags.verbose && deleted_and_unreported)
|
||||
log_debug(" removed %d unused temporary wires.\n", deleted_and_unreported);
|
||||
|
||||
if (deleted_total)
|
||||
module->design->scratchpad_set_bool("opt.did_something", true);
|
||||
|
||||
return deleted_total != 0;
|
||||
}
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
Loading…
Reference in New Issue