Stefan Frederik 36b8c30fcc revert ngspice/autozero_comp.sch to previous version since ngspice has fixed parameters in agauss funtion; add tests/xschemtest.tcl		2021-12-09 23:39:07 +01:00
..
binto7seg	add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports	2021-01-06 00:12:04 +01:00
devices	swap s/d in verilog netlisting rule for enhancement load "rnmos4.sym" so it can be used as usually done with nmos devices (drain side up) .	2021-12-01 15:53:14 +01:00
examples	new find_inst_to_be_redrawn() implementation to recalculate area to be redrawn with/without show net names on symbol pins, simplified new_window() call in callback `x` command, code formatting in globals.c, added xschem get [xy]origin commands	2021-12-03 19:15:07 +01:00
gschem_import	some parameter checks in xschem commands, global var removal in simulation help window - No use for production yet	2021-11-16 22:28:10 +01:00
logic	removed comment in schematic test_verilog_verilog.sch	2021-12-01 15:58:26 +01:00
ngspice	revert ngspice/autozero_comp.sch to previous version since ngspice has fixed parameters in agauss funtion; add tests/xschemtest.tcl	2021-12-09 23:39:07 +01:00
pcb	Windows does not recognize XPending, fix typo for verilog_format`s port name: g instead of f	2021-11-26 13:16:52 +01:00
rom8k	added hierarchical ps/pdf export (File menu)	2021-06-13 23:55:17 +02:00
rulz-r8c33	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
symgen	removed unused files	2020-08-24 10:01:41 +02:00
xTAG	populating xschem git repo	2020-08-08 15:47:34 +02:00
xschem_simulator	static function rename	2021-12-09 13:43:00 +01:00
Makefile	added "xschem_simulator" sample example directory for trying logic propagation of probed nets	2020-12-26 19:26:33 +01:00