revert ngspice/autozero_comp.sch to previous version since ngspice has fixed parameters in agauss funtion; add tests/xschemtest.tcl
This commit is contained in:
Stefan Frederik
parent
9e2f3816fd
commit
36b8c30fcc
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@ -0,0 +1,194 @@
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## xschemtest.tcl
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## script for testing various xschem functions:
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## works on xschem versions newer than r1819
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## - drawing and drawing speed, with selections and highlights
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## - netlisting in various formats
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## - show net names on instance pins
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## - logic simulation engine
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## - print png, svg, pdf
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## - trim wires
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## run:
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# xschem --script /path/to/drawtest.tcl
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## optionally with logging to catch memory leaks:
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# xschem -d 3 -l log --script /path/to/drawtest.tcl
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## and then running: xschemtest
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## running this test with different xschem versions with profiling enabled (-pg)
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## allows to see differences in number of function calls / time spent.
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## calculate 32 bit hash of file, used to compare files.
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## This is NOT a crypto hash, and NOT even a strong collision resistant hash
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## but for our purposes this is enough
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proc hash_file {f} {
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set hash 5381
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set fd [open $f r]
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fconfigure $fd -encoding binary -translation binary
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set data [read $fd]
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## hash should be the same on windows: remove carriage returns
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regsub -all {\r} $data {} data
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close $fd
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for {set i 0} {$i < [string length $data]} {incr i} {
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set asciicode [scan [string index $data $i] %c]
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set hash [expr {($hash * 33 + $asciicode) & 0xffffffff}]
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}
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return $hash
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}
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## move schematic and redraw in a loop.
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proc drawtest {} {
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set increment 5.0
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set a [time {
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for { set i 0 } { $i < 100 } { incr i} {
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set x [xschem get xorigin]
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set y [xschem get yorigin]
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set x [expr {$x +$increment}]
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set y [expr {$y +$increment}]
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xschem origin $x $y
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xschem redraw
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}
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}]
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set a [lindex $a 0]
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set fps [expr {100.0 / $a * 1e6} ] ;# calculate drawing frames per second
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puts "[rel_sym_path [xschem get schname]]: draw speed: $fps fps"
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}
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proc copy_paste_test {} {
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xschem zoom_box -18000 -18000 18000 18000
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xschem select_all
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set n [xschem get lastsel]
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xschem copy
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for { set i 3000 } {$i < 12001} { set i [expr {$i + 3000}]} {
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xschem paste 0 $i
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xschem paste 0 -$i
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xschem paste $i 0
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xschem paste -$i 0
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xschem paste $i $i
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xschem paste $i -$i
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xschem paste -$i $i
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xschem paste -$i -$i
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}
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update
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xschem select_all
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set m [xschem get lastsel]
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if { $m == $n * 33 } {
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puts "Copy / paste 32 additional circuits: $m elements == $n * 33. OK"
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} else {
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puts "Copy / paste 32 additional circuits: $m elements != $n * 33. FAIL"
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}
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xschem unselect_all
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xschem clear force
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}
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## draw a grid of long vertical wires and small horizontal wire segments
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## after a trim wire operation vertical wires are cut at intersection points.
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proc draw_trim_wiregrid {} {
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xschem unhilight_all
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xschem clear force
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xschem set no_undo 1
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for {set i 0} {$i < 129} {incr i} {
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set x [expr {$i * 40.0}]
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set y [expr {128.0*40}]
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xschem wire $x 0 $x $y
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}
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for {set i 0} {$i < 129} {incr i} {
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for {set j 0} {$j < 128} {incr j} {
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set x1 [expr {$j * 40}]
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set x2 [expr {$j * 40 + 40}]
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set y [expr {$i * 40}]
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xschem wire $x1 $y $x2 $y
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}
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}
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xschem set no_undo 0
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xschem zoom_full
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update ;# so updated window will be visible.
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xschem trim_wires ;# will also draw result
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update
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xschem select_all
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set n [xschem get lastsel]
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xschem unselect_all
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## if all wires trimmed correctly we should have 129*128*2 = 33024 segments.
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if {$n == 33024} { puts "trim wire test: $n segments, OK"} else { puts "trim wire test FAIL"}
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after 200 { xschem clear force}
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}
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proc xschemtest {{view 0}} {
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global tclstop netlist_dir OS XSCHEM_SHAREDIR show_pin_net_names
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set t [time {
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## make sure ERC window wil not pop up above schematic while doing tests
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wm deiconify .infotext
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lower .infotext
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for {set n 0} {$n < 7} {incr n} {
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set show_pin_net_names 0
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if {$n % 7 == 1} {
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xschem set netlist_type verilog
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xschem load [abs_sym_path greycnt.sch]
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} elseif {$n % 7 == 2} {
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xschem set netlist_type spice
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xschem load [abs_sym_path autozero_comp.sch]
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xschem print png autozero_comp.png
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} elseif {$n % 7 == 3} {
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xschem set netlist_type vhdl
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xschem load [abs_sym_path loading.sch]
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} elseif {$n % 7 == 4} {
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xschem set netlist_type spice
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set show_pin_net_names 1
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xschem load [abs_sym_path mos_power_ampli.sch]
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xschem print svg mos_power_ampli.svg
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} elseif {$n % 7 == 5} {
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xschem set netlist_type spice
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xschem load [abs_sym_path LCC_instances.sch]
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} elseif {$n % 7 == 6} {
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xschem set netlist_type spice
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xschem load [abs_sym_path simulate_ff.sch]
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xschem print pdf simulate_ff.pdf
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eval [xschem getprop instance h3 tclcommand]
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} else {
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xschem set netlist_type spice
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xschem load [abs_sym_path rom8k.sch]
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}
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xschem search regex 1 lab . ;# select all nets
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xschem hilight ;# hilight all selected nets and labels
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xschem unselect_all
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xschem netlist
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drawtest
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if { $n == 4} { copy_paste_test }
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}
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xschem clear force
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draw_trim_wiregrid
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## check netlist hashes, compare with gold hashes
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foreach {f h} {
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greycnt.v 389394682
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mos_power_ampli.spice 1186348644
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autozero_comp.spice 1416313184
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loading.vhdl 3834408538
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LCC_instances.spice 3918341865
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simulate_ff.spice 1321596936
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rom8k.spice 2198713988
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} {
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if { [hash_file $netlist_dir/$f] == $h } {
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puts "$f netlist check OK"
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} else {
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puts "$f netlist check FAIL"
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}
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}
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## test print files. Exact file content depend on window size and conversion tool,
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## so we simply check if existing and size > 0.
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foreach i {autozero_comp.png mos_power_ampli.svg simulate_ff.pdf} {
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if {$view && $OS ne {Windows}} {
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execute 0 xdg-open $i
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alert_ "Check if $i print file look fine"
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}
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if {[file exists $i] && [file size $i] > 0} {
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puts "print file $i exists. OK"
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} else {
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puts "print file $i not existing or empty. FAIL"
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}
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file delete $i
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}
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}]
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puts $t
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}
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## this is the test to run from xschem console after sourcing this file
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# xschemtest
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@ -26,7 +26,7 @@ T {SENSING
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30ns} 530 -300 0 1 0.4 0.4 {}
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T {OFF} 660 -300 0 1 0.4 0.4 {}
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T {OFF} 210 -300 0 1 0.4 0.4 {}
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T {NGSPICE MONTE CARLO SIMULATION} 1210 -310 0 0 0.8 0.8 {}
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T {NGSPICE MISMATCH SIMULATION} 1210 -310 0 0 0.8 0.8 {}
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T {Offset-compensated comparator. Detects +/- 2mv differential signal on PLUS, MINUS.
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Output on SAOUT
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Gaussian Threshold variation (via delvto parameter) is added to all MOS transistors.} 1110 -240 0 0 0.6 0.6 {}
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@ -141,7 +141,7 @@ N 1960 -1330 2060 -1330 {lab=ZERO2}
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N 1850 -800 1920 -800 {lab=SAOUTF}
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N 1850 -510 1920 -510 {lab=SAOUTF}
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N 1470 -710 1710 -710 {lab=SAOUTF}
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N 2180 -710 2290 -710 {lab=SAOUT}
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N 1960 -710 2290 -710 {lab=SAOUT}
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N 1850 -800 1850 -710 {lab=SAOUTF}
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N 1960 -770 1960 -710 {lab=SAOUT}
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N 1470 -770 1470 -710 {lab=SAOUTF}
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@ -151,9 +151,9 @@ N 2180 -880 2180 -840 {lab=VCC}
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N 2180 -780 2180 -710 {lab=SAOUT}
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N 590 -770 620 -770 {lab=VCC}
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N 420 -830 420 -800 {lab=SP}
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N 530 -830 620 -830 {lab=SP}
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N 520 -830 620 -830 {lab=SP}
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N 620 -830 620 -800 {lab=SP}
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N 420 -830 530 -830 {lab=SP}
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N 420 -830 520 -830 {lab=SP}
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N 420 -770 450 -770 {lab=VCC}
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N 390 -640 420 -640 {lab=VSS}
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N 620 -640 650 -640 {lab=VSS}
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@ -161,9 +161,9 @@ N 460 -640 580 -640 {lab=GP}
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N 460 -670 460 -640 {lab=GP}
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N 420 -670 460 -670 {lab=GP}
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N 420 -740 420 -670 {lab=GP}
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N 620 -700 620 -670 {lab=OUTDIFF}
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N 620 -740 620 -670 {lab=OUTDIFF}
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N 620 -610 620 -590 {lab=VSSI}
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N 520 -590 620 -590 {lab=VSSI}
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N 420 -590 620 -590 {lab=VSSI}
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N 420 -610 420 -590 {lab=VSSI}
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N 490 -550 520 -550 {lab=VSSI}
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N 520 -590 520 -550 {lab=VSSI}
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@ -171,9 +171,6 @@ N 530 -900 560 -900 {lab=VCC}
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N 530 -870 530 -830 {lab=SP}
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N 530 -950 530 -930 {lab=VCC}
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N 620 -700 680 -700 {lab=OUTDIFF}
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N 1960 -710 2180 -710 {lab=SAOUT}
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N 420 -590 520 -590 {lab=VSSI}
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N 620 -740 620 -700 {lab=OUTDIFF}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {ipin.sym} 110 -850 0 0 { name=p92 lab=CAL }
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C {ipin.sym} 110 -910 0 0 { name=p93 lab=PLUS }
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@ -191,10 +188,10 @@ C {code.sym} 840 -190 0 0 {name=STIMULI
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only_toplevel=true
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place=end
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value="* .option SCALE=1e-6
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.option method=gear
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.option method=gear $$ seed=12
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.param VCC=0.9
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.param VDL='VCC/2+0.2'
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.param delvto_var='agauss(0,0.05,3)'
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.param ABSVAR=0.05
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.temp 25
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** to generate following file:
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@ -211,7 +208,6 @@ value="* .option SCALE=1e-6
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* .tran 0.1n 900n uic
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.control
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option seed=12
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let run=1
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dowhile run <= 10
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@ -240,49 +236,49 @@ C {lab_pin.sym} 190 -1180 0 1 {name=p283 lab=VSS}
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C {lab_pin.sym} 120 -1180 0 0 {name=l56 lab=EN}
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C {lab_pin.sym} 160 -1130 0 0 {name=p284 lab=VSS}
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C {lab_pin.sym} 160 -1230 0 0 {name=p199 lab=VSSI}
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C {nmos4-v.sym} 140 -1180 0 0 {name=M67 verilog_gate=nmos del=50,50,50 model=nmos w=5u l=0.13u extra="delvto='delvto_var'"}
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C {nmos4-v.sym} 140 -1180 0 0 {name=M67 verilog_gate=nmos del=50,50,50 model=nmos w=5u l=0.13u extra="delvto='agauss(0,ABSVAR,3)'"}
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C {parax_cap.sym} 160 -1120 0 0 {name=c38 value=2p}
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C {passgate.sym} 860 -1260 0 1 {name=x1 m=1
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+ wn=0.4u ln=0.13u
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+ wp=0.4u lp=0.13u
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+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='delvto_var'"}
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+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='agauss(0,ABSVAR,3)'"}
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C {lab_pin.sym} 860 -1290 0 1 {name=l19 sig_type=std_logic lab=CALB}
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C {lab_pin.sym} 860 -1230 0 1 {name=l44 sig_type=std_logic lab=CALBB}
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C {nmos4-v.sym} 1100 -1100 0 0 {name=M3 verilog_gate=nmos del=50,50,50 model=nmos w=1.0u l=1.0u extra="delvto='delvto_var'"}
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C {nmos4-v.sym} 1100 -1100 0 0 {name=M3 verilog_gate=nmos del=50,50,50 model=nmos w=1.0u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
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C {lab_pin.sym} 1150 -1100 0 1 {name=p179 lab=VSS}
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C {pmos4-v.sym} 1100 -1330 0 0 {name=M4 verilog_gate=pmos del=50,50,50 model=pmos w=2.0u l=1.0u extra="delvto='delvto_var'"}
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C {pmos4-v.sym} 1100 -1330 0 0 {name=M4 verilog_gate=pmos del=50,50,50 model=pmos w=2.0u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
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C {lab_pin.sym} 1150 -1330 0 1 {name=p180 lab=VCC}
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C {lab_pin.sym} 1090 -1400 0 0 {name=p181 lab=VCC}
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C {lab_pin.sym} 1090 -970 0 0 {name=p182 lab=VSSI}
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C {passgate.sym} 1350 -1260 0 1 {name=x2 m=1
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+ wn=0.4u ln=0.13u
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+ wp=0.4u lp=0.13u
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+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='delvto_var'"}
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+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='agauss(0,ABSVAR,3)'"}
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C {lab_pin.sym} 1350 -1290 0 1 {name=l45 sig_type=std_logic lab=CALB}
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C {lab_pin.sym} 1350 -1230 0 1 {name=l46 sig_type=std_logic lab=CALBB}
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C {nmos4-v.sym} 1590 -1100 0 0 {name=M7 verilog_gate=nmos del=50,50,50 model=nmos w=1.3u l=1.0u extra="delvto='delvto_var'"}
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C {nmos4-v.sym} 1590 -1100 0 0 {name=M7 verilog_gate=nmos del=50,50,50 model=nmos w=1.3u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
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C {lab_pin.sym} 1640 -1100 0 1 {name=p183 lab=VSS}
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C {pmos4-v.sym} 1590 -1330 0 0 {name=M9 verilog_gate=pmos del=50,50,50 model=pmos w=2.6u l=1.0u extra="delvto='delvto_var'"}
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C {pmos4-v.sym} 1590 -1330 0 0 {name=M9 verilog_gate=pmos del=50,50,50 model=pmos w=2.6u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
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C {lab_pin.sym} 1640 -1330 0 1 {name=p184 lab=VCC}
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C {lab_pin.sym} 1580 -1400 0 0 {name=p185 lab=VCC}
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C {lab_pin.sym} 1580 -970 0 0 {name=p186 lab=VSSI}
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C {lab_pin.sym} 1470 -1320 0 0 {name=l47 lab=ZERO1}
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C {lab_pin.sym} 980 -1320 0 0 {name=l48 lab=ZERO0}
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C {nmos4-v.sym} 870 -640 0 0 {name=M20 verilog_gate=nmos del=50,50,50 model=nmos w=2u l=0.4u extra="delvto='delvto_var'"}
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C {nmos4-v.sym} 1110 -640 0 1 {name=M8 verilog_gate=nmos del=50,50,50 model=nmos w=2u l=0.4u extra="delvto='delvto_var'"}
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C {nmos4-v.sym} 870 -640 0 0 {name=M20 verilog_gate=nmos del=50,50,50 model=nmos w=2u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
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C {nmos4-v.sym} 1110 -640 0 1 {name=M8 verilog_gate=nmos del=50,50,50 model=nmos w=2u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
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C {lab_pin.sym} 920 -640 0 1 {name=p187 lab=VSS}
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C {lab_pin.sym} 1060 -640 0 0 {name=p188 lab=VSS}
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C {pmos4-v.sym} 1070 -800 0 0 {name=M30 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='delvto_var'"}
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C {pmos4-v.sym} 1070 -800 0 0 {name=M30 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
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C {lab_pin.sym} 1120 -800 0 1 {name=p189 lab=VCC}
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C {pmos4-v.sym} 910 -800 0 1 {name=M12 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='delvto_var'"}
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C {pmos4-v.sym} 910 -800 0 1 {name=M12 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
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C {lab_pin.sym} 860 -800 0 0 {name=p190 lab=VCC}
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C {nmos4-v.sym} 970 -510 0 0 {name=M32 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='delvto_var'"}
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C {nmos4-v.sym} 970 -510 0 0 {name=M32 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
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C {lab_pin.sym} 1020 -510 0 1 {name=p191 lab=VSS}
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C {lab_pin.sym} 990 -880 0 0 {name=p192 lab=VCC}
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C {lab_pin.sym} 960 -380 0 0 {name=p193 lab=VSSI}
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C {nmos4-v.sym} 1450 -510 0 0 {name=M17 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='delvto_var'"}
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C {nmos4-v.sym} 1450 -510 0 0 {name=M17 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
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C {lab_pin.sym} 1500 -510 0 1 {name=p194 lab=VSS}
|
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C {pmos4-v.sym} 1450 -800 0 0 {name=M13 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='delvto_var'"}
|
||||
C {pmos4-v.sym} 1450 -800 0 0 {name=M13 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
||||
C {lab_pin.sym} 1500 -800 0 1 {name=p195 lab=VCC}
|
||||
C {lab_pin.sym} 1440 -870 0 0 {name=p196 lab=VCC}
|
||||
C {lab_pin.sym} 1440 -380 0 0 {name=p197 lab=VSSI}
|
||||
|
|
@ -301,9 +297,9 @@ C {ammeter.sym} 990 -450 0 0 {name=v2}
|
|||
C {ammeter.sym} 1470 -450 0 0 {name=v3}
|
||||
C {ammeter.sym} 1610 -1040 0 0 {name=v4}
|
||||
C {ammeter.sym} 1120 -1040 0 0 {name=v6}
|
||||
C {nmos4-v.sym} 1940 -510 0 0 {name=M19 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='delvto_var'"}
|
||||
C {nmos4-v.sym} 1940 -510 0 0 {name=M19 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
||||
C {lab_pin.sym} 1990 -510 0 1 {name=p9 lab=VSS}
|
||||
C {pmos4-v.sym} 1940 -800 0 0 {name=M21 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='delvto_var'"}
|
||||
C {pmos4-v.sym} 1940 -800 0 0 {name=M21 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
||||
C {lab_pin.sym} 1990 -800 0 1 {name=p10 lab=VCC}
|
||||
C {lab_pin.sym} 1930 -870 0 0 {name=p11 lab=VCC}
|
||||
C {lab_pin.sym} 1930 -380 0 0 {name=p12 lab=VSSI}
|
||||
|
|
@ -313,29 +309,29 @@ C {lab_pin.sym} 2290 -710 0 1 {name=l3 lab=SAOUT}
|
|||
C {passgate.sym} 1840 -1260 0 1 {name=x3 m=1
|
||||
+ wn=0.4u ln=0.13u
|
||||
+ wp=0.4u lp=0.13u
|
||||
+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='delvto_var'"}
|
||||
+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='agauss(0,ABSVAR,3)'"}
|
||||
C {lab_pin.sym} 1840 -1290 0 1 {name=l5 sig_type=std_logic lab=CALB}
|
||||
C {lab_pin.sym} 1840 -1230 0 1 {name=l6 sig_type=std_logic lab=CALBB}
|
||||
C {nmos4-v.sym} 2080 -1100 0 0 {name=M23 verilog_gate=nmos del=50,50,50 model=nmos w=1.5u l=1.0u extra="delvto='delvto_var'"}
|
||||
C {nmos4-v.sym} 2080 -1100 0 0 {name=M23 verilog_gate=nmos del=50,50,50 model=nmos w=1.5u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
|
||||
C {lab_pin.sym} 2130 -1100 0 1 {name=p13 lab=VSS}
|
||||
C {pmos4-v.sym} 2080 -1330 0 0 {name=M24 verilog_gate=pmos del=50,50,50 model=pmos w=3u l=1.0u extra="delvto='delvto_var'"}
|
||||
C {pmos4-v.sym} 2080 -1330 0 0 {name=M24 verilog_gate=pmos del=50,50,50 model=pmos w=3u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
|
||||
C {lab_pin.sym} 2130 -1330 0 1 {name=p14 lab=VCC}
|
||||
C {lab_pin.sym} 2070 -1400 0 0 {name=p16 lab=VCC}
|
||||
C {lab_pin.sym} 2070 -970 0 0 {name=p17 lab=VSSI}
|
||||
C {lab_pin.sym} 1960 -1320 0 0 {name=l8 lab=ZERO2}
|
||||
C {ammeter.sym} 2100 -1040 0 0 {name=v5}
|
||||
C {pmos4-v.sym} 2160 -810 0 0 {name=M6 verilog_gate=pmos del=50,50,50 model=pmos w=0.6u l=0.2u extra="delvto='delvto_var'"}
|
||||
C {pmos4-v.sym} 2160 -810 0 0 {name=M6 verilog_gate=pmos del=50,50,50 model=pmos w=0.6u l=0.2u extra="delvto='agauss(0,ABSVAR,3)'"}
|
||||
C {lab_pin.sym} 2210 -810 0 1 {name=p18 lab=VCC}
|
||||
C {lab_pin.sym} 2150 -880 0 0 {name=p19 lab=VCC}
|
||||
C {lab_pin.sym} 2140 -810 0 0 {name=l2 lab=EN}
|
||||
C {pmos4-v.sym} 640 -770 0 1 {name=M18 verilog_gate=pmos del=50,50,50 model=pmos w=4u l=0.4u extra="delvto='delvto_var'"}
|
||||
C {pmos4-v.sym} 640 -770 0 1 {name=M18 verilog_gate=pmos del=50,50,50 model=pmos w=4u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
|
||||
C {lab_pin.sym} 590 -770 0 0 {name=p20 lab=VCC}
|
||||
C {pmos4-v.sym} 400 -770 0 0 {name=M25 verilog_gate=pmos del=50,50,50 model=pmos w=4u l=0.4u extra="delvto='delvto_var'"}
|
||||
C {pmos4-v.sym} 400 -770 0 0 {name=M25 verilog_gate=pmos del=50,50,50 model=pmos w=4u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
|
||||
C {lab_pin.sym} 450 -770 0 1 {name=p21 lab=VCC}
|
||||
C {lab_pin.sym} 390 -640 0 0 {name=p22 lab=VSS}
|
||||
C {lab_pin.sym} 650 -640 0 1 {name=p23 lab=VSS}
|
||||
C {lab_pin.sym} 490 -550 0 0 {name=p24 lab=VSSI}
|
||||
C {pmos4-v.sym} 510 -900 0 0 {name=M28 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='delvto_var'"}
|
||||
C {pmos4-v.sym} 510 -900 0 0 {name=M28 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
||||
C {lab_pin.sym} 560 -900 0 1 {name=p25 lab=VCC}
|
||||
C {lab_pin.sym} 530 -950 0 0 {name=p26 lab=VCC}
|
||||
C {lab_pin.sym} 490 -900 0 0 {name=l7 lab=GP}
|
||||
|
|
@ -343,8 +339,8 @@ C {lab_pin.sym} 460 -670 0 1 {name=l9 lab=GP}
|
|||
C {lab_pin.sym} 380 -770 0 0 {name=l10 lab=MINUS}
|
||||
C {lab_pin.sym} 660 -770 0 1 {name=l11 lab=PLUS}
|
||||
C {lab_pin.sym} 680 -700 0 1 {name=l12 lab=OUTDIFF}
|
||||
C {nmos4-v.sym} 600 -640 0 0 {name=M26 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='delvto_var'"}
|
||||
C {nmos4-v.sym} 440 -640 0 1 {name=M1 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='delvto_var'"}
|
||||
C {nmos4-v.sym} 600 -640 0 0 {name=M26 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
||||
C {nmos4-v.sym} 440 -640 0 1 {name=M1 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
|
||||
C {parax_cap.sym} 500 -630 0 0 {name=c2 value=4f}
|
||||
C {lab_pin.sym} 530 -850 0 0 {name=l13 lab=SP}
|
||||
C {launcher.sym} 930 -260 0 0 {name=h2
|
||||
|
|
|
|||
Loading…
Reference in New Issue