sv2v/sv2v.cabal

name: sv2v
version: 0.0.1
synopsis: SystemVerilog to Verilog conversion
description:
  A tool for coverting SystemVerilog to Verilog. Originally forked from the
  Verilog parser found at https://github.com/tomahawkins/verilog
category: Language, Hardware, Embedded, Development

author: Zachary Snow <zach@zachjs.com>, Tom Hawkins <tomahawkins@gmail.com>
maintainer: Zachary Snow <zach@zachjs.com>
license: BSD3
license-file: LICENSE
homepage: https://github.com/zachjs/sv2v

build-type: Simple
cabal-version: >= 1.12

executable sv2v
  default-language: Haskell2010
  main-is: sv2v.hs
  hs-source-dirs: src
  build-tools:
    alex  >= 3 && < 4,
    happy >= 1 && < 2
  build-depends:
    array,
    base,
    cmdargs,
    containers,
    directory,
    filepath,
    hashable,
    mtl,
    Unique
  other-modules:
    -- SystemVerilog modules
    Language.SystemVerilog
    Language.SystemVerilog.AST
    Language.SystemVerilog.AST.Attr
    Language.SystemVerilog.AST.Decl
    Language.SystemVerilog.AST.Description
    Language.SystemVerilog.AST.Expr
    Language.SystemVerilog.AST.GenItem
    Language.SystemVerilog.AST.LHS
    Language.SystemVerilog.AST.ModuleItem
    Language.SystemVerilog.AST.Op
    Language.SystemVerilog.AST.ShowHelp
    Language.SystemVerilog.AST.Stmt
    Language.SystemVerilog.AST.Type
    Language.SystemVerilog.Parser
    Language.SystemVerilog.Parser.Lex
    Language.SystemVerilog.Parser.Parse
    Language.SystemVerilog.Parser.ParseDecl
    Language.SystemVerilog.Parser.Tokens
    -- Conversion modules
    Convert
    Convert.AlwaysKW
    Convert.AsgnOp
    Convert.Assertion
    Convert.BlockDecl
    Convert.DimensionQuery
    Convert.EmptyArgs
    Convert.Enum
    Convert.ForDecl
    Convert.FuncRet
    Convert.Interface
    Convert.IntTypes
    Convert.KWArgs
    Convert.Logic
    Convert.NamedBlock
    Convert.NestPI
    Convert.Package
    Convert.PackedArray
    Convert.ParamType
    Convert.RemoveComments
    Convert.Return
    Convert.Simplify
    Convert.StarPort
    Convert.StmtBlock
    Convert.Stream
    Convert.Struct
    Convert.Typedef
    Convert.Traverse
    Convert.UnbasedUnsized
    Convert.Unique
    -- sv2v CLI modules
    Job
  ghc-options:
    -O3
    -threaded
    -rtsopts
    -with-rtsopts=-N
    -funbox-strict-fields
    -Wall
    -j

source-repository head
  type:     git
  location: git://github.com/zachjs/sv2v.git
directory re-org; streamline build setup 2019-02-28 19:52:31 +01:00			`name: sv2v`
Refactor project setup for our purposes 2019-02-08 06:19:39 +01:00			`version: 0.0.1`
			`synopsis: SystemVerilog to Verilog conversion`
			`description:`
directory re-org; streamline build setup 2019-02-28 19:52:31 +01:00			`A tool for coverting SystemVerilog to Verilog. Originally forked from the`
			`Verilog parser found at https://github.com/tomahawkins/verilog`
			`category: Language, Hardware, Embedded, Development`
Refactor project setup for our purposes 2019-02-08 06:19:39 +01:00
directory re-org; streamline build setup 2019-02-28 19:52:31 +01:00			`author: Zachary Snow <zach@zachjs.com>, Tom Hawkins <tomahawkins@gmail.com>`
Refactor project setup for our purposes 2019-02-08 06:19:39 +01:00			`maintainer: Zachary Snow <zach@zachjs.com>`
directory re-org; streamline build setup 2019-02-28 19:52:31 +01:00			`license: BSD3`
Refactor project setup for our purposes 2019-02-08 06:19:39 +01:00			`license-file: LICENSE`
			`homepage: https://github.com/zachjs/sv2v`

directory re-org; streamline build setup 2019-02-28 19:52:31 +01:00			`build-type: Simple`
			`cabal-version: >= 1.12`
Refactor project setup for our purposes 2019-02-08 06:19:39 +01:00
			`executable sv2v`
			`default-language: Haskell2010`
			`main-is: sv2v.hs`
directory re-org; streamline build setup 2019-02-28 19:52:31 +01:00			`hs-source-dirs: src`
switch to using stack 2019-02-12 05:44:02 +01:00			`build-tools:`
			`alex >= 3 && < 4,`
			`happy >= 1 && < 2`
Basic build setup! 2019-02-08 07:09:10 +01:00			`build-depends:`
			`array,`
added logic to module items; toying with initial Conversion 2019-02-18 05:39:01 +01:00			`base,`
split up Yosys and VTR targeting 2019-02-26 21:03:49 +01:00			`cmdargs,`
initial work on Traverse AST transformations 2019-02-25 08:36:37 +01:00			`containers,`
updated CLI to support include dirs and multiple files 2019-03-29 00:55:53 +01:00			`directory,`
completely rewrote preprocessor; more extensive directive support (include, timescale) 2019-03-18 10:00:23 +01:00			`filepath,`
struct conversion uses packing functions to force field width 2019-04-22 03:56:23 +02:00			`hashable,`
use the Unique package in a few places 2019-09-12 05:01:34 +02:00			`mtl,`
			`Unique`
Basic build setup! 2019-02-08 07:09:10 +01:00			`other-modules:`
directory re-org; streamline build setup 2019-02-28 19:52:31 +01:00			`-- SystemVerilog modules`
updated build procedure 2019-02-08 22:51:32 +01:00			`Language.SystemVerilog`
			`Language.SystemVerilog.AST`
surprisingly non-disgusting addition of attribute instances to module items and statements 2019-03-26 06:54:16 +01:00			`Language.SystemVerilog.AST.Attr`
split out Decl, LHS, and Stmt into separate AST modules 2019-03-25 18:29:35 +01:00			`Language.SystemVerilog.AST.Decl`
final major round of splitting and cleanup in the SystemVerilog module 2019-04-04 02:24:09 +02:00			`Language.SystemVerilog.AST.Description`
starting work to clean up and segment AST 2019-03-23 00:24:45 +01:00			`Language.SystemVerilog.AST.Expr`
final major round of splitting and cleanup in the SystemVerilog module 2019-04-04 02:24:09 +02:00			`Language.SystemVerilog.AST.GenItem`
split out Decl, LHS, and Stmt into separate AST modules 2019-03-25 18:29:35 +01:00			`Language.SystemVerilog.AST.LHS`
final major round of splitting and cleanup in the SystemVerilog module 2019-04-04 02:24:09 +02:00			`Language.SystemVerilog.AST.ModuleItem`
starting work to clean up and segment AST 2019-03-23 00:24:45 +01:00			`Language.SystemVerilog.AST.Op`
			`Language.SystemVerilog.AST.ShowHelp`
split out Decl, LHS, and Stmt into separate AST modules 2019-03-25 18:29:35 +01:00			`Language.SystemVerilog.AST.Stmt`
starting work to clean up and segment AST 2019-03-23 00:24:45 +01:00			`Language.SystemVerilog.AST.Type`
Basic build setup! 2019-02-08 07:09:10 +01:00			`Language.SystemVerilog.Parser`
updated build procedure 2019-02-08 22:51:32 +01:00			`Language.SystemVerilog.Parser.Lex`
			`Language.SystemVerilog.Parser.Parse`
support for interfaces; new "declaration parser" 2019-03-04 08:58:00 +01:00			`Language.SystemVerilog.Parser.ParseDecl`
updated build procedure 2019-02-08 22:51:32 +01:00			`Language.SystemVerilog.Parser.Tokens`
directory re-org; streamline build setup 2019-02-28 19:52:31 +01:00			`-- Conversion modules`
added logic to module items; toying with initial Conversion 2019-02-18 05:39:01 +01:00			`Convert`
always construct conversion; more modular conversion approach 2019-02-18 07:38:16 +01:00			`Convert.AlwaysKW`
added conversion for genvar iteration AsgnOps 2019-03-05 01:58:54 +01:00			`Convert.AsgnOp`
significantly stronger support, and proper handling of assertions 2019-04-04 01:08:30 +02:00			`Convert.Assertion`
conversion for block decls with asignments 2019-09-02 19:08:41 +02:00			`Convert.BlockDecl`
conversion for array query system functions (resolves #37) 2019-09-14 22:42:54 +02:00			`Convert.DimensionQuery`
parse and convert empty function arguments (resolves #17) 2019-08-29 02:28:56 +02:00			`Convert.EmptyArgs`
initial version of enum conversion 2019-03-01 04:44:31 +01:00			`Convert.Enum`
convert for loop declarations and assignments to signle assignment (closes #15) 2019-08-30 06:11:57 +02:00			`Convert.ForDecl`
function return type logic to implicit conversion 2019-03-06 20:36:16 +01:00			`Convert.FuncRet`
first half of interface conversion 2019-03-07 02:30:47 +01:00			`Convert.Interface`
basic conversion for int, byte, shortint, and longint 2019-04-24 20:00:08 +02:00			`Convert.IntTypes`
added conversion for name task and function arguments 2019-04-01 19:16:21 +02:00			`Convert.KWArgs`
always construct conversion; more modular conversion approach 2019-02-18 07:38:16 +01:00			`Convert.Logic`
added conversion which adds names to unnamed blocks with decls 2019-04-20 01:08:52 +02:00			`Convert.NamedBlock`
conversions are applied per-file - NestTF refactored to cover all package items - fixed issue where type traverse skipped typedefs 2019-04-24 00:44:45 +02:00			`Convert.NestPI`
added preliminary package conversion 2019-04-24 02:22:03 +02:00			`Convert.Package`
significant refactor of packed array flatten conversion; now supports module items in generate blocks 2019-02-28 06:16:53 +01:00			`Convert.PackedArray`
initial parameter type conversion 2019-09-11 09:27:18 +02:00			`Convert.ParamType`
remove comments by default; added --verbose flag 2019-08-29 01:48:25 +02:00			`Convert.RemoveComments`
preliminary struct conversion; return conversion 2019-03-06 06:51:09 +01:00			`Convert.Return`
substitution conversion for size casts (closes #27) 2019-09-12 04:52:01 +02:00			`Convert.Simplify`
suport for in module instantiations 2019-02-20 21:22:26 +01:00			`Convert.StarPort`
added conversion to make functions and tasks use only one statement 2019-03-27 02:43:27 +01:00			`Convert.StmtBlock`
preliminary stream conversion 2019-09-04 05:36:29 +02:00			`Convert.Stream`
preliminary struct conversion; return conversion 2019-03-06 06:51:09 +01:00			`Convert.Struct`
very preliminary support for typedefs 2019-02-18 09:59:17 +01:00			`Convert.Typedef`
initial work on Traverse AST transformations 2019-02-25 08:36:37 +01:00			`Convert.Traverse`
simple conversion for unbased unsized literals 2019-03-19 18:40:25 +01:00			`Convert.UnbasedUnsized`
broader operator support; other parser cleanup 2019-03-05 00:25:14 +01:00			`Convert.Unique`
directory re-org; streamline build setup 2019-02-28 19:52:31 +01:00			`-- sv2v CLI modules`
cleaned up command line args module a bit 2019-02-28 20:06:35 +01:00			`Job`
Refactor project setup for our purposes 2019-02-08 06:19:39 +01:00			`ghc-options:`
			`-O3`
			`-threaded`
			`-rtsopts`
			`-with-rtsopts=-N`
			`-funbox-strict-fields`
			`-Wall`
switch to parallel builds 2019-03-27 08:41:02 +01:00			`-j`
Refactor project setup for our purposes 2019-02-08 06:19:39 +01:00
			`source-repository head`
			`type: git`
			`location: git://github.com/zachjs/sv2v.git`