added conversion which adds names to unnamed blocks with decls

src/Convert.hs

@@ -18,6 +18,7 @@ import qualified Convert.FuncRet
 import qualified Convert.Interface
 import qualified Convert.KWArgs
 import qualified Convert.Logic
+import qualified Convert.NamedBlock
 import qualified Convert.PackedArray
 import qualified Convert.Return
 import qualified Convert.StarPort
@@ -33,6 +34,7 @@ type Phase = AST -> AST
 phases :: [Job.Exclude] -> [Phase]
 phases excludes =
     [ Convert.AsgnOp.convert
+    , Convert.NamedBlock.convert
     , Convert.Assertion.convert
     , Convert.Bits.convert
     , selectExclude (Job.Logic    , Convert.Logic.convert)

src/Convert/NamedBlock.hs

@@ -0,0 +1,52 @@
+{- sv2v
+ - Author: Zachary Snow <zach@zachjs.com>
+ -
+ - Conversion for unnamed blocks with contain data declarations
+ -}
+
+module Convert.NamedBlock (convert) where
+
+import Control.Monad.State
+import qualified Data.Set as Set
+
+import Convert.Traverse
+import Language.SystemVerilog.AST
+
+type Idents = Set.Set Identifier
+
+convert :: AST -> AST
+convert ast =
+    -- we collect all the existing blocks in the first pass to make sure we
+    -- don't generate conflicting names on repeated passes of this conversion
+    evalState (runner collectStmtM ast >>= runner traverseStmtM) Set.empty
+    where runner = traverseDescriptionsM . traverseModuleItemsM . traverseStmtsM
+
+collectStmtM :: Stmt -> State Idents Stmt
+collectStmtM (Block (Just x) decls stmts) = do
+    modify $ Set.insert x
+    return $ Block (Just x) decls stmts
+collectStmtM other = return other
+
+traverseStmtM :: Stmt -> State Idents Stmt
+traverseStmtM (Block Nothing [] stmts) =
+    return $ Block Nothing [] stmts
+traverseStmtM (Block Nothing decls stmts) = do
+    names <- get
+    let x = uniqueBlockName names
+    modify $ Set.insert x
+    return $ Block (Just x) decls stmts
+traverseStmtM other = return other
+
+uniqueBlockName :: Idents -> Identifier
+uniqueBlockName names =
+    step ("sv2v_autoblock_" ++ (show $ Set.size names)) 0
+    where
+        step :: Identifier -> Int -> Identifier
+        step base n =
+            if Set.member name names
+                then step base (n + 1)
+                else name
+            where
+                name = if n == 0
+                    then base
+                    else base ++ "_" ++ show n

sv2v.cabal

@@ -62,6 +62,7 @@ executable sv2v
     Convert.Interface
     Convert.KWArgs
     Convert.Logic
+    Convert.NamedBlock
     Convert.PackedArray
     Convert.Return
     Convert.StarPort

test/basic/named_block.sv

@@ -0,0 +1,14 @@
+module top;
+    // The below blocks must be named when converted to Verilog-2005 because it
+    // contains a data declaration.
+    initial begin
+        integer i;
+        i = 1;
+        $display("%08d", i);
+    end
+    initial begin
+        integer i;
+        i = 1;
+        $display("%08d", i);
+    end
+endmodule

test/basic/named_block.v

@@ -0,0 +1,12 @@
+module top;
+    initial begin : block_name1
+        integer i;
+        i = 1;
+        $display("%08d", i);
+    end
+    initial begin : block_name2
+        integer i;
+        i = 1;
+        $display("%08d", i);
+    end
+endmodule

test/basic/named_block_tb.v

@@ -0,0 +1 @@
+// intentionally empty