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simple conversion for unbased unsized literals
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@ -20,6 +20,7 @@ import qualified Convert.Return
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import qualified Convert.StarPort
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import qualified Convert.Struct
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import qualified Convert.Typedef
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import qualified Convert.UnbasedUnsized
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import qualified Convert.Unique
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type Phase = AST -> AST
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@ -35,6 +36,7 @@ phases excludes =
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, Convert.Struct.convert
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, Convert.Return.convert
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, Convert.Typedef.convert
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, Convert.UnbasedUnsized.convert
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, Convert.Unique.convert
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]
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where
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@ -0,0 +1,29 @@
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- Conversion for unbased, unsized literals ('0, '1, 'z, 'x)
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-
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- Maintaining the unsized-ness of the literals is critical, but those digits
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- are all equivalent regardless of base. We simply convert them to all use a
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- binary base for compatability with Verilog-2005.
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-}
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module Convert.UnbasedUnsized (convert) where
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import Convert.Traverse
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import Language.SystemVerilog.AST
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convert :: AST -> AST
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convert =
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traverseDescriptions $ traverseModuleItems $
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traverseExprs $ traverseNestedExprs convertExpr
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digits :: [Char]
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digits = ['0', '1', 'x', 'z', 'X', 'Z']
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convertExpr :: Expr -> Expr
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convertExpr (Number ['\'', ch]) =
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if elem ch digits
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then Number ("'b" ++ [ch])
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else error $ "unexpected unbased-unsized digit: " ++ [ch]
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convertExpr other = other
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@ -53,6 +53,7 @@ executable sv2v
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Convert.Struct
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Convert.Typedef
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Convert.Traverse
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Convert.UnbasedUnsized
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Convert.Unique
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-- sv2v CLI modules
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Job
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