mirror of https://github.com/zachjs/sv2v.git
62 lines
1.3 KiB
Plaintext
62 lines
1.3 KiB
Plaintext
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name: sv2v
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version: 0.0.1
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category: Language, Hardware, Embedded
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synopsis: SystemVerilog to Verilog conversion
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description:
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A tool for coverting SystemVerilog to Verilog. Also exposes a limited
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SystemVerilog parser and AST. Forked from the Verilog parser found at
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https://github.com/tomahawkins/verilog
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author: Zachary Snow <zach@zachjs.com>, Tom Hawkins <tomahawkins@gmail.com>
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maintainer: Zachary Snow <zach@zachjs.com>
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license: BSD3
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license-file: LICENSE
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homepage: https://github.com/zachjs/sv2v
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build-type: Simple
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cabal-version: >= 1.10
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library
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default-language: Haskell2010
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build-tools:
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alex >= 3 && < 4,
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happy >= 1 && < 2
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build-depends:
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base >= 4.8.2.0 && < 5.0,
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array >= 0.5.1.0 && < 0.6
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exposed-modules:
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Data.BitVec
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Language.SystemVerilog
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Language.SystemVerilog.AST
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Language.SystemVerilog.Parser
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Language.SystemVerilog.Parser.Lex
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Language.SystemVerilog.Parser.Parse
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Language.SystemVerilog.Parser.Preprocess
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Language.SystemVerilog.Parser.Tokens
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ghc-options: -W
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executable sv2v
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default-language: Haskell2010
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main-is: sv2v.hs
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Build-Depends:
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base
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ghc-options:
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-O3
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-threaded
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-rtsopts
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-with-rtsopts=-N
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-funbox-strict-fields
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-Wall
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source-repository head
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type: git
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location: git://github.com/zachjs/sv2v.git
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