split up Yosys and VTR targeting

Args.hs

@@ -0,0 +1,32 @@
+{-# LANGUAGE DeriveDataTypeable #-}
+{- sv2v
+ - Author: Zachary Snow <zach@zachjs.com>
+ -
+ - Command line arguments.
+ -}
+
+module Args where
+
+import System.Console.CmdArgs
+
+data Target = VTR | YOSYS
+    deriving (Show, Typeable, Data)
+
+data Job = Job
+    { target :: Target
+    , file :: FilePath
+    } deriving (Show, Typeable, Data)
+
+defaultJob :: Job
+defaultJob = Job
+    { target = YOSYS &= typ "TARGET"
+        &= help "target sythesizer (yosys, vtr; defaults to yosys)"
+    , file = def &= args &= typFile
+    }
+    &= program "sv2v"
+    &= summary "sv2v v0.0.1, (C) Zachary Snow 2019, Tom Hawkins, 2011-2015"
+    &= details [ "sv2v converts SystemVerilog to Verilog."
+               , "More info: https://github.com/zachjs/sv2v" ]
+
+readArgs :: IO Job
+readArgs = cmdArgs defaultJob

Convert.hs

@@ -7,6 +7,7 @@
 module Convert (convert) where
 
 import Language.SystemVerilog.AST
+import qualified Args as Args
 
 import qualified Convert.AlwaysKW
 import qualified Convert.CaseKW
@@ -18,24 +19,29 @@ import qualified Convert.StarPort
 
 type Phase = AST -> AST
 
-phases :: [Phase]
-phases =
+phases :: Args.Target -> [Phase]
+phases Args.YOSYS =
+    [ Convert.Typedef.convert
+    , Convert.PackedArrayFlatten.convert
+    , Convert.StarPort.convert
+    ]
+phases Args.VTR =
+    (phases Args.YOSYS) ++
     [ Convert.AlwaysKW.convert
     , Convert.CaseKW.convert
     , Convert.Logic.convert
-    , Convert.Typedef.convert
-    , Convert.PackedArrayFlatten.convert
     , Convert.SplitPortDecl.convert
-    , Convert.StarPort.convert
     ]
 
-run :: Phase
-run = foldr (.) id phases
+run :: Args.Target -> Phase
+run target = foldr (.) id $ phases target
 
-convert :: Phase
-convert descriptions =
-    let descriptions' = run descriptions
-    in
-        if descriptions == descriptions'
-            then descriptions
-            else convert descriptions'
+convert :: Args.Target -> Phase
+convert target = convert'
+    where
+        convert' :: Phase
+        convert' descriptions =
+            if descriptions == descriptions'
+                then descriptions
+                else convert' descriptions'
+            where descriptions' = run target descriptions

README.md

@@ -1,13 +1,15 @@
 # sv2v: SystemVerilog to Verilog
 
 sv2v is a tool for converting synthesizable SystemVerilog into Verilog that is
-synthesizable by tools with more limited feature sets. This project was
-originally created for converting SystemVerilog into the [limited subset of
-Verilog] supported by [VTR]. However, sv2v is intended to be configurable and
-extensible so that it can be used with new and different toolchains and as
-Verilog keyword support evolves.
+synthesizable by tools with more limited feature sets. This project is primarily
+focused on converting SystemVerilog into the subset of Verilog supported by
+[Yosys]. However, sv2v also has support for targeting the [limited subset of
+Verilog] supported by [VTR]. In the long term, we hope for sv2v to be more
+configurable and extensible so that it can be used with new and different
+toolchains and as Verilog support evolves.
 
-[limited subset of Verilog]: https://vtr-verilog-to-routing.readthedocs.io/en/latest/odin/index.html#verilog-hdl-file-keyword-support
+[Yosys]: http://www.clifford.at/yosys/
+[limited subset of Verilog]: https://docs.verilogtorouting.org/en/latest/odin/#verilog-synthesizable-keyword-support
 [VTR]: https://github.com/verilog-to-routing/vtr-verilog-to-routing
 
 
@@ -36,8 +38,23 @@ This creates the executable at `./bin/sv2v`
 
 ## Usage
 
-The interface for this tool has not yet been finalized. Currently, running
-`bin/sv2v path/to/file.sv` will output the converted file to `stdout`.
+The interface for this tool has not yet been finalized. Currently, running `sv2v
+path/to/file.sv` will output the converted file to `stdout`.
+
+```
+sv2v [OPTIONS] [FILE]
+
+Common flags:
+  -t --target=TARGET    target sythesizer (yosys, vtr; defaults to yosys)
+  -? --help             Display help message
+```
+
+
+## VTR Support
+
+sv2v can target VTR by specifying `--target=vtr` on the command line. Note that
+VTR does not support `generate` blocks, and this tool is not capable of
+converting those at this time.
 
 
 ## SystemVerilog Parser/AST

sv2v.cabal

@@ -50,9 +50,11 @@ executable sv2v
   build-depends:
     array,
     base,
+    cmdargs,
     containers,
     mtl
   other-modules:
+    Args
     Language.SystemVerilog
     Language.SystemVerilog.AST
     Language.SystemVerilog.Parser

sv2v.hs

@@ -1,3 +1,4 @@
+{-# LANGUAGE DeriveDataTypeable #-}
 {- sv2v
  - Author: Zachary Snow <zach@zachjs.com>
  -
@@ -6,18 +7,18 @@
 
 import System.IO
 import System.Exit
-import System.Environment
-
-import Language.SystemVerilog.Parser
 
+import Args (readArgs, target, file)
 import Convert (convert)
+import Language.SystemVerilog.Parser
 
 main :: IO ()
 main = do
-    [filePath] <- getArgs
+    args <- readArgs
+    let filePath = file args
     content <- readFile filePath
     let ast = parseFile [] filePath content
-    let res = Right (convert ast)
+    let res = Right (convert (target args) ast)
     case res of
         Left  _ -> do
             --hPrint stderr err