mirror of https://github.com/zachjs/sv2v.git
split out Decl, LHS, and Stmt into separate AST modules
This commit is contained in:
Zachary Snow
parent
77f0d23d4b
commit
8907ac861d
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@ -18,28 +18,24 @@ module Language.SystemVerilog.AST
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, PackageItem(..)
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, ModuleItem (..)
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, Direction (..)
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, Stmt (..)
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, LHS (..)
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, Expr (..)
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, Sense (..)
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, Timing (..)
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, GenItem (..)
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, AlwaysKW (..)
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, CaseKW (..)
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, PartKW (..)
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, Decl (..)
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, Lifetime (..)
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, NInputGateKW (..)
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, NOutputGateKW (..)
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, AST
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, PortBinding
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, ModportDecl
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, Case
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, GenCase
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, simplify
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, rangeSize
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, module Decl
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, module Expr
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, module LHS
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, module Op
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, module Stmt
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, module Type
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) where
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@ -48,8 +44,11 @@ import Data.Maybe (maybe, fromJust, isJust)
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import Text.Printf (printf)
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import Text.Read (readMaybe)
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import Language.SystemVerilog.AST.Decl as Decl
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import Language.SystemVerilog.AST.Expr as Expr
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import Language.SystemVerilog.AST.LHS as LHS
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import Language.SystemVerilog.AST.Op as Op
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import Language.SystemVerilog.AST.Stmt as Stmt
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import Language.SystemVerilog.AST.Type as Type
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import Language.SystemVerilog.AST.ShowHelp
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@ -109,31 +108,6 @@ instance Show PartKW where
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show Module = "module"
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show Interface = "interface"
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data Direction
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= Input
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| Output
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| Inout
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| Local
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deriving Eq
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instance Show Direction where
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show Input = "input"
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show Output = "output"
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show Inout = "inout"
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show Local = ""
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data Decl
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= Parameter Type Identifier Expr
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| Localparam Type Identifier Expr
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| Variable Direction Type Identifier [Range] (Maybe Expr)
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deriving Eq
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instance Show Decl where
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showList l _ = unlines' $ map show l
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show (Parameter t x e) = printf "parameter %s%s = %s;" (showPad t) x (show e)
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show (Localparam t x e) = printf "localparam %s%s = %s;" (showPad t) x (show e)
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show (Variable d t x a me) = printf "%s%s %s%s%s;" (showPad d) (show t) x (showRanges a) (showAssignment me)
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data ModuleItem
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= MIDecl Decl
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| AlwaysC AlwaysKW Stmt
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@ -220,113 +194,6 @@ instance Show NOutputGateKW where
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show GateBuf = "buf"
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show GateNot = "not"
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data LHS
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= LHSIdent Identifier
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| LHSBit LHS Expr
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| LHSRange LHS Range
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| LHSDot LHS Identifier
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| LHSConcat [LHS]
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deriving Eq
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instance Show LHS where
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show (LHSIdent x ) = x
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show (LHSBit l e ) = printf "%s[%s]" (show l) (show e)
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show (LHSRange l (a, b)) = printf "%s[%s:%s]" (show l) (show a) (show b)
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show (LHSDot l x ) = printf "%s.%s" (show l) x
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show (LHSConcat lhss ) = printf "{%s}" (commas $ map show lhss)
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data CaseKW
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= CaseN
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| CaseZ
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| CaseX
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deriving Eq
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instance Show CaseKW where
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show CaseN = "case"
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show CaseZ = "casez"
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show CaseX = "casex"
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data Stmt
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= Block (Maybe Identifier) [Decl] [Stmt]
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| Case Bool CaseKW Expr [Case] (Maybe Stmt)
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| For (Identifier, Expr) Expr (Identifier, Expr) Stmt
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| AsgnBlk AsgnOp LHS Expr
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| Asgn (Maybe Timing) LHS Expr
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| While Expr Stmt
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| RepeatL Expr Stmt
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| DoWhile Expr Stmt
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| Forever Stmt
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| If Expr Stmt Stmt
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| Timing Timing Stmt
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| Return Expr
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| Subroutine Identifier [Maybe Expr]
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| Null
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deriving Eq
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instance Show Stmt where
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show (Block name decls stmts) =
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printf "begin%s\n%s\n%s\nend" header (block decls) (block stmts)
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where
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header = maybe "" (" : " ++) name
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block :: Show t => [t] -> String
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block = indent . unlines' . map show
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show (Case u kw e cs def) =
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printf "%s%s (%s)\n%s%s\nendcase" uniqStr (show kw) (show e) (indent $ unlines' $ map showCase cs) defStr
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where
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uniqStr = if u then "unique " else ""
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defStr = case def of
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Nothing -> ""
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Just c -> printf "\n\tdefault: %s" (show c)
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show (For (a,b) c (d,e) f) = printf "for (%s = %s; %s; %s = %s)\n%s" a (show b) (show c) d (show e) $ indent $ show f
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show (AsgnBlk o v e) = printf "%s %s %s;" (show v) (show o) (show e)
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show (Asgn t v e) = printf "%s <= %s%s;" (show v) (maybe "" showPad t) (show e)
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show (While e s) = printf "while (%s) %s" (show e) (show s)
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show (RepeatL e s) = printf "repeat (%s) %s" (show e) (show s)
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show (DoWhile e s) = printf "do %s while (%s);" (show s) (show e)
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show (Forever s ) = printf "forever %s" (show s)
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show (If a b Null) = printf "if (%s) %s" (show a) (show b)
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show (If a b c ) = printf "if (%s) %s\nelse %s" (show a) (show b) (show c)
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show (Return e ) = printf "return %s;" (show e)
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show (Subroutine x a) = printf "%s(%s);" x (commas $ map (maybe "" show) a)
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show (Timing t s ) = printf "%s%s" (show t) rest
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where
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rest = case s of
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Null -> ";"
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Block _ _ _ -> " " ++ (show s)
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_ -> "\n" ++ (indent $ show s)
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show (Null ) = ";"
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type Case = ([Expr], Stmt)
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showCase :: (Show x, Show y) => ([x], y) -> String
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showCase (a, b) = printf "%s: %s" (commas $ map show a) (show b)
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data Timing
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= Event Sense
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| Delay Expr
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| Cycle Expr
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deriving Eq
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instance Show Timing where
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show (Event s) = printf "@(%s)" (show s)
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show (Delay e) = printf "#(%s)" (show e)
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show (Cycle e) = printf "##(%s)" (show e)
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data Sense
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= Sense LHS
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| SenseOr Sense Sense
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| SensePosedge LHS
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| SenseNegedge LHS
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| SenseStar
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deriving Eq
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instance Show Sense where
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show (Sense a ) = show a
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show (SenseOr a b) = printf "%s or %s" (show a) (show b)
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show (SensePosedge a ) = printf "posedge %s" (show a)
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show (SenseNegedge a ) = printf "negedge %s" (show a)
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show (SenseStar ) = "*"
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type GenCase = ([Expr], GenItem)
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data GenItem
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@ -0,0 +1,42 @@
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
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-
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- SystemVerilog left-hand sides (aka lvals)
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-}
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module Language.SystemVerilog.AST.Decl
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( Decl (..)
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, Direction (..)
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) where
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import Text.Printf (printf)
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import Language.SystemVerilog.AST.ShowHelp (showPad, unlines')
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import Language.SystemVerilog.AST.Type (Type, Identifier)
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import Language.SystemVerilog.AST.Expr (Expr, Range, showRanges, showAssignment)
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data Decl
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= Parameter Type Identifier Expr
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| Localparam Type Identifier Expr
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| Variable Direction Type Identifier [Range] (Maybe Expr)
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deriving Eq
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instance Show Decl where
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showList l _ = unlines' $ map show l
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show (Parameter t x e) = printf "parameter %s%s = %s;" (showPad t) x (show e)
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show (Localparam t x e) = printf "localparam %s%s = %s;" (showPad t) x (show e)
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show (Variable d t x a me) = printf "%s%s %s%s%s;" (showPad d) (show t) x (showRanges a) (showAssignment me)
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data Direction
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= Input
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| Output
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| Inout
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| Local
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deriving Eq
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instance Show Direction where
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show Input = "input"
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show Output = "output"
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show Inout = "inout"
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show Local = ""
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@ -0,0 +1,31 @@
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
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-
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- SystemVerilog left-hand sides (aka lvals)
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-}
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module Language.SystemVerilog.AST.LHS
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( LHS (..)
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) where
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import Text.Printf (printf)
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import Language.SystemVerilog.AST.ShowHelp (commas)
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import Language.SystemVerilog.AST.Type (Identifier)
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import Language.SystemVerilog.AST.Expr (Expr, Range)
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data LHS
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= LHSIdent Identifier
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| LHSBit LHS Expr
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| LHSRange LHS Range
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| LHSDot LHS Identifier
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| LHSConcat [LHS]
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deriving Eq
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instance Show LHS where
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show (LHSIdent x ) = x
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show (LHSBit l e ) = printf "%s[%s]" (show l) (show e)
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show (LHSRange l (a, b)) = printf "%s[%s:%s]" (show l) (show a) (show b)
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show (LHSDot l x ) = printf "%s.%s" (show l) x
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show (LHSConcat lhss ) = printf "{%s}" (commas $ map show lhss)
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@ -12,9 +12,11 @@ module Language.SystemVerilog.AST.ShowHelp
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, unlines'
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, commas
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, indentedParenList
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, showCase
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) where
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import Data.List (intercalate)
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import Text.Printf (printf)
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showPad :: Show t => t -> String
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showPad x =
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@ -48,3 +50,5 @@ indentedParenList [] = "()"
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indentedParenList [x] = "(" ++ x ++ ")"
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indentedParenList l = "(\n" ++ (indent $ intercalate ",\n" l) ++ "\n)"
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showCase :: (Show x, Show y) => ([x], y) -> String
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showCase (a, b) = printf "%s: %s" (commas $ map show a) (show b)
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@ -0,0 +1,109 @@
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
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-
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- SystemVerilog procedural statements
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-}
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module Language.SystemVerilog.AST.Stmt
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( Stmt (..)
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, Timing (..)
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, Sense (..)
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, CaseKW (..)
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, Case
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) where
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import Text.Printf (printf)
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import Language.SystemVerilog.AST.ShowHelp (commas, indent, unlines', showPad, showCase)
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import Language.SystemVerilog.AST.Decl (Decl)
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import Language.SystemVerilog.AST.Expr (Expr)
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import Language.SystemVerilog.AST.LHS (LHS)
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import Language.SystemVerilog.AST.Op (AsgnOp)
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import Language.SystemVerilog.AST.Type (Identifier)
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data Stmt
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= Block (Maybe Identifier) [Decl] [Stmt]
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| Case Bool CaseKW Expr [Case] (Maybe Stmt)
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| For (Identifier, Expr) Expr (Identifier, Expr) Stmt
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| AsgnBlk AsgnOp LHS Expr
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| Asgn (Maybe Timing) LHS Expr
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| While Expr Stmt
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| RepeatL Expr Stmt
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| DoWhile Expr Stmt
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| Forever Stmt
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| If Expr Stmt Stmt
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| Timing Timing Stmt
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| Return Expr
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| Subroutine Identifier [Maybe Expr]
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| Null
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deriving Eq
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instance Show Stmt where
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show (Block name decls stmts) =
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printf "begin%s\n%s\n%s\nend" header (block decls) (block stmts)
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where
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header = maybe "" (" : " ++) name
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block :: Show t => [t] -> String
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block = indent . unlines' . map show
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show (Case u kw e cs def) =
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printf "%s%s (%s)\n%s%s\nendcase" uniqStr (show kw) (show e) bodyStr defStr
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where
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uniqStr = if u then "unique " else ""
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bodyStr = indent $ unlines' $ map showCase cs
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defStr = case def of
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Nothing -> ""
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Just c -> printf "\n\tdefault: %s" (show c)
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show (For (a,b) c (d,e) f) =
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printf "for (%s = %s; %s; %s = %s)\n%s" a (show b) (show c) d (show e) (indent $ show f)
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show (Subroutine x a) = printf "%s(%s);" x (commas $ map (maybe "" show) a)
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show (AsgnBlk o v e) = printf "%s %s %s;" (show v) (show o) (show e)
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show (Asgn t v e) = printf "%s <= %s%s;" (show v) (maybe "" showPad t) (show e)
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show (While e s) = printf "while (%s) %s" (show e) (show s)
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show (RepeatL e s) = printf "repeat (%s) %s" (show e) (show s)
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show (DoWhile e s) = printf "do %s while (%s);" (show s) (show e)
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show (Forever s ) = printf "forever %s" (show s)
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show (If a b Null) = printf "if (%s) %s" (show a) (show b)
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show (If a b c ) = printf "if (%s) %s\nelse %s" (show a) (show b) (show c)
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show (Return e ) = printf "return %s;" (show e)
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show (Timing t s ) = printf "%s%s" (show t) (show s)
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show (Null ) = ";"
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data CaseKW
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= CaseN
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| CaseZ
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| CaseX
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deriving Eq
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instance Show CaseKW where
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show CaseN = "case"
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show CaseZ = "casez"
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show CaseX = "casex"
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type Case = ([Expr], Stmt)
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data Timing
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= Event Sense
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| Delay Expr
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| Cycle Expr
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deriving Eq
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instance Show Timing where
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show (Event s) = printf "@(%s)" (show s)
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show (Delay e) = printf "#(%s)" (show e)
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show (Cycle e) = printf "##(%s)" (show e)
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data Sense
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= Sense LHS
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| SenseOr Sense Sense
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| SensePosedge LHS
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| SenseNegedge LHS
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| SenseStar
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deriving Eq
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instance Show Sense where
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show (Sense a ) = show a
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show (SenseOr a b) = printf "%s or %s" (show a) (show b)
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show (SensePosedge a ) = printf "posedge %s" (show a)
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show (SenseNegedge a ) = printf "negedge %s" (show a)
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show (SenseStar ) = "*"
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@ -33,9 +33,12 @@ executable sv2v
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-- SystemVerilog modules
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Language.SystemVerilog
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Language.SystemVerilog.AST
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Language.SystemVerilog.AST.Decl
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Language.SystemVerilog.AST.Expr
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Language.SystemVerilog.AST.LHS
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Language.SystemVerilog.AST.Op
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Language.SystemVerilog.AST.ShowHelp
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Language.SystemVerilog.AST.Stmt
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Language.SystemVerilog.AST.Type
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Language.SystemVerilog.Parser
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Language.SystemVerilog.Parser.Lex
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