added conversion to make functions and tasks use only one statement

src/Convert.hs

@@ -18,6 +18,7 @@ import qualified Convert.Logic
 import qualified Convert.PackedArray
 import qualified Convert.Return
 import qualified Convert.StarPort
+import qualified Convert.StmtBlock
 import qualified Convert.Struct
 import qualified Convert.Typedef
 import qualified Convert.UnbasedUnsized
@@ -33,6 +34,7 @@ phases excludes =
     , Convert.Enum.convert
     , Convert.PackedArray.convert
     , Convert.StarPort.convert
+    , Convert.StmtBlock.convert
     , Convert.Struct.convert
     , Convert.Return.convert
     , Convert.Typedef.convert

src/Convert/StmtBlock.hs

@@ -0,0 +1,30 @@
+{- sv2v
+ - Author: Zachary Snow <zach@zachjs.com>
+ -
+ - Conversion for tasks and functions to use only one statement, as required in
+ - Verilog-2005.
+ -}
+
+module Convert.StmtBlock (convert) where
+
+import Convert.Traverse
+import Language.SystemVerilog.AST
+
+convert :: AST -> AST
+convert = traverseDescriptions $ traverseModuleItems convertModuleItem
+
+convertModuleItem :: ModuleItem -> ModuleItem
+convertModuleItem (MIPackageItem packageItem) =
+    MIPackageItem $ convertPackageItem packageItem
+convertModuleItem other = other
+
+convertPackageItem :: PackageItem -> PackageItem
+convertPackageItem (Function ml t f decls stmts) =
+    Function ml t f decls [stmtsToStmt stmts]
+convertPackageItem (Task     ml   f decls stmts) =
+    Task     ml   f decls [stmtsToStmt stmts]
+convertPackageItem other = other
+
+stmtsToStmt :: [Stmt] -> Stmt
+stmtsToStmt [stmt] = stmt
+stmtsToStmt stmts = Block Nothing [] stmts

sv2v.cabal

@@ -58,6 +58,7 @@ executable sv2v
     Convert.PackedArray
     Convert.Return
     Convert.StarPort
+    Convert.StmtBlock
     Convert.Struct
     Convert.Typedef
     Convert.Traverse