mirror of https://github.com/zachjs/sv2v.git
final major round of splitting and cleanup in the SystemVerilog module
This commit is contained in:
Zachary Snow
parent
6d0f7dd0a7
commit
383754fa7a
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@ -1,9 +1,12 @@
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-- | A parser for SystemVerilog.
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{- sv2v
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- Author: Tom Hawkins <tomahawkins@gmail.com>
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-
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- A parser for SystemVerilog.
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-}
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module Language.SystemVerilog
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( module Language.SystemVerilog.AST
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, module Language.SystemVerilog.Parser
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) where
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( module Language.SystemVerilog.AST
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, module Language.SystemVerilog.Parser
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) where
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import Language.SystemVerilog.AST
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import Language.SystemVerilog.Parser
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@ -14,257 +14,28 @@
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-}
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module Language.SystemVerilog.AST
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( Description(..)
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, PackageItem(..)
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, ModuleItem (..)
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, Direction (..)
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, GenItem (..)
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, AlwaysKW (..)
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, CaseKW (..)
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, PartKW (..)
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, Lifetime (..)
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, NInputGateKW (..)
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, NOutputGateKW (..)
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, AST
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, PortBinding
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, ModportDecl
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, GenCase
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, simplify
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, rangeSize
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( AST
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, module Attr
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, module Decl
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, module Description
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, module Expr
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, module GenItem
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, module LHS
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, module ModuleItem
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, module Op
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, module Stmt
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, module Type
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) where
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import Data.List (intercalate)
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import Data.Maybe (maybe, fromJust, isJust)
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import Text.Printf (printf)
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import Text.Read (readMaybe)
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import Language.SystemVerilog.AST.Attr as Attr
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import Language.SystemVerilog.AST.Decl as Decl
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import Language.SystemVerilog.AST.Description as Description
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import Language.SystemVerilog.AST.Expr as Expr
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import Language.SystemVerilog.AST.GenItem as GenItem
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import Language.SystemVerilog.AST.LHS as LHS
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import Language.SystemVerilog.AST.ModuleItem as ModuleItem
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import Language.SystemVerilog.AST.Op as Op
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import Language.SystemVerilog.AST.Stmt as Stmt
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import Language.SystemVerilog.AST.Type as Type
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import Language.SystemVerilog.AST.ShowHelp
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-- Note: Verilog allows modules to be declared with either a simple list of
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-- ports _identifiers_, or a list of port _declarations_. If only the
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-- identifiers are used, they must be declared with a type and direction
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-- (potentially separately!) within the module itself.
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type AST = [Description]
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data PackageItem
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= Typedef Type Identifier
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| Function (Maybe Lifetime) Type Identifier [Decl] [Stmt]
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| Task (Maybe Lifetime) Identifier [Decl] [Stmt]
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| Comment String
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deriving Eq
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instance Show PackageItem where
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show (Typedef t x) = printf "typedef %s %s;" (show t) x
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show (Function ml t x i b) =
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printf "function %s%s%s;\n%s\n%s\nendfunction"
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(showLifetime ml) (showPad t) x (indent $ show i)
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(indent $ unlines' $ map show b)
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show (Task ml x i b) =
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printf "task %s%s;\n%s\n%s\nendtask"
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(showLifetime ml) x (indent $ show i)
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(indent $ unlines' $ map show b)
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show (Comment c) = "// " ++ c
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data Description
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= Part Bool PartKW (Maybe Lifetime) Identifier [Identifier] [ModuleItem]
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| PackageItem PackageItem
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| Directive String
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deriving Eq
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instance Show Description where
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showList descriptions _ = intercalate "\n" $ map show descriptions
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show (Part True kw lifetime name _ items) =
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printf "extern %s %s%s %s;"
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(show kw) (showLifetime lifetime) name (indentedParenList itemStrs)
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where itemStrs = map (\(MIDecl a) -> init $ show a) items
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show (Part False kw lifetime name ports items) =
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printf "%s %s%s%s;\n%s\nend%s"
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(show kw) (showLifetime lifetime) name portsStr bodyStr (show kw)
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where
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portsStr =
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if null ports
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then ""
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else " " ++ indentedParenList ports
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bodyStr = indent $ unlines' $ map show items
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show (PackageItem i) = show i
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show (Directive str) = str
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data PartKW
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= Module
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| Interface
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deriving Eq
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instance Show PartKW where
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show Module = "module"
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show Interface = "interface"
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data ModuleItem
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= MIAttr Attr ModuleItem
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| MIDecl Decl
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| AlwaysC AlwaysKW Stmt
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| Assign (Maybe Expr) LHS Expr
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| Defparam LHS Expr
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| Instance Identifier [PortBinding] Identifier (Maybe Range) [PortBinding]
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| Genvar Identifier
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| Generate [GenItem]
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| Modport Identifier [ModportDecl]
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| Initial Stmt
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| MIPackageItem PackageItem
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| NInputGate NInputGateKW (Maybe Identifier) LHS [Expr]
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| NOutputGate NOutputGateKW (Maybe Identifier) [LHS] Expr
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| AssertionItem AssertionItem
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deriving Eq
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data AlwaysKW
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= Always
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| AlwaysComb
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| AlwaysFF
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| AlwaysLatch
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deriving Eq
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instance Show AlwaysKW where
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show Always = "always"
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show AlwaysComb = "always_comb"
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show AlwaysFF = "always_ff"
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show AlwaysLatch = "always_latch"
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type PortBinding = (Identifier, Maybe Expr)
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type ModportDecl = (Direction, Identifier, Maybe Expr)
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instance Show ModuleItem where
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show thing = case thing of
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MIAttr attr mi -> printf "%s %s" (show attr) (show mi)
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MIDecl nest -> show nest
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AlwaysC k b -> printf "%s %s" (show k) (show b)
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Assign d a b -> printf "assign %s%s = %s;" delayStr (show a) (show b)
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where delayStr = maybe "" (\e -> "#(" ++ show e ++ ") ") d
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Defparam a b -> printf "defparam %s = %s;" (show a) (show b)
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Instance m params i r ports
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| null params -> printf "%s %s%s%s;" m i rStr (showPorts ports)
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| otherwise -> printf "%s #%s %s%s%s;" m (showPorts params) i rStr (showPorts ports)
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where rStr = maybe "" (\a -> showRanges [a] ++ " ") r
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Genvar x -> printf "genvar %s;" x
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Generate b -> printf "generate\n%s\nendgenerate" (indent $ unlines' $ map show b)
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Modport x l -> printf "modport %s(\n%s\n);" x (indent $ intercalate ",\n" $ map showModportDecl l)
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Initial s -> printf "initial %s" (show s)
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MIPackageItem i -> show i
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NInputGate kw x lhs exprs -> printf "%s%s (%s, %s);" (show kw) (maybe "" (" " ++) x) (show lhs) (commas $ map show exprs)
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NOutputGate kw x lhss expr -> printf "%s%s (%s, %s);" (show kw) (maybe "" (" " ++) x) (commas $ map show lhss) (show expr)
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AssertionItem (Nothing, a) -> show a
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AssertionItem (Just x, a) -> printf "%s : %s" x (show a)
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where
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showPorts :: [PortBinding] -> String
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showPorts ports = indentedParenList $ map showPort ports
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showPort :: PortBinding -> String
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showPort ("*", Nothing) = ".*"
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showPort (i, arg) =
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if i == ""
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then show (fromJust arg)
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else printf ".%s(%s)" i (if isJust arg then show $ fromJust arg else "")
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showModportDecl :: ModportDecl -> String
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showModportDecl (dir, ident, me) =
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if me == Just (Ident ident)
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then printf "%s %s" (show dir) ident
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else printf "%s .%s(%s)" (show dir) ident (maybe "" show me)
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data NInputGateKW
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= GateAnd
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| GateNand
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| GateOr
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| GateNor
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| GateXor
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| GateXnor
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deriving Eq
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data NOutputGateKW
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= GateBuf
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| GateNot
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deriving Eq
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instance Show NInputGateKW where
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show GateAnd = "and"
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show GateNand = "nand"
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show GateOr = "or"
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show GateNor = "nor"
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show GateXor = "xor"
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show GateXnor = "xnor"
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instance Show NOutputGateKW where
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show GateBuf = "buf"
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show GateNot = "not"
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type GenCase = ([Expr], GenItem)
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data GenItem
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= GenBlock (Maybe Identifier) [GenItem]
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| GenCase Expr [GenCase] (Maybe GenItem)
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| GenFor (Identifier, Expr) Expr (Identifier, AsgnOp, Expr) (Maybe Identifier) [GenItem]
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| GenIf Expr GenItem GenItem
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| GenNull
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| GenModuleItem ModuleItem
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deriving Eq
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instance Show GenItem where
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showList i _ = unlines' $ map show i
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show (GenBlock Nothing i) = printf "begin\n%s\nend" (indent $ unlines' $ map show i)
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show (GenBlock (Just x) i) = printf "begin : %s\n%s\nend" x (indent $ unlines' $ map show i)
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show (GenCase e c Nothing ) = printf "case (%s)\n%s\nendcase" (show e) (indent $ unlines' $ map showCase c)
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show (GenCase e c (Just d)) = printf "case (%s)\n%s\n\tdefault:\n%s\nendcase" (show e) (indent $ unlines' $ map showCase c) (indent $ indent $ show d)
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show (GenIf e a GenNull) = printf "if (%s) %s" (show e) (show a)
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show (GenIf e a b ) = printf "if (%s) %s\nelse %s" (show e) (show a) (show b)
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show (GenFor (x1, e1) c (x2, o2, e2) mx is) = printf "for (%s = %s; %s; %s %s %s) %s" x1 (show e1) (show c) x2 (show o2) (show e2) (show $ GenBlock mx is)
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show GenNull = ";"
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show (GenModuleItem item) = show item
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data Lifetime
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= Static
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| Automatic
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deriving (Eq, Ord)
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instance Show Lifetime where
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show Static = "static"
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show Automatic = "automatic"
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showLifetime :: Maybe Lifetime -> String
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showLifetime Nothing = ""
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showLifetime (Just l) = show l ++ " "
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-- basic expression simplfication utility to help us generate nicer code in the
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-- common case of ranges like `[FOO-1:0]`
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simplify :: Expr -> Expr
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simplify (BinOp op e1 e2) =
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case (op, e1', e2') of
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(Add, Number "0", e) -> e
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(Add, e, Number "0") -> e
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(Sub, e, Number "0") -> e
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(Add, BinOp Sub e (Number "1"), Number "1") -> e
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(Add, e, BinOp Sub (Number "0") (Number "1")) -> BinOp Sub e (Number "1")
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(_ , Number a, Number b) ->
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case (op, readMaybe a :: Maybe Int, readMaybe b :: Maybe Int) of
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(Add, Just x, Just y) -> Number $ show (x + y)
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(Sub, Just x, Just y) -> Number $ show (x - y)
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(Mul, Just x, Just y) -> Number $ show (x * y)
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_ -> BinOp op e1' e2'
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_ -> BinOp op e1' e2'
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where
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e1' = simplify e1
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e2' = simplify e2
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simplify other = other
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rangeSize :: Range -> Expr
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rangeSize (s, e) =
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simplify $ BinOp Add (BinOp Sub s e) (Number "1")
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@ -0,0 +1,90 @@
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
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-
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- SystemVerilog top-level items (descriptions, package items)
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-}
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module Language.SystemVerilog.AST.Description
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( Description (..)
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, PackageItem (..)
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, PartKW (..)
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, Lifetime (..)
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) where
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import Data.List (intercalate)
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import Text.Printf (printf)
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import Language.SystemVerilog.AST.ShowHelp
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import Language.SystemVerilog.AST.Decl (Decl)
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import Language.SystemVerilog.AST.Stmt (Stmt)
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import Language.SystemVerilog.AST.Type (Type, Identifier)
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import {-# SOURCE #-} Language.SystemVerilog.AST.ModuleItem (ModuleItem)
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data Description
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= Part Bool PartKW (Maybe Lifetime) Identifier [Identifier] [ModuleItem]
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| PackageItem PackageItem
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| Directive String -- currently unused
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deriving Eq
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instance Show Description where
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showList descriptions _ = intercalate "\n" $ map show descriptions
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show (Part True kw lifetime name _ items) =
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printf "extern %s %s%s %s;"
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(show kw) (showLifetime lifetime) name (indentedParenList itemStrs)
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where itemStrs = map (init . show) items
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show (Part False kw lifetime name ports items) =
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printf "%s %s%s%s;\n%s\nend%s"
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(show kw) (showLifetime lifetime) name portsStr bodyStr (show kw)
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where
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portsStr = if null ports
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then ""
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else " " ++ indentedParenList ports
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bodyStr = indent $ unlines' $ map show items
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show (PackageItem i) = show i
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show (Directive str) = str
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data PackageItem
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= Typedef Type Identifier
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| Function (Maybe Lifetime) Type Identifier [Decl] [Stmt]
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| Task (Maybe Lifetime) Identifier [Decl] [Stmt]
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| Comment String
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deriving Eq
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instance Show PackageItem where
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show (Typedef t x) = printf "typedef %s %s;" (show t) x
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show (Function ml t x i b) =
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printf "function %s%s%s;\n%s\n%s\nendfunction"
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(showLifetime ml) (showPad t) x (indent $ show i)
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(indent $ unlines' $ map show b)
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show (Task ml x i b) =
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printf "task %s%s;\n%s\n%s\nendtask"
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(showLifetime ml) x (indent $ show i)
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(indent $ unlines' $ map show b)
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show (Comment c) =
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if elem '\n' c
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then "// " ++ show c
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else "// " ++ c
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data PartKW
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= Module
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| Interface
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deriving Eq
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instance Show PartKW where
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show Module = "module"
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show Interface = "interface"
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data Lifetime
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= Static
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| Automatic
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deriving (Eq, Ord)
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instance Show Lifetime where
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show Static = "static"
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show Automatic = "automatic"
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showLifetime :: Maybe Lifetime -> String
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showLifetime Nothing = ""
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showLifetime (Just l) = show l ++ " "
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@ -8,13 +8,16 @@
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module Language.SystemVerilog.AST.Expr
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( Expr (..)
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, Range
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, Args (..)
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, showAssignment
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, showRanges
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, Args (..)
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, simplify
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, rangeSize
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) where
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import Data.List (intercalate)
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import Text.Printf (printf)
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import Text.Read (readMaybe)
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import Language.SystemVerilog.AST.Op
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import Language.SystemVerilog.AST.ShowHelp
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@ -83,3 +86,29 @@ showRanges l = " " ++ (concatMap showRange l)
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showRange :: Range -> String
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showRange (h, l) = printf "[%s:%s]" (show h) (show l)
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-- basic expression simplfication utility to help us generate nicer code in the
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-- common case of ranges like `[FOO-1:0]`
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simplify :: Expr -> Expr
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simplify (BinOp op e1 e2) =
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case (op, e1', e2') of
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(Add, Number "0", e) -> e
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(Add, e, Number "0") -> e
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(Sub, e, Number "0") -> e
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(Add, BinOp Sub e (Number "1"), Number "1") -> e
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(Add, e, BinOp Sub (Number "0") (Number "1")) -> BinOp Sub e (Number "1")
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(_ , Number a, Number b) ->
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case (op, readMaybe a :: Maybe Int, readMaybe b :: Maybe Int) of
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(Add, Just x, Just y) -> Number $ show (x + y)
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(Sub, Just x, Just y) -> Number $ show (x - y)
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(Mul, Just x, Just y) -> Number $ show (x * y)
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_ -> BinOp op e1' e2'
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_ -> BinOp op e1' e2'
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where
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e1' = simplify e1
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e2' = simplify e2
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simplify other = other
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rangeSize :: Range -> Expr
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rangeSize (s, e) =
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simplify $ BinOp Add (BinOp Sub s e) (Number "1")
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|
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@ -0,0 +1,52 @@
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
|
||||
- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
|
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-
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- SystemVerilog `generate` items
|
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-}
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module Language.SystemVerilog.AST.GenItem
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( GenItem (..)
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, GenCase
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) where
|
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|
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import Text.Printf (printf)
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import Language.SystemVerilog.AST.ShowHelp
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import Language.SystemVerilog.AST.Expr (Expr)
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import Language.SystemVerilog.AST.Op (AsgnOp)
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import Language.SystemVerilog.AST.Type (Identifier)
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import {-# SOURCE #-} Language.SystemVerilog.AST.ModuleItem (ModuleItem)
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data GenItem
|
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= GenBlock (Maybe Identifier) [GenItem]
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| GenCase Expr [GenCase] (Maybe GenItem)
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| GenFor (Identifier, Expr) Expr (Identifier, AsgnOp, Expr) (Maybe Identifier) [GenItem]
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| GenIf Expr GenItem GenItem
|
||||
| GenNull
|
||||
| GenModuleItem ModuleItem
|
||||
deriving Eq
|
||||
|
||||
instance Show GenItem where
|
||||
showList i _ = unlines' $ map show i
|
||||
show (GenBlock mx i) =
|
||||
printf "begin%s\n%s\nend"
|
||||
(maybe "" (" : " ++) mx)
|
||||
(indent $ unlines' $ map show i)
|
||||
show (GenCase e c md) =
|
||||
printf "case (%s)\n%s%s\nendcase" (show e)
|
||||
(indent $ unlines' $ map showCase c)
|
||||
(maybe "" (indent . indent . show) md)
|
||||
show (GenIf e a GenNull) = printf "if (%s) %s" (show e) (show a)
|
||||
show (GenIf e a b ) = printf "if (%s) %s\nelse %s" (show e) (show a) (show b)
|
||||
show (GenFor (x1, e1) c (x2, o2, e2) mx is) =
|
||||
printf "for (%s = %s; %s; %s %s %s) %s"
|
||||
x1 (show e1)
|
||||
(show c)
|
||||
x2 (show o2) (show e2)
|
||||
(show $ GenBlock mx is)
|
||||
show (GenNull) = ";"
|
||||
show (GenModuleItem item) = show item
|
||||
|
||||
type GenCase = ([Expr], GenItem)
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
{- sv2v
|
||||
- Author: Zachary Snow <zach@zachjs.com>
|
||||
- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
|
||||
-
|
||||
- SystemVerilog `module` items
|
||||
-}
|
||||
|
||||
module Language.SystemVerilog.AST.ModuleItem
|
||||
( ModuleItem (..)
|
||||
, PortBinding
|
||||
, ModportDecl
|
||||
, AlwaysKW (..)
|
||||
, NInputGateKW (..)
|
||||
, NOutputGateKW (..)
|
||||
) where
|
||||
|
||||
import Data.List (intercalate)
|
||||
import Data.Maybe (maybe, fromJust, isJust)
|
||||
import Text.Printf (printf)
|
||||
|
||||
import Language.SystemVerilog.AST.ShowHelp
|
||||
|
||||
import Language.SystemVerilog.AST.Attr (Attr)
|
||||
import Language.SystemVerilog.AST.Decl (Decl, Direction)
|
||||
import Language.SystemVerilog.AST.Description (PackageItem)
|
||||
import Language.SystemVerilog.AST.Expr (Expr(Ident), Range, showRanges)
|
||||
import Language.SystemVerilog.AST.GenItem (GenItem)
|
||||
import Language.SystemVerilog.AST.LHS (LHS)
|
||||
import Language.SystemVerilog.AST.Stmt (Stmt, AssertionItem)
|
||||
import Language.SystemVerilog.AST.Type (Identifier)
|
||||
|
||||
data ModuleItem
|
||||
= MIAttr Attr ModuleItem
|
||||
| MIDecl Decl
|
||||
| AlwaysC AlwaysKW Stmt
|
||||
| Assign (Maybe Expr) LHS Expr
|
||||
| Defparam LHS Expr
|
||||
| Instance Identifier [PortBinding] Identifier (Maybe Range) [PortBinding]
|
||||
| Genvar Identifier
|
||||
| Generate [GenItem]
|
||||
| Modport Identifier [ModportDecl]
|
||||
| Initial Stmt
|
||||
| MIPackageItem PackageItem
|
||||
| NInputGate NInputGateKW (Maybe Identifier) LHS [Expr]
|
||||
| NOutputGate NOutputGateKW (Maybe Identifier) [LHS] Expr
|
||||
| AssertionItem AssertionItem
|
||||
deriving Eq
|
||||
|
||||
instance Show ModuleItem where
|
||||
show (MIDecl nest) = show nest
|
||||
show (MIPackageItem i) = show i
|
||||
show (MIAttr attr mi ) = printf "%s %s" (show attr) (show mi)
|
||||
show (AlwaysC k b) = printf "%s %s" (show k) (show b)
|
||||
show (Defparam a b) = printf "defparam %s = %s;" (show a) (show b)
|
||||
show (Genvar x ) = printf "genvar %s;" x
|
||||
show (Generate b ) = printf "generate\n%s\nendgenerate" (indent $ unlines' $ map show b)
|
||||
show (Modport x l) = printf "modport %s(\n%s\n);" x (indent $ intercalate ",\n" $ map showModportDecl l)
|
||||
show (Initial s ) = printf "initial %s" (show s)
|
||||
show (NInputGate kw x lhs exprs) = printf "%s%s (%s, %s);" (show kw) (maybe "" (" " ++) x) (show lhs) (commas $ map show exprs)
|
||||
show (NOutputGate kw x lhss expr) = printf "%s%s (%s, %s);" (show kw) (maybe "" (" " ++) x) (commas $ map show lhss) (show expr)
|
||||
show (Assign d a b) =
|
||||
printf "assign %s%s = %s;" delayStr (show a) (show b)
|
||||
where delayStr = maybe "" (\e -> "#(" ++ show e ++ ") ") d
|
||||
show (AssertionItem (mx, a)) =
|
||||
if mx == Nothing
|
||||
then show a
|
||||
else printf "%s : %s" (fromJust mx) (show a)
|
||||
show (Instance m params i r ports) =
|
||||
if null params
|
||||
then printf "%s %s%s%s;" m i rStr (showPorts ports)
|
||||
else printf "%s #%s %s%s%s;" m (showPorts params) i rStr (showPorts ports)
|
||||
where rStr = maybe "" (\a -> showRanges [a] ++ " ") r
|
||||
|
||||
showPorts :: [PortBinding] -> String
|
||||
showPorts ports = indentedParenList $ map showPort ports
|
||||
|
||||
showPort :: PortBinding -> String
|
||||
showPort ("*", Nothing) = ".*"
|
||||
showPort (i, arg) =
|
||||
if i == ""
|
||||
then show (fromJust arg)
|
||||
else printf ".%s(%s)" i (if isJust arg then show $ fromJust arg else "")
|
||||
|
||||
showModportDecl :: ModportDecl -> String
|
||||
showModportDecl (dir, ident, me) =
|
||||
if me == Just (Ident ident)
|
||||
then printf "%s %s" (show dir) ident
|
||||
else printf "%s .%s(%s)" (show dir) ident (maybe "" show me)
|
||||
|
||||
type PortBinding = (Identifier, Maybe Expr)
|
||||
|
||||
type ModportDecl = (Direction, Identifier, Maybe Expr)
|
||||
|
||||
data AlwaysKW
|
||||
= Always
|
||||
| AlwaysComb
|
||||
| AlwaysFF
|
||||
| AlwaysLatch
|
||||
deriving Eq
|
||||
|
||||
instance Show AlwaysKW where
|
||||
show Always = "always"
|
||||
show AlwaysComb = "always_comb"
|
||||
show AlwaysFF = "always_ff"
|
||||
show AlwaysLatch = "always_latch"
|
||||
|
||||
data NInputGateKW
|
||||
= GateAnd
|
||||
| GateNand
|
||||
| GateOr
|
||||
| GateNor
|
||||
| GateXor
|
||||
| GateXnor
|
||||
deriving Eq
|
||||
|
||||
instance Show NInputGateKW where
|
||||
show GateAnd = "and"
|
||||
show GateNand = "nand"
|
||||
show GateOr = "or"
|
||||
show GateNor = "nor"
|
||||
show GateXor = "xor"
|
||||
show GateXnor = "xnor"
|
||||
|
||||
data NOutputGateKW
|
||||
= GateBuf
|
||||
| GateNot
|
||||
deriving Eq
|
||||
|
||||
instance Show NOutputGateKW where
|
||||
show GateBuf = "buf"
|
||||
show GateNot = "not"
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
module Language.SystemVerilog.AST.ModuleItem
|
||||
( ModuleItem
|
||||
) where
|
||||
|
||||
data ModuleItem
|
||||
instance Eq ModuleItem
|
||||
instance Show ModuleItem
|
||||
|
|
@ -2,15 +2,15 @@
|
|||
- Author: Zachary Snow <zach@zachjs.com>
|
||||
-}
|
||||
module Language.SystemVerilog.Parser
|
||||
( parseFile
|
||||
) where
|
||||
( parseFile
|
||||
) where
|
||||
|
||||
import Language.SystemVerilog.AST
|
||||
import Language.SystemVerilog.Parser.Lex
|
||||
import Language.SystemVerilog.Parser.Parse
|
||||
import Language.SystemVerilog.AST (AST)
|
||||
import Language.SystemVerilog.Parser.Lex (lexFile)
|
||||
import Language.SystemVerilog.Parser.Parse (parse)
|
||||
|
||||
-- parses a file given a table of predefined macros and the file name
|
||||
-- parses a file given include search paths, a table of predefined macros, and
|
||||
-- the file path
|
||||
parseFile :: [String] -> [(String, String)] -> FilePath -> IO AST
|
||||
parseFile includePaths env file =
|
||||
lexFile includePaths env file >>=
|
||||
return . descriptions
|
||||
parseFile includePaths defines path =
|
||||
lexFile includePaths defines path >>= return . parse
|
||||
|
|
|
|||
|
|
@ -5,19 +5,20 @@
|
|||
- This file has been *heavily* modified and extended from the original version
|
||||
- in tomahawkins/verilog. I have added support for numerous SystemVerilog
|
||||
- constructs, which has necessitated rewriting nearly all of this.
|
||||
-
|
||||
- This file is the only remaining one that still uses 2-space indentation. I've
|
||||
- decided to leave it this way because I think it is too important to preserve
|
||||
- the ability to easily blame/diff this file.
|
||||
-}
|
||||
{
|
||||
module Language.SystemVerilog.Parser.Parse (descriptions) where
|
||||
|
||||
import Data.List
|
||||
import Data.Maybe
|
||||
module Language.SystemVerilog.Parser.Parse (parse) where
|
||||
|
||||
import Language.SystemVerilog.AST
|
||||
import Language.SystemVerilog.Parser.ParseDecl
|
||||
import Language.SystemVerilog.Parser.Tokens
|
||||
}
|
||||
|
||||
%name descriptions
|
||||
%name parse
|
||||
%tokentype { Token }
|
||||
%error { parseError }
|
||||
|
||||
|
|
|
|||
|
|
@ -36,8 +36,11 @@ executable sv2v
|
|||
Language.SystemVerilog.AST
|
||||
Language.SystemVerilog.AST.Attr
|
||||
Language.SystemVerilog.AST.Decl
|
||||
Language.SystemVerilog.AST.Description
|
||||
Language.SystemVerilog.AST.Expr
|
||||
Language.SystemVerilog.AST.GenItem
|
||||
Language.SystemVerilog.AST.LHS
|
||||
Language.SystemVerilog.AST.ModuleItem
|
||||
Language.SystemVerilog.AST.Op
|
||||
Language.SystemVerilog.AST.ShowHelp
|
||||
Language.SystemVerilog.AST.Stmt
|
||||
|
|
|
|||
Loading…
Reference in New Issue