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prjxray
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236 Commits

Author SHA1 Message Date
Jake Mercer c05b4b0406 MAKE - Format Trailing Whitespace 
Add `make format-trailing-ws`.  This recipe finds all _files_ (not
links) known to Git and uses `sed` to remove trailing whitespace.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-10-26 10:04:52 +01:00
litghost c94cb0224c
Revert "Whitespace" 2019-10-23 14:22:17 -07:00
Jake Mercer bf11f43390 FORMAT - Run `make format` 
Changes after running `make format`.  Future commits which add
whitespace should be caught by CI at the PR stage.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-10-22 19:35:24 +01:00
Leonardo Romor c138c156ed
Applied requested changes to use XRAY_UTILS_DIR 
Signed-off-by: Leonardo Romor <leonardo.romor@gmail.com>
 2019-10-10 19:50:02 +02:00
Leonardo Romor 48755a1128
Updated wrong string path added in syspath before import 
Signed-off-by: Leonardo Romor <leonardo.romor@gmail.com>
 2019-10-10 19:20:32 +02:00
Tim Ansell ecfd250a28
Merge pull request #1068 from antmicro/litex_readme 
Updated README.md for LiteX minitest
 2019-09-30 10:08:47 +02:00
litghost 22750bc2ce
Merge pull request #1058 from antmicro/pll_minitest 
Minitest for PLLE2_ADV
 2019-09-26 10:06:53 -07:00
Maciej Kurc dd26790d65 Updated README.md, added different phase settings to the PLL. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-26 09:47:58 +02:00
Tim Ansell d78b50af8b
Merge pull request #1040 from antmicro/fix-sphinx-xref-links 
Fixing documentation cross-reference links
 2019-09-25 10:29:07 -07:00
Maciej Kurc 1f31c98265 Updated README.md 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-25 12:13:11 +02:00
Alessandro Comodi 2fab112c71 docs: fixed some READMEs and removed empty .md file generation 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-09-25 09:54:28 +02:00
Maciej Kurc 32feed6640 Removed BUFR and BUFMR, clock division implemented on logic. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-24 10:45:09 +02:00
Maciej Kurc 31ba200080 Minitest for PLLE2_ADV. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-20 11:20:30 +02:00
Maciej Kurc 2b3ca04914 Removed the need for physical pin loopback. The design now transmitts and receives using the same pins. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-12 15:08:05 +02:00
Maciej Kurc e722712661 Formatting 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-12 14:35:37 +02:00
Maciej Kurc 0ebe592dca Updated docs. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-12 14:35:37 +02:00
Maciej Kurc b878a2e651 A minitest for ISERDES in NETWORKING SDR/DDR modes. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-12 14:35:37 +02:00
litghost 6d21194b56
Merge pull request #1047 from antmicro/oserdes_minitest 
OSERDES minitest
 2019-09-11 09:13:48 -07:00
Maciej Kurc b31345010c OSERDES minitest without the need for hardware loopbacks. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-11 13:34:07 +02:00
Maciej Kurc 2f143b18b8 Code polish 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-03 16:36:07 +02:00
Maciej Kurc baf288ad24 A minitest for ISERDES+IDELAY 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-09-03 16:23:45 +02:00
Keith Rothman 6c4e6aa718 Update HCLK_IOI offset to match tilegrid 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-26 17:18:48 -07:00
Keith Rothman 2c7b64ea22 Create script for generating remaining bit report. 
This report is fairly fragile, but works well enough for the remaining
LiteX bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-26 15:04:29 -07:00
Keith Rothman fa2f61f914 Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 17:21:26 -07:00
Keith Rothman a7ba547acb Filter out non-IOB bits. 
Also add output from LiteX to verify IOB FASM features.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 13:38:03 -07:00
Keith Rothman 3345f30817 Fix D9/B8 in arty-swbut harness. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-10 17:15:18 -07:00
litghost 559f840097
Merge pull request #916 from antmicro/srl_minitests 
Minitests for SRLs
 2019-07-09 09:10:36 -07:00
Maciej Kurc 5c60639442 Added generation of sorted and "uniqued" FASM output 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-05 12:03:30 +02:00
Maciej Kurc cbbf46112f Updated EDIF write to include cell attributes 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-02 16:03:02 +02:00
Maciej Kurc 4d6f75e8ad Added packing tests for SRL32+LUT6 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-28 10:53:27 +02:00
Maciej Kurc 98bcd3f447 Added full vivado flow to the Makefile 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-28 10:53:22 +02:00
Maciej Kurc 4c2b0a5395 Added minitests for SRLs 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-27 15:13:18 +02:00
Keith Rothman e697365c7d Add ROI base file that adds a clock divider. 
This cannot be used for an ROI harness until
https://github.com/SymbiFlow/prjxray/issues/891 is complete.

Command to build new harness
```
XRAY_ROIV=../roi_base_div2.v make
```

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-25 12:05:44 -07:00
Maciej Kurc 68c810ce3b Added source files dependencies to Makefiles 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-25 10:14:20 +02:00
Maciej Kurc 64a05b4fa2 Changed makefiles to use XRAY_DIR 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-19 09:19:28 +02:00
Maciej Kurc bf1c7d3183 Fixed invication of prjxray scripts in Makefiles 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 13:00:23 +02:00
Maciej Kurc 728a6a76d2 Added bitread and segprint to the Makefile flow 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-17 14:52:06 +02:00
Maciej Kurc 3783e7b2e3 Fixed the LiteX generated SoC to be Linux capable 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-17 13:45:11 +02:00
Maciej Kurc 4798c08ad8 Changed Vivado invocation 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-14 09:40:21 +02:00
Maciej Kurc 4f459cfde3 Ran format-tcl 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 16:39:49 +02:00
Maciej Kurc 421af109b1 Added bit2fasm targets to Makefiles 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 16:29:20 +02:00
Maciej Kurc 0c244f242d Added submodule with Yosys and integrated it with the LiteX minitest 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 16:16:11 +02:00
Maciej Kurc 01f77fd2b2 Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 15:58:06 +02:00
Keith Rothman 259894f81d Add README for timing minitest. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-05-29 15:05:18 -07:00
Keith Rothman 992280f3b1 Add timing model minitest. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-05-29 14:55:04 -07:00
Keith Rothman 36177e9599 Add make targets to build additional outputs from each database. 
These targets are for:
 - Generating additional database outputs that are part, e.g. yaml files.
 - Generating harnesses

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-10 11:55:39 -07:00
Tim 'mithro' Ansell 5c61326d8b minitest/roi_harness: Move comments around to improve formatting. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-03-26 19:08:49 -07:00
Tim 'mithro' Ansell a3a5ffd45b minitests/roi_harness: Updating README. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-03-26 18:29:07 -07:00
Tim 'mithro' Ansell a8ff30b32f minitest/roi_harness: Strip trailing spaces 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-03-26 18:29:07 -07:00
Tim 'mithro' Ansell 9fc2649e86 minitest/roi_harness: Fixing comment indenting. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-03-26 18:29:07 -07:00