luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
2,389 Commits 31 Branches 4 Tags 7.7 MiB
Commit Graph

2389 Commits

Author SHA1 Message Date
litghost 36af12c149
Merge pull request #933 from antmicro/016-doutmux-amc31 
Fuzzer for DOUTMUX.MC31 and DFFMUX.MC31
 2019-07-10 15:47:33 -07:00
litghost 2d13b11f13
Merge pull request #935 from litghost/more_ilogic_bits 
Expand ILOGIC fuzzer to document additional ISERDES bits.
 2019-07-10 11:21:08 -07:00
Maciej Kurc b7fc6734d2 Ran format-py 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:15:28 +02:00
Maciej Kurc 1e6b85b8a8 Increased number of specimens and CLBs 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:07:11 +02:00
Maciej Kurc e08ce61fbe Modified 015 to include DFFMUX.MC31 for SLICEM 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:06:07 +02:00
Maciej Kurc 56cb76e90f Added a makefile which allows to fuzz features for both SLICEM and SLICEL but separate them during database merge. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 15:06:58 +02:00
litghost 05ef773e60
Merge pull request #938 from antmicro/mmcme2-base-addr-fix 
fuzzers: tilegrid: mmcme: LOC mmcme2_adv instances
 2019-07-09 21:14:29 -07:00
litghost f400565f71
Merge pull request #926 from litghost/add_pll_interconnect_fuzzer 
Add PLL fuzzer
 2019-07-09 13:56:32 -07:00
Karol Gugala b989c2fc05 fuzzers: tilegrid: mmcme: LOC mmcme2_adv instances 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-09 18:42:04 +02:00
litghost 559f840097
Merge pull request #916 from antmicro/srl_minitests 
Minitests for SRLs
 2019-07-09 09:10:36 -07:00
Keith Rothman 280191ce0e Attempt to fix fuzzer error. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-08 17:16:45 -07:00
Keith Rothman 2a242bbd62 Expand ILOGIC fuzzer to document additional ISERDES bits. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-08 17:00:06 -07:00
Keith Rothman 444f214561 Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-08 11:23:33 -07:00
Keith Rothman f92fb52576 Merge branch 'master' into add_pll_interconnect_fuzzer 2019-07-08 11:22:49 -07:00
Keith Rothman 3d1fade706 Change error output to stderr. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-08 11:21:43 -07:00
Maciej Kurc 67dba10fb7 Modified fuzzer 016 to include DOUTMUX.AMC31 feature. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-08 15:39:06 +02:00
Maciej Kurc 5c60639442 Added generation of sorted and "uniqued" FASM output 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-05 12:03:30 +02:00
Tomasz Michalak 948a3b21cc
Merge pull request #915 from antmicro/913_hclk_ioi_baseaddress 
Calculate base addresses for HCLK_IOI3 tiles.
 2019-07-04 23:32:20 +02:00
Keith Rothman b77c47b155 Fixes for zynq7 and PLL fuzzing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:19:03 -07:00
Keith Rothman a7f5a305b9 Add 034 to fuzzer makefile. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:19:03 -07:00
Keith Rothman 2728b781d1 Limit pips to the ones we care about. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:19:03 -07:00
Keith Rothman 30648d554a Complete initial PLL fuzzer. 
This solves for all unknown bits, but results in a large "IN_USE"
feature for apparently constant bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:18:58 -07:00
Keith Rothman bc822f8337 Update 032 with some fixes found during interconnect fuzzing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:18:58 -07:00
Keith Rothman 68ad409d23 Refactor PLL segbits to leverage known register file. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:18:53 -07:00
Karol Gugala 219f0f0175
Merge pull request #899 from antmicro/routing-bels 
Fuzzers: 007-timing: add routing BELs fuzzer
 2019-07-03 05:36:28 +02:00
Karol Gugala 78346781ce fuzzers: 007: fix Makefile targets definitions 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-02 19:04:10 +02:00
Maciej Kurc cbbf46112f Updated EDIF write to include cell attributes 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-02 16:03:02 +02:00
Karol Gugala 28d961a650 fuzzers: routing BELs: group timings by interconn oputput 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-02 13:08:14 +02:00
Tomasz Michalak e096d9c172 005-tilegrid: Add HCLK_IOI base addresses calculation 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-01 08:58:45 +02:00
Karol Gugala fac9212751 third-party: bump python-sdf-timing submodule 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala 6cc614f1fb fuzzers: 007: fix BEL fuzzer Makefile 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala 9658653da8 fuzzers: bel: emit routing bels timings as INTERCONN 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala eaa8e50fe1 utils: sdfmerge: use ns timescale 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala 03252bc46f fuzzers: 007: add gitignores 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala a99e26bbd4 fuzzers: 007: make both bels and routing-bels 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala cb3a2b42d7 fuzzers: 007: produce sdf files for routing bels 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala b0cc42353a third-party: bump python-sdf-timing submodule 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala 2c1d4342b7 fuzzers: 007: format python 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala 94f3baf157 third-party: bump python-sdf-timing submodule 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala ec28d95604 fuzzers: 007: add routing BELs fuzzer 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
litghost f357aa06c1
Merge pull request #896 from antmicro/895_falsely_ignored_pips 
Fix problem with falsely ignored PIPs
 2019-06-28 08:55:14 -07:00
Maciej Kurc 4d6f75e8ad Added packing tests for SRL32+LUT6 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-28 10:53:27 +02:00
Maciej Kurc 98bcd3f447 Added full vivado flow to the Makefile 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-28 10:53:22 +02:00
Maciej Kurc 4c2b0a5395 Added minitests for SRLs 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-27 15:13:18 +02:00
Tomasz Michalak 36e9120fc7 Fix problem with falsely ignored PIPs 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-27 08:01:01 +02:00
litghost 5fb2153a0a
Merge pull request #889 from antmicro/875_44_clk_bufg_pips 
Fix duplicate tag in 044-clk-bufg-pips
 2019-06-26 08:31:58 -07:00
litghost 38087b313b
Merge pull request #909 from litghost/slow_harness 
Add ROI base file that adds a clock divider.
 2019-06-26 08:19:53 -07:00
Alessandro Comodi ca6bbee193
Merge pull request #908 from antmicro/fix-bram-timing-fuzzer 
007-timing: added missing aliases for bram timing
 2019-06-26 13:00:20 +02:00
Keith Rothman e697365c7d Add ROI base file that adds a clock divider. 
This cannot be used for an ROI harness until
https://github.com/SymbiFlow/prjxray/issues/891 is complete.

Command to build new harness
```
XRAY_ROIV=../roi_base_div2.v make
```

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-25 12:05:44 -07:00
litghost b8f64484da
Merge pull request #901 from antmicro/bel-fuzzer-stabilization 
BEL fuzzer stabilization
 2019-06-25 10:43:12 -07:00