mirror of https://github.com/openXC7/prjxray.git
Merge pull request #899 from antmicro/routing-bels
Fuzzers: 007-timing: add routing BELs fuzzer
This commit is contained in:
Karol Gugala
GitHub
commit
219f0f0175
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@ -0,0 +1,2 @@
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*.json
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sdfs
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@ -1,10 +1,30 @@
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SLICEL_SDFS = bel/build/CLBLL_L.sdf bel/build/CLBLL_R.sdf bel/build/CLBLM_L.sdf bel/build/CLBLM_R.sdf routing-bels/build/slicel.sdf
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SLICEM_SDFS = bel/build/CLBLL_L.sdf bel/build/CLBLL_R.sdf bel/build/CLBLM_L.sdf bel/build/CLBLM_R.sdf routing-bels/build/slicem.sdf
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run: all
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all: bel/build/sdf
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touch run.ok
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all: pushdb
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clean:
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cd bel && $(MAKE) clean
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cd routing-bels && $(MAKE) clean
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bel/build/sdf:
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bel/build/sdf.ok:
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cd bel && $(MAKE)
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routing-bels/build/sdf:
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cd routing-bels && $(MAKE)
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mergesdfs: bel/build/sdf.ok routing-bels/build/sdf
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mkdir -p sdfs
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python3 ${XRAY_UTILS_DIR}/sdfmerge.py --sdfs $(SLICEM_SDFS) --site SLICEM --out sdfs/slicem.sdf
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python3 ${XRAY_UTILS_DIR}/sdfmerge.py --sdfs $(SLICEL_SDFS) --site SLICEL --out sdfs/slicel.sdf --json debu.json
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cp bel/build/*.sdf sdfs
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pushdb: mergesdfs
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mkdir -p ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/timings
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cp sdfs/*.sdf ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/timings
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touch run.ok
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cleandb:
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rm -rf ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/timings
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@ -1,12 +1,12 @@
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all: pushdb
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all: build/sdf.ok
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clean:
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rm -rf build
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build/bel_timings.txt:
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build/run.ok:
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bash runme.sh
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build/fixup_timings: build/bel_timings.txt
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build/fixup_timings: build/run.ok
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python3 fixup_timings_txt.py --txtin build/bel_timings.txt --txtout build/bel_timings.txt --site RAMBFIFO36E1 --slice BRAM_L --type timings
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python3 fixup_timings_txt.py --txtin build/bel_timings.txt --txtout build/bel_timings.txt --site RAMBFIFO36E1 --slice BRAM_R --type timings
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python3 fixup_timings_txt.py --txtin build/bel_pins.txt --txtout build/bel_pins.txt --site RAMBFIFO36E1 --slice BRAM_L --type pins
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@ -17,17 +17,7 @@ build/fixup_timings: build/bel_timings.txt
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build/bel_timings.json: build/fixup_timings
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python3 tim2json.py --timings=build/bel_timings.txt --json=build/bel_timings.json --properties=build/bel_properties.txt --propertiesmap=properties_map.json --pinaliasmap=pin_alias_map.json --belpins=build/bel_pins.txt --sitepins=build/tile_pins.txt --debug true
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build/sdf: build/bel_timings.json
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build/sdf.ok: build/bel_timings.json
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python3 ${XRAY_UTILS_DIR}/makesdf.py --json=${PWD}/build/bel_timings.json --sdf=${PWD}/build
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touch build/sdf.ok
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cleandb:
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rm -rf ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/timings
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mergesdfs: build/sdf
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python3 ${XRAY_UTILS_DIR}/sdfmerge.py --sdfs build/CLBLL_L.sdf build/CLBLL_R.sdf build/CLBLM_L.sdf build/CLBLM_R.sdf --site SLICEM --out build/slicem.sdf
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python3 ${XRAY_UTILS_DIR}/sdfmerge.py --sdfs build/CLBLL_L.sdf build/CLBLL_R.sdf build/CLBLM_L.sdf build/CLBLM_R.sdf --site SLICEL --out build/slicel.sdf
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pushdb: mergesdfs
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mkdir -p ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/timings
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cp build/*sdf ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/timings
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touch run.ok
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@ -0,0 +1 @@
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*json
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@ -0,0 +1,17 @@
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all: build/slicel.sdf build/slicem.sdf
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clean:
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rm -rf build
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build/slicel.sdf: build/run.ok
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python3 tim2sdf.py --timings build/slicel.txt --site SLICEL --sdf build/slicel.sdf
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build/slicem.sdf: build/run.ok
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python3 tim2sdf.py --timings build/slicem.txt --site SLICEM --sdf build/slicem.sdf
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build/run.ok:
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bash runme.sh
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cleandb:
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rm -rf ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/timings
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@ -0,0 +1,13 @@
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#!/bin/bash
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set -ex
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# Create build dir
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export SRC_DIR=$PWD
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export BUILD_DIR=build
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mkdir -p $BUILD_DIR
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cd $BUILD_DIR
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${XRAY_VIVADO} -mode batch -source $SRC_DIR/runme.tcl
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test -z "$(fgrep CRITICAL vivado.log)" && touch run.ok
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@ -0,0 +1,62 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc create_design {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog $::env(SRC_DIR)/top.v
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synth_design -top top -flatten_hierarchy none
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports do]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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}
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proc place_and_route_design {} {
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place_design
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route_design
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write_checkpoint -force design.dcp
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}
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proc dump_model_timings {timing_fp models} {
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set properties [list "DELAY" "FAST_MAX" "FAST_MIN" "SLOW_MAX" "SLOW_MIN"]
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foreach model $models {
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set timing_line {}
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lappend timing_line "$model"
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foreach property $properties {
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set value [get_property $property [get_speed_models -patterns $model]]
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lappend timing_line "$property:$value"
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}
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puts $timing_fp $timing_line
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}
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}
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proc dump {} {
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set slicel_fp [open "slicel.txt" w]
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set slicem_fp [open "slicem.txt" w]
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set slicel_speed_models [get_speed_models -patterns *_sl_*]
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set slicem_speed_models [get_speed_models -patterns *_sm_*]
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dump_model_timings $slicel_fp $slicel_speed_models
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dump_model_timings $slicem_fp $slicem_speed_models
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close $slicel_fp
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close $slicem_fp
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}
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proc run {} {
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create_design
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place_and_route_design
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dump
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write_bitstream -force design.bit
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}
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run
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#!/usr/bin/env python3
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import argparse
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import json
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from sdf_timing import sdfparse
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from sdf_timing import utils
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def generate_sdf(timings, sdffile):
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sdf_data = sdfparse.emit(timings, timescale='1ns')
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with open(sdffile, 'w') as fp:
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fp.write(sdf_data)
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def add_timing_paths_entry(paths, type, values):
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paths[type] = dict()
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paths[type]['min'] = values[0]
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paths[type]['avg'] = values[1]
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paths[type]['max'] = values[2]
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return paths
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def read_raw_timings(fin, site):
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timings = dict()
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timings['cells'] = dict()
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with open(fin, "r") as f:
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for line in f:
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raw_data = line.split()
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speed_model = raw_data[0]
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if speed_model.startswith('bel_d_'):
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speed_model = speed_model[6:]
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speed_model_split = speed_model.split('_')
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interconn_input = "_".join(speed_model_split[1:-1])
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interconn_output = speed_model_split[-1]
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celltype = "routing_bel"
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if celltype not in timings['cells']:
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timings['cells'][celltype] = dict()
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cellsite = site + '/' + interconn_output.upper()
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if cellsite not in timings['cells'][celltype]:
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timings['cells'][celltype][cellsite] = dict()
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if speed_model not in timings['cells'][celltype][cellsite]:
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timings['cells'][celltype][cellsite][speed_model] = dict()
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delays = dict()
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# each timing entry reports 5 delays
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for d in range(0, 5):
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(t, v) = raw_data[d + 1].split(':')
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delays[t] = v
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# create entry for sdf writer
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iport = dict()
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iport['port'] = interconn_input
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iport['port_edge'] = None
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oport = dict()
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oport['port'] = interconn_output
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oport['port_edge'] = None
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paths = dict()
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paths = add_timing_paths_entry(
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paths, 'slow', [delays['SLOW_MIN'], None, delays['SLOW_MAX']])
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paths = add_timing_paths_entry(
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paths, 'fast', [delays['FAST_MIN'], None, delays['FAST_MAX']])
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if speed_model.endswith('diff'):
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iport['port'] = "_".join(speed_model_split[1:])
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iport['port_edge'] = None
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timings['cells'][celltype][cellsite][
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speed_model] = utils.add_device(iport, paths)
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else:
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timings['cells'][celltype][cellsite][
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speed_model] = utils.add_interconnect(iport, oport, paths)
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timings['cells'][celltype][cellsite][speed_model][
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'is_absolute'] = True
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return timings
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def main():
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parser = argparse.ArgumentParser()
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parser.add_argument('--timings', type=str, help='Raw timing input file')
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parser.add_argument('--sdf', type=str, help='output sdf file')
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parser.add_argument(
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'--site', type=str, help='Site of the processed timings')
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parser.add_argument(
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'--debug', type=bool, default=False, help='Enable debug json dumps')
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args = parser.parse_args()
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timings = read_raw_timings(args.timings, args.site)
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if args.debug:
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with open("debug" + args.site + ".json", 'w') as fp:
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json.dump(timings, fp, indent=4, sort_keys=True)
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generate_sdf(timings, args.sdf)
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if __name__ == '__main__':
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main()
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module top(input di, output do);
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assign do = di;
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endmodule
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@ -1 +1 @@
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Subproject commit 95010bcea451ad8a5bf7308a80001d16012ae116
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Subproject commit 679152c9e6b92627cffba186618ab98ac29b627b
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@ -55,7 +55,7 @@ def main():
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timings_list.append(timing)
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merged_sdf = merge(timings_list, args.site)
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open(args.out, 'w').write(sdfparse.emit(merged_sdf))
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open(args.out, 'w').write(sdfparse.emit(merged_sdf, timescale='1ns'))
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if args.json is not None:
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with open(args.json, 'w') as fp:
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