mirror of https://github.com/openXC7/prjxray.git
Merge pull request #926 from litghost/add_pll_interconnect_fuzzer
Add PLL fuzzer
This commit is contained in:
litghost
GitHub
commit
f400565f71
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@ -36,7 +36,9 @@ DB_SIMPLE_L=$(addprefix segbits_,$(SEGBITS_L))
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DB_SIMPLE_R=$(addprefix segbits_,$(SEGBITS_R))
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DB_SIMPLE=\
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$(addsuffix _l, $(DB_SIMPLE_LR) $(DB_SIMPLE_L)) \
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$(addsuffix _r, $(DB_SIMPLE_LR) $(DB_SIMPLE_R))
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$(addsuffix _r, $(DB_SIMPLE_LR) $(DB_SIMPLE_R)) \
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segbits_cmt_top_l_upper_t \
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segbits_cmt_top_r_upper_t \
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BLOCK_RAM_EXTRA_FOR=\
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mask_bram \
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@ -18,6 +18,7 @@ TILEGRID_TDB_DEPENDENCIES += monitor_int/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += clk_hrow/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += clk_bufg/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += hclk_cmt/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += pll/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += hclk_ioi/build/segbits_tilegrid.tdb
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GENERATE_FULL_ARGS=
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@ -26,7 +27,6 @@ ifeq (${XRAY_DATABASE}, zynq7)
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TILEGRID_TDB_DEPENDENCIES += ps7_int/build/segbits_tilegrid.tdb
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else
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# Artix7/Kintex7 only
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TILEGRID_TDB_DEPENDENCIES += pll/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += mmcm/build/segbits_tilegrid.tdb
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endif
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@ -79,7 +79,7 @@ def run(fn_in, fn_out, verbose=False):
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("iob/build/segbits_tilegrid.tdb", 42, 4),
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("ioi/build/segbits_tilegrid.tdb", 42, 4),
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("mmcm/build/segbits_tilegrid.tdb", 30, 101),
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("pll/build/segbits_tilegrid.tdb", 30, 101),
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("pll/build/segbits_tilegrid.tdb", 30, 26),
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("monitor/build/segbits_tilegrid.tdb", 30, 101),
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("bram/build/segbits_tilegrid.tdb", 28, 10),
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("bram_block/build/segbits_tilegrid.tdb", 128, 10),
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@ -1,3 +1,3 @@
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N ?= 5
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GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 1C --dword 98"
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GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 1C --dword 23"
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include ../fuzzaddr/common.mk
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@ -1,12 +1,23 @@
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# read/write width is relatively slow to resolve
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# Even slower with multi bit masks...
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N := 8
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N := 50
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include ../fuzzer.mk
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database: $(SPECIMENS_OK)
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database: build/segbits_cmt_top_upper_t.db
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pushdb:
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echo "FIXME" && false
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build/segbits_cmt_top_upper_t.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -c 150 -o build/segbits_cmt_top_upper_t.rdb \
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$(shell find build -name "segdata_cmt_top_*_upper_t.txt")
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build/segbits_cmt_top_upper_t.db: build/segbits_cmt_top_upper_t.rdb write_pll_reg.py
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python3 write_pll_reg.py \
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--seg_in build/segbits_cmt_top_upper_t.rdb \
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> build/segbits_cmt_top_upper_t.rdb2
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_cmt_top_upper_t.rdb2 \
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--seg-fn-out build/segbits_cmt_top_upper_t.db
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pushdb: database
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${XRAY_MERGEDB} cmt_top_r_upper_t build/segbits_cmt_top_upper_t.db
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${XRAY_MERGEDB} cmt_top_l_upper_t build/segbits_cmt_top_upper_t.db
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.PHONY: database pushdb
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@ -1,3 +1,4 @@
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# Clock Management Tile (CMT) - Phase Lock Loop (PLL) Fuzzer
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FIXME: Add description.
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Bits that are part of the dynamic configration register interface (see APPNOTE
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XAPP888) are handled specially.
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@ -6,15 +6,155 @@ from prjxray.segmaker import Segmaker
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from prjxray import verilog
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def bitfilter(frame, word):
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if frame < 28:
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return False
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if frame == 25 and word == 3121:
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return False
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return True
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def bus_tags(segmk, ps, site):
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for param, tagname in [('CLKOUT0_DIVIDE', 'ZCLKOUT0_DIVIDE')]:
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segmk.add_site_tag(site, 'IN_USE', ps['active'])
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if not ps['active']:
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return
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for k in ps:
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segmk.add_site_tag(site, 'param_' + k + '_' + str(ps[k]), 1)
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for reg, invert in [
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('RST', 1),
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('PWRDWN', 1),
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('CLKINSEL', 0),
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]:
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opt = 'IS_{}_INVERTED'.format(reg)
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if invert:
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segmk.add_site_tag(site, 'ZINV_' + reg, 1 ^ ps[opt])
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else:
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segmk.add_site_tag(site, 'INV_' + reg, ps[opt])
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for opt in ['OPTIMIZED', 'HIGH', 'LOW']:
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if verilog.unquote(ps['BANDWIDTH']) == opt:
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segmk.add_site_tag(site, 'BANDWIDTH.' + opt, 1)
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elif verilog.unquote(ps['BANDWIDTH']) == 'LOW':
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segmk.add_site_tag(site, 'BANDWIDTH.' + opt, 0)
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for opt in ['ZHOLD', 'BUF_IN', 'EXTERNAL', 'INTERNAL']:
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continue
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opt_match = verilog.unquote(ps['COMPENSATION']) == opt
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if ps['clkfbin_conn'] == '':
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segmk.add_site_tag(site, 'COMP.NOFB_' + opt, opt_match)
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segmk.add_site_tag(site, 'COMP.ZNOFB_' + opt, opt_match)
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continue
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for conn in ['clk', 'clkfbout_mult_BUFG_' + ps['site'],
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'clkfbout_mult_' + ps['site']]:
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conn_match = ps['clkfbin_conn'] == conn
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segmk.add_site_tag(
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site, 'COMP.' + opt + '_' + conn + '_' + ps['site'], opt_match
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and conn_match)
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segmk.add_site_tag(
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site, 'COMP.Z' + opt + '_' + conn + '_' + ps['site'],
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not opt_match and conn_match)
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segmk.add_site_tag(
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site, 'COMP.Z' + opt + '_Z' + conn + '_' + ps['site'],
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not opt_match and not conn_match)
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segmk.add_site_tag(
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site, 'COMP.' + opt + '_Z' + conn + '_' + ps['site'], opt_match
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and not conn_match)
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match = verilog.unquote(ps['COMPENSATION']) in ['BUF_IN', 'EXTERNAL']
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bufg_on_clkin = \
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'BUFG' in ps['clkin1_conn'] or \
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'BUFG' in ps['clkin2_conn']
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if not match:
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if verilog.unquote(ps['COMPENSATION']) == 'ZHOLD' and bufg_on_clkin:
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match = True
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segmk.add_site_tag(
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site, 'COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF', match)
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match = verilog.unquote(ps['COMPENSATION']) in ['ZHOLD']
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segmk.add_site_tag(
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site, 'COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF', not match
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or (match and bufg_on_clkin))
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segmk.add_site_tag(
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site, 'COMPENSATION.ZHOLD_NO_CLKIN_BUF', match and \
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not bufg_on_clkin
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)
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segmk.add_site_tag(
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site, 'COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP', match and \
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not bufg_on_clkin and \
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site != "PLLE2_ADV_X0Y2"
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)
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segmk.add_site_tag(
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site, 'COMP.ZHOLD_NO_CLKIN_BUF_TOP', match and \
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not bufg_on_clkin and \
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site == "PLLE2_ADV_X0Y2"
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)
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for opt in ['ZHOLD', 'BUF_IN', 'EXTERNAL', 'INTERNAL']:
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if opt in ['BUF_IN', 'EXTERNAL']:
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if ps['clkfbin_conn'] not in ['', 'clk']:
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continue
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if site == "PLLE2_ADV_X0Y2" and opt == 'ZHOLD':
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segmk.add_site_tag(
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site, 'TOP.COMPENSATION.' + opt,
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verilog.unquote(ps['COMPENSATION']) == opt)
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else:
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segmk.add_site_tag(
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site, 'COMPENSATION.' + opt,
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verilog.unquote(ps['COMPENSATION']) == opt)
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segmk.add_site_tag(
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site, 'COMPENSATION.Z_' + opt,
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verilog.unquote(ps['COMPENSATION']) != opt)
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segmk.add_site_tag(
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site, 'COMPENSATION.INTERNAL',
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verilog.unquote(ps['COMPENSATION']) in ['INTERNAL'])
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for param in ['CLKFBOUT_MULT']:
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paramadj = int(ps[param])
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bitstr = [int(x) for x in "{0:09b}".format(paramadj)[::-1]]
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for i in range(7):
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segmk.add_site_tag(site, '%s[%u]' % (param, i), bitstr[i])
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for param in ['CLKOUT0_DUTY_CYCLE']:
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assert ps[param][:2] == '0.', ps[param]
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assert len(ps[param]) == 5
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paramadj = int(ps[param][2:])
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bitstr = [int(x) for x in "{0:011b}".format(paramadj)[::-1]]
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for i in range(10):
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segmk.add_site_tag(site, '%s[%u]' % (param, i), bitstr[i])
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for param, bits in [
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('CLKOUT0_DIVIDE', 7),
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('CLKOUT1_DIVIDE', 7),
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('CLKOUT2_DIVIDE', 7),
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('CLKOUT3_DIVIDE', 7),
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('CLKOUT4_DIVIDE', 7),
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('CLKOUT5_DIVIDE', 7),
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('DIVCLK_DIVIDE', 6),
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]:
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# 1-128 => 0-127 for actual 7 bit value
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paramadj = int(ps[param]) - 1
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bitstr = [int(x) for x in "{0:07b}".format(paramadj)[::-1]]
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# FIXME: only bits 0 and 1 resolving
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# for i in range(7):
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for i in range(2):
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segmk.add_site_tag(site, '%s[%u]' % (param, i), 1 ^ bitstr[i])
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paramadj = int(ps[param])
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if paramadj < 4:
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continue
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bitstr = [int(x) for x in "{0:09b}".format(paramadj)[::-1]]
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for i in range(bits):
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segmk.add_site_tag(site, '%s[%u]' % (param, i), bitstr[i])
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segmk.add_site_tag(
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site, 'STARTUP_WAIT',
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verilog.unquote(ps['STARTUP_WAIT']) == 'TRUE')
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def run():
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@ -26,13 +166,9 @@ def run():
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f.readline()
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for l in f:
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j = json.loads(l)
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ps = j['params']
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assert j['module'] == 'my_PLLE2_ADV'
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site = verilog.unquote(ps['LOC'])
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bus_tags(segmk, j, j['site'])
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bus_tags(segmk, ps, site)
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segmk.compile()
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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@ -3,20 +3,18 @@ read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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create_clock -period 10.00 [get_ports clk]
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set net [get_nets clk_IBUF]
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if { [llength $net] > 0 } {
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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}
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# Disable MMCM frequency etc sanity checks
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
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@ -24,10 +22,29 @@ set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-126}]
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# PLL
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-43}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-78}]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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set fp [open params.json "w"]
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puts $fp "\["
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foreach cell [get_cells -hierarchical -filter {REF_NAME == PLLE2_ADV}] {
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puts $fp " {"
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puts $fp " \"tile\": \"[get_tiles -of [get_sites -of $cell]]\","
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puts $fp " \"site\": \"[get_sites -of $cell]\","
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puts $fp " \"params\": {"
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foreach prop [list_property $cell] {
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puts $fp " \"$prop\": \"[get_property $prop $cell]\","
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}
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puts $fp " }"
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puts $fp " },"
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}
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puts $fp "\]"
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close $fp
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@ -3,102 +3,247 @@ import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.verilog import vrandbit, vrandbits
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import sys
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from prjxray.db import Database
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import json
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def gen_sites():
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for _tile_name, site_name, _site_type in sorted(util.get_roi().gen_sites(
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["PLLE2_ADV"])):
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yield site_name
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site_name, site_type in gridinfo.sites.items():
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if site_type in ['PLLE2_ADV']:
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yield site_name
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sites = list(gen_sites())
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DUTN = len(sites)
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DIN_N = DUTN * 8
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DOUT_N = DUTN * 8
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def main():
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f = open('params.jl', 'w')
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f.write('module,loc,params\n')
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verilog.top_harness(DIN_N, DOUT_N)
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f = open('params.jl', 'w')
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f.write('module,loc,params\n')
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print(
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'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
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(DIN_N - 1, DOUT_N - 1))
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for loci, site in enumerate(sites):
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ports = {
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'clk': 'clk',
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'din': 'din[ %d +: 8]' % (8 * loci, ),
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'dout': 'dout[ %d +: 8]' % (8 * loci, ),
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}
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params = {
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"CLKOUT0_DIVIDE": random.randint(1, 128),
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}
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modname = "my_PLLE2_ADV"
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verilog.instance(modname, "inst_%u" % loci, ports, params=params)
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# LOC isn't support
|
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params["LOC"] = verilog.quote(site)
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|
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j = {'module': modname, 'i': loci, 'params': params}
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f.write('%s\n' % (json.dumps(j)))
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print('')
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||||
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f.close()
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print(
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'''endmodule
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||||
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// ---------------------------------------------------------------------
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|
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''')
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print(
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'''
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module my_PLLE2_ADV (input clk, input [7:0] din, output [7:0] dout);
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parameter CLKOUT0_DIVIDE = 1;
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parameter CLKOUT1_DIVIDE = 1;
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parameter CLKOUT2_DIVIDE = 1;
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parameter CLKOUT3_DIVIDE = 1;
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parameter CLKOUT4_DIVIDE = 1;
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parameter CLKOUT5_DIVIDE = 1;
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parameter DIVCLK_DIVIDE = 1;
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parameter CLKFBOUT_MULT = 5;
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print(
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"""module top(input clk);
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT1 dummy();
|
||||
""")
|
||||
|
||||
for site in sorted(gen_sites()):
|
||||
params = {
|
||||
"site":
|
||||
site,
|
||||
'active':
|
||||
random.random() > .2,
|
||||
"clkin1_conn":
|
||||
random.choice((
|
||||
"clkfbout_mult_BUFG_" + site,
|
||||
"clk",
|
||||
)),
|
||||
"clkin2_conn":
|
||||
random.choice((
|
||||
"clkfbout_mult_BUFG_" + site,
|
||||
"clk",
|
||||
)),
|
||||
"dclk_conn":
|
||||
random.choice((
|
||||
"0",
|
||||
"clk",
|
||||
)),
|
||||
"dwe_conn":
|
||||
random.choice((
|
||||
"",
|
||||
"1",
|
||||
"0",
|
||||
"dwe_" + site,
|
||||
"den_" + site,
|
||||
)),
|
||||
"den_conn":
|
||||
random.choice((
|
||||
"",
|
||||
"1",
|
||||
"0",
|
||||
"den_" + site,
|
||||
)),
|
||||
"daddr4_conn":
|
||||
random.choice((
|
||||
"0",
|
||||
"dwe_" + site,
|
||||
)),
|
||||
"IS_RST_INVERTED":
|
||||
random.randint(0, 1),
|
||||
"IS_PWRDWN_INVERTED":
|
||||
random.randint(0, 1),
|
||||
"IS_CLKINSEL_INVERTED":
|
||||
random.randint(0, 1),
|
||||
"CLKFBOUT_MULT":
|
||||
random.randint(2, 4),
|
||||
"CLKOUT0_DIVIDE":
|
||||
random.randint(1, 128),
|
||||
"CLKOUT1_DIVIDE":
|
||||
random.randint(1, 128),
|
||||
"CLKOUT2_DIVIDE":
|
||||
random.randint(1, 128),
|
||||
"CLKOUT3_DIVIDE":
|
||||
random.randint(1, 128),
|
||||
"CLKOUT4_DIVIDE":
|
||||
random.randint(1, 128),
|
||||
"CLKOUT5_DIVIDE":
|
||||
random.randint(1, 128),
|
||||
"DIVCLK_DIVIDE":
|
||||
random.randint(1, 5),
|
||||
"CLKOUT0_DUTY_CYCLE":
|
||||
"0.500",
|
||||
"STARTUP_WAIT":
|
||||
verilog.quote('TRUE' if random.randint(0, 1) else 'FALSE'),
|
||||
"COMPENSATION":
|
||||
verilog.quote(
|
||||
random.choice((
|
||||
'ZHOLD',
|
||||
'BUF_IN',
|
||||
'EXTERNAL',
|
||||
'INTERNAL',
|
||||
))),
|
||||
"BANDWIDTH":
|
||||
verilog.quote(random.choice((
|
||||
'OPTIMIZED',
|
||||
'HIGH',
|
||||
'LOW',
|
||||
))),
|
||||
}
|
||||
|
||||
if verilog.unquote(params['COMPENSATION']) == 'ZHOLD':
|
||||
params['clkfbin_conn'] = random.choice(
|
||||
(
|
||||
"",
|
||||
"clkfbout_mult_BUFG_" + site,
|
||||
))
|
||||
elif verilog.unquote(params['COMPENSATION']) == 'INTERNAL':
|
||||
params['clkfbin_conn'] = random.choice(
|
||||
(
|
||||
"",
|
||||
"clkfbout_mult_" + site,
|
||||
))
|
||||
else:
|
||||
params['clkfbin_conn'] = random.choice(
|
||||
("", "clk", "clkfbout_mult_BUFG_" + site))
|
||||
|
||||
f.write('%s\n' % (json.dumps(params)))
|
||||
|
||||
if not params['active']:
|
||||
continue
|
||||
|
||||
print(
|
||||
"""
|
||||
|
||||
wire den_{site};
|
||||
wire dwe_{site};
|
||||
|
||||
LUT1 den_lut_{site} (
|
||||
.O(den_{site})
|
||||
);
|
||||
|
||||
LUT1 dwe_lut_{site} (
|
||||
.O(dwe_{site})
|
||||
);
|
||||
|
||||
wire clkfbout_mult_{site};
|
||||
wire clkfbout_mult_BUFG_{site};
|
||||
wire clkout0_{site};
|
||||
wire clkout1_{site};
|
||||
wire clkout2_{site};
|
||||
wire clkout3_{site};
|
||||
wire clkout4_{site};
|
||||
wire clkout5_{site};
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
PLLE2_ADV #(
|
||||
.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
|
||||
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
|
||||
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
|
||||
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
|
||||
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
|
||||
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
|
||||
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
|
||||
.CLKFBOUT_MULT(CLKFBOUT_MULT)
|
||||
) dut(
|
||||
.CLKFBOUT(),
|
||||
.CLKOUT0(dout[0]),
|
||||
.CLKOUT1(),
|
||||
.CLKOUT2(),
|
||||
.CLKOUT3(),
|
||||
.CLKOUT4(),
|
||||
.CLKOUT5(),
|
||||
.IS_RST_INVERTED({IS_RST_INVERTED}),
|
||||
.IS_PWRDWN_INVERTED({IS_PWRDWN_INVERTED}),
|
||||
.IS_CLKINSEL_INVERTED({IS_CLKINSEL_INVERTED}),
|
||||
.CLKOUT0_DIVIDE({CLKOUT0_DIVIDE}),
|
||||
.CLKOUT1_DIVIDE({CLKOUT1_DIVIDE}),
|
||||
.CLKOUT2_DIVIDE({CLKOUT2_DIVIDE}),
|
||||
.CLKOUT3_DIVIDE({CLKOUT3_DIVIDE}),
|
||||
.CLKOUT4_DIVIDE({CLKOUT4_DIVIDE}),
|
||||
.CLKOUT5_DIVIDE({CLKOUT5_DIVIDE}),
|
||||
.CLKFBOUT_MULT({CLKFBOUT_MULT}),
|
||||
.DIVCLK_DIVIDE({DIVCLK_DIVIDE}),
|
||||
.STARTUP_WAIT({STARTUP_WAIT}),
|
||||
.CLKOUT0_DUTY_CYCLE({CLKOUT0_DUTY_CYCLE}),
|
||||
.COMPENSATION({COMPENSATION}),
|
||||
.BANDWIDTH({BANDWIDTH}),
|
||||
.CLKIN1_PERIOD(10.0),
|
||||
.CLKIN2_PERIOD(10.0)
|
||||
) pll_{site} (
|
||||
.CLKFBOUT(clkfbout_mult_{site}),
|
||||
.CLKOUT0(clkout0_{site}),
|
||||
.CLKOUT1(clkout1_{site}),
|
||||
.CLKOUT2(clkout2_{site}),
|
||||
.CLKOUT3(clkout3_{site}),
|
||||
.CLKOUT4(clkout4_{site}),
|
||||
.CLKOUT5(clkout5_{site}),
|
||||
.DRDY(),
|
||||
.LOCKED(),
|
||||
.DO(),
|
||||
.CLKFBIN(),
|
||||
.CLKIN1(),
|
||||
.CLKIN2(),
|
||||
.CLKFBIN({clkfbin_conn}),
|
||||
.CLKIN1({clkin1_conn}),
|
||||
.CLKIN2({clkin2_conn}),
|
||||
.CLKINSEL(),
|
||||
.DCLK(),
|
||||
.DEN(),
|
||||
.DWE(),
|
||||
.DCLK({dclk_conn}),
|
||||
.DEN({den_conn}),
|
||||
.DWE({dwe_conn}),
|
||||
.PWRDWN(),
|
||||
.RST(din[0]),
|
||||
.RST(),
|
||||
.DI(),
|
||||
.DADDR());
|
||||
endmodule
|
||||
''')
|
||||
.DADDR({{7{{ {daddr4_conn} }} }}));
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
BUFG bufg_{site} (
|
||||
.I(clkfbout_mult_{site}),
|
||||
.O(clkfbout_mult_BUFG_{site})
|
||||
);
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
FDRE reg_clkfbout_mult_{site} (
|
||||
.C(clkfbout_mult_{site})
|
||||
);
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
FDRE reg_clkout0_{site} (
|
||||
.C(clkout0_{site})
|
||||
);
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
FDRE reg_clkout1_{site} (
|
||||
.C(clkout1_{site})
|
||||
);
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
FDRE reg_clkout2_{site} (
|
||||
.C(clkout2_{site})
|
||||
);
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
FDRE reg_clkout3_{site} (
|
||||
.C(clkout3_{site})
|
||||
);
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
FDRE reg_clkout4_{site} (
|
||||
.C(clkout4_{site})
|
||||
);
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
FDRE reg_clkout5_{site} (
|
||||
.C(clkout5_{site})
|
||||
);
|
||||
""".format(**params))
|
||||
|
||||
print('endmodule')
|
||||
|
||||
f.close()
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
|
|||
|
|
@ -0,0 +1,284 @@
|
|||
import argparse
|
||||
|
||||
REGISTER_LAYOUT = {
|
||||
'CLKOUT1': [
|
||||
('LOW_TIME', 6),
|
||||
('HIGH_TIME', 6),
|
||||
('OUTPUT_ENABLE', 1),
|
||||
('PHASE_MUX', 3),
|
||||
],
|
||||
'CLKOUT2': [
|
||||
('DELAY_TIME', 6),
|
||||
('NO_COUNT', 1),
|
||||
('EDGE', 1),
|
||||
('MX', 2),
|
||||
('FRAC_WF_R', 1),
|
||||
('FRAC_EN', 1),
|
||||
('FRAC', 3),
|
||||
('RESERVED', 1),
|
||||
],
|
||||
'DIVCLK': [
|
||||
('LOW_TIME', 6),
|
||||
('HIGH_TIME', 6),
|
||||
('NO_COUNT', 1),
|
||||
('EDGE', 1),
|
||||
('RESERVED', 2),
|
||||
],
|
||||
'LOCKREG1': [
|
||||
('LKTABLE', 10, 20),
|
||||
('LOCKREG1_RESERVED', 6, 0),
|
||||
],
|
||||
'LOCKREG2': [
|
||||
('LKTABLE', 10, 0),
|
||||
('LKTABLE', 5, 30),
|
||||
('LOCKREG2_RESERVED', 1, 0),
|
||||
],
|
||||
'LOCKREG3': [
|
||||
('LKTABLE', 10, 10),
|
||||
('LKTABLE', 5, 35),
|
||||
('LOCKREG3_RESERVED', 1, 0),
|
||||
],
|
||||
'FILTREG1': [
|
||||
('FILTREG1_RESERVED', 8, 0),
|
||||
('TABLE', 1, 6),
|
||||
('FILTREG1_RESERVED', 2, 8),
|
||||
('TABLE', 2, 7),
|
||||
('FILTREG1_RESERVED', 2, 10),
|
||||
('TABLE', 1, 9),
|
||||
],
|
||||
'FILTREG2': [
|
||||
('FILTREG2_RESERVED', 4, 0),
|
||||
('TABLE', 1, 0),
|
||||
('FILTREG2_RESERVED', 2, 4),
|
||||
('TABLE', 2, 1),
|
||||
('FILTREG2_RESERVED', 2, 6),
|
||||
('TABLE', 2, 3),
|
||||
('FILTREG2_RESERVED', 2, 8),
|
||||
('TABLE', 1, 5),
|
||||
],
|
||||
'POWER_REG': [
|
||||
('POWER_REG', 16),
|
||||
],
|
||||
}
|
||||
|
||||
BASE_OFFSET = 0x00
|
||||
REGISTER_MAP = []
|
||||
|
||||
REGISTER_MAP.append(None)
|
||||
REGISTER_MAP.append(None)
|
||||
|
||||
for idx in range(3):
|
||||
REGISTER_MAP.append(None)
|
||||
|
||||
REGISTER_MAP.append(None)
|
||||
|
||||
# 0x06 - 0x15
|
||||
for output in ['CLKOUT5', 'CLKOUT0', 'CLKOUT1', 'CLKOUT2', 'CLKOUT3',
|
||||
'CLKOUT4', None, 'CLKFBOUT']:
|
||||
if output is not None:
|
||||
REGISTER_MAP.append(('CLKOUT1', output))
|
||||
REGISTER_MAP.append(('CLKOUT2', output))
|
||||
else:
|
||||
REGISTER_MAP.append(None)
|
||||
REGISTER_MAP.append(None)
|
||||
|
||||
# 0x16
|
||||
REGISTER_MAP.append(('DIVCLK', 'DIVCLK'))
|
||||
# 0x17
|
||||
REGISTER_MAP.append(None)
|
||||
# 0x18-0x1A
|
||||
REGISTER_MAP.append(('LOCKREG1', 'LOCKREG1'))
|
||||
REGISTER_MAP.append(('LOCKREG2', 'LOCKREG2'))
|
||||
REGISTER_MAP.append(('LOCKREG3', 'LOCKREG3'))
|
||||
|
||||
for _ in range(0x28 - 0x1A - 1):
|
||||
REGISTER_MAP.append(None)
|
||||
|
||||
REGISTER_MAP.append(('POWER_REG', 'POWER_REG'))
|
||||
|
||||
for _ in range(0x4E - 0x28 - 1):
|
||||
REGISTER_MAP.append(None)
|
||||
|
||||
# 0x4E - 0x4F
|
||||
REGISTER_MAP.append(('FILTREG1', 'FILTREG1'))
|
||||
REGISTER_MAP.append(('FILTREG2', 'FILTREG2'))
|
||||
|
||||
for _ in range(0x20):
|
||||
REGISTER_MAP.append(None)
|
||||
|
||||
|
||||
class RegisterAddress(object):
|
||||
def __init__(self, frame_offsets, bit_offset):
|
||||
self.frame_index = 0
|
||||
self.frame_offsets = frame_offsets
|
||||
self.bit_offset = bit_offset
|
||||
self.bits_used = set()
|
||||
|
||||
def next_bit(self, used=True):
|
||||
output = '{}_{}'.format(
|
||||
self.frame_offsets[self.frame_index], self.bit_offset)
|
||||
|
||||
if used:
|
||||
self.bits_used.add(output)
|
||||
|
||||
self.frame_index += 1
|
||||
if self.frame_index >= len(self.frame_offsets):
|
||||
self.frame_index = 0
|
||||
self.bit_offset += 1
|
||||
|
||||
return output
|
||||
|
||||
|
||||
def passthrough_non_register_segbits(seg_in):
|
||||
""" Filter input segbits file and capture register base offset.
|
||||
|
||||
Some PLL bit ranges are documented registers in the PLL/MMCM dynamic
|
||||
reconfiguration iterface. These features will be generated in
|
||||
output_registers. In order for output_registers to function, it needs
|
||||
the starting bit offset of the register space, which is based off of
|
||||
base_offset_register segbit definition.
|
||||
|
||||
Other features generated in fuzzing are passed through.
|
||||
|
||||
"""
|
||||
base_offset_register = 'CMT_UPPER_T.PLLE2.CLKOUT5_DIVIDE[1]'
|
||||
|
||||
bit_offset = None
|
||||
in_use = None
|
||||
with open(seg_in, 'r') as f:
|
||||
for l in f:
|
||||
if l.startswith(base_offset_register):
|
||||
parts = l.split()
|
||||
assert len(parts) == 2
|
||||
assert parts[0] == base_offset_register
|
||||
frame_offset, bit_index = map(int, parts[1].split('_'))
|
||||
|
||||
assert frame_offset == 28
|
||||
assert bit_index > 3
|
||||
bit_offset = bit_index - 3 - 16 * 3
|
||||
|
||||
continue
|
||||
|
||||
if 'IN_USE' in l:
|
||||
assert in_use is None
|
||||
in_use = l.strip()
|
||||
continue
|
||||
|
||||
parts = l.split()
|
||||
feature_parts = parts[0].split('.')
|
||||
|
||||
if len(feature_parts) < 3:
|
||||
print(l.strip())
|
||||
continue
|
||||
|
||||
if feature_parts[2] == 'BANDWIDTH':
|
||||
continue
|
||||
|
||||
if '[' not in feature_parts[2]:
|
||||
print(l.strip())
|
||||
continue
|
||||
|
||||
base_feature = feature_parts[2].split('[')
|
||||
|
||||
if base_feature[0] in [
|
||||
'CLKOUT0_DIVIDE',
|
||||
'CLKOUT1_DIVIDE',
|
||||
'CLKOUT2_DIVIDE',
|
||||
'CLKOUT3_DIVIDE',
|
||||
'CLKOUT4_DIVIDE',
|
||||
'CLKOUT5_DIVIDE',
|
||||
'DIVCLK_DIVIDE',
|
||||
'CLKFBOUT_MULT',
|
||||
'CLKOUT0_DUTY_CYCLE',
|
||||
]:
|
||||
# These features are PLL registers, so ignore the base
|
||||
continue
|
||||
|
||||
print(l.strip())
|
||||
|
||||
assert bit_offset is not None
|
||||
assert in_use is not None
|
||||
return bit_offset, in_use
|
||||
|
||||
|
||||
def output_registers(bit_offset, in_use):
|
||||
""" Output segbits for the known PLL register space.
|
||||
|
||||
The first bit offset in the register space is required to generate this
|
||||
output.
|
||||
|
||||
"""
|
||||
reg = RegisterAddress(frame_offsets=[28, 29], bit_offset=bit_offset)
|
||||
|
||||
for idx, register in enumerate(REGISTER_MAP):
|
||||
if register is None:
|
||||
for _ in range(16):
|
||||
reg.next_bit(used=False)
|
||||
continue
|
||||
|
||||
layout, register_name = register
|
||||
|
||||
layout_bits = REGISTER_LAYOUT[layout]
|
||||
|
||||
simple_layout = len(layout_bits[0]) == 2
|
||||
|
||||
if True:
|
||||
bit_count = 0
|
||||
if simple_layout:
|
||||
for field, width in layout_bits:
|
||||
for bit in range(width):
|
||||
bit_count += 1
|
||||
|
||||
if field is None:
|
||||
reg.next_bit(used=False)
|
||||
continue
|
||||
|
||||
print(
|
||||
'CMT_UPPER_T.PLLE2.{}_{}_{}[{}] {}'.format(
|
||||
register_name, layout, field, bit,
|
||||
reg.next_bit()))
|
||||
else:
|
||||
for field, width, start_bit in layout_bits:
|
||||
for bit in range(width):
|
||||
bit_count += 1
|
||||
|
||||
if field is None:
|
||||
reg.next_bit(used=False)
|
||||
continue
|
||||
|
||||
print(
|
||||
'CMT_UPPER_T.PLLE2.{}[{}] {}'.format(
|
||||
field, start_bit + bit, reg.next_bit()))
|
||||
|
||||
assert bit_count == 16
|
||||
else:
|
||||
for bit in range(16):
|
||||
if register_name != layout or layout in ['CLKOUT1', 'CLKOUT2']:
|
||||
print(
|
||||
'CMT_UPPER_T.PLLE2.{}_{}[{}] {}'.format(
|
||||
register_name, layout, bit, reg.next_bit()))
|
||||
else:
|
||||
print(
|
||||
'CMT_UPPER_T.PLLE2.{}[{}] {}'.format(
|
||||
register_name, bit, reg.next_bit()))
|
||||
|
||||
parts = in_use.split()
|
||||
feature = parts[0]
|
||||
bits = [p for p in parts[1:] if p not in reg.bits_used]
|
||||
print('{} {}'.format(feature, ' '.join(bits)))
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description="")
|
||||
|
||||
parser.add_argument('--seg_in')
|
||||
|
||||
args = parser.parse_args()
|
||||
|
||||
bit_offset, in_use = passthrough_non_register_segbits(args.seg_in)
|
||||
|
||||
output_registers(bit_offset, in_use)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
export FUZDIR=$(shell pwd)
|
||||
PIP_TYPE?=cmt_top
|
||||
PIPLIST_TCL=$(FUZDIR)/cmt_top_upper_t.tcl
|
||||
TODO_RE=".*\.CMT_TOP_[LR]_UPPER_T_PLLE2_CLK_[^_]+_INT"
|
||||
|
||||
ifneq (${XRAY_DATABASE}, zynq7)
|
||||
MAKETODO_FLAGS=--sides "r_upper_t,l_upper_t" --pip-type ${PIP_TYPE} --seg-type cmt_top --re $(TODO_RE)
|
||||
else
|
||||
MAKETODO_FLAGS=--sides "l_upper_t" --pip-type ${PIP_TYPE} --seg-type cmt_top --re $(TODO_RE)
|
||||
endif
|
||||
N = 50
|
||||
|
||||
A_PIPLIST=cmt_top_l_upper_t.txt
|
||||
|
||||
include ../pip_loop.mk
|
||||
|
||||
build/segbits_cmt_top_l_upper_t.rdb: $(SPECIMENS_OK)
|
||||
${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o build/segbits_cmt_top_l_upper_t.rdb \
|
||||
$(shell find build -name segdata_cmt_top_l_upper_t.txt)
|
||||
|
||||
RDBS = build/segbits_cmt_top_l_upper_t.rdb
|
||||
|
||||
ifneq (${XRAY_DATABASE}, zynq7)
|
||||
# Target Zynq7 part has no CMT_TOP_R_UPPER_T
|
||||
build/segbits_cmt_top_r_upper_t.rdb: $(SPECIMENS_OK)
|
||||
${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o build/segbits_cmt_top_r_upper_t.rdb \
|
||||
$(shell find build -name segdata_cmt_top_r_upper_t.txt)
|
||||
|
||||
RDBS += build/segbits_cmt_top_r_upper_t.rdb
|
||||
endif
|
||||
|
||||
database: ${RDBS}
|
||||
${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
|
||||
--seg-fn-in build/segbits_cmt_top_l_upper_t.rdb \
|
||||
--seg-fn-out build/segbits_cmt_top_l_upper_t.db
|
||||
|
||||
ifneq (${XRAY_DATABASE}, zynq7)
|
||||
${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
|
||||
--seg-fn-in build/segbits_cmt_top_r_upper_t.rdb \
|
||||
--seg-fn-out build/segbits_cmt_top_r_upper_t.db
|
||||
endif
|
||||
|
||||
# Keep a copy to track iter progress
|
||||
cp build/segbits_cmt_top_l_upper_t.rdb build/$(ITER)/segbits_cmt_top_l_upper_t.rdb
|
||||
cp build/segbits_cmt_top_l_upper_t.db build/$(ITER)/segbits_cmt_top_l_upper_t.db
|
||||
ifneq (${XRAY_DATABASE}, zynq7)
|
||||
cp build/segbits_cmt_top_r_upper_t.rdb build/$(ITER)/segbits_cmt_top_r_upper_t.rdb
|
||||
cp build/segbits_cmt_top_r_upper_t.db build/$(ITER)/segbits_cmt_top_r_upper_t.db
|
||||
endif
|
||||
|
||||
|
||||
${XRAY_MASKMERGE} build/mask_cmt_top_l_upper_t.db \
|
||||
$(shell find build -name segdata_cmt_top_l_upper_t.txt)
|
||||
ifneq (${XRAY_DATABASE}, zynq7)
|
||||
${XRAY_MASKMERGE} build/mask_cmt_top_r_upper_t.db \
|
||||
$(shell find build -name segdata_cmt_top_r_upper_t.txt)
|
||||
endif
|
||||
|
||||
# Clobber existing .db to eliminate potential conflicts
|
||||
cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db build/database/${XRAY_DATABASE}
|
||||
XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} cmt_top_l_upper_t build/segbits_cmt_top_l_upper_t.db
|
||||
ifneq (${XRAY_DATABASE}, zynq7)
|
||||
XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} cmt_top_r_upper_t build/segbits_cmt_top_r_upper_t.db
|
||||
endif
|
||||
|
||||
pushdb: database
|
||||
${XRAY_MERGEDB} cmt_top_l_upper_t build/segbits_cmt_top_l_upper_t.db
|
||||
ifneq (${XRAY_DATABASE}, zynq7)
|
||||
${XRAY_MERGEDB} cmt_top_r_upper_t build/segbits_cmt_top_r_upper_t.db
|
||||
endif
|
||||
|
||||
.PHONY: database pushdb
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
proc print_tile_pips {tile_type filename} {
|
||||
set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
|
||||
puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
|
||||
set fp [open $filename w]
|
||||
foreach pip [lsort [get_pips -of_objects [get_tiles $tile]]] {
|
||||
set src [get_wires -uphill -of_objects $pip]
|
||||
set dst [get_wires -downhill -of_objects $pip]
|
||||
if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] == 1} {
|
||||
set src_node [get_nodes -of $src]
|
||||
set dst_node [get_nodes -of $dst]
|
||||
|
||||
if { [string first INT_INTERFACE [get_wires -of $src_node]] != -1 } {
|
||||
continue
|
||||
}
|
||||
if { [string first INT_INTERFACE [get_wires -of $dst_node]] != -1 } {
|
||||
continue
|
||||
}
|
||||
}
|
||||
puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
create_project -force -part $::env(XRAY_PART) design design
|
||||
set_property design_mode PinPlanning [current_fileset]
|
||||
open_io_design -name io_1
|
||||
|
||||
print_tile_pips CMT_TOP_L_UPPER_T cmt_top_l_upper_t.txt
|
||||
print_tile_pips CMT_TOP_R_UPPER_T cmt_top_r_upper_t.txt
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
from prjxray.segmaker import Segmaker
|
||||
import os
|
||||
import os.path
|
||||
|
||||
|
||||
def bitfilter(frame, word):
|
||||
if frame <= 1:
|
||||
return False
|
||||
|
||||
return True
|
||||
|
||||
|
||||
def main():
|
||||
segmk = Segmaker("design.bits")
|
||||
|
||||
tiledata = {}
|
||||
pipdata = {}
|
||||
ignpip = set()
|
||||
|
||||
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
|
||||
'cmt_top', 'cmt_top_l_upper_t.txt')) as f:
|
||||
for l in f:
|
||||
tile_type, dst, src = l.strip().split('.')
|
||||
if tile_type not in pipdata:
|
||||
pipdata[tile_type] = []
|
||||
|
||||
pipdata[tile_type].append((src, dst))
|
||||
|
||||
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
|
||||
'cmt_top', 'cmt_top_r_upper_t.txt')) as f:
|
||||
for l in f:
|
||||
tile_type, dst, src = l.strip().split('.')
|
||||
if tile_type not in pipdata:
|
||||
pipdata[tile_type] = []
|
||||
|
||||
pipdata[tile_type].append((src, dst))
|
||||
|
||||
print("Loading tags from design.txt.")
|
||||
with open("design.txt", "r") as f:
|
||||
for line in f:
|
||||
tile, pip, src, dst, pnum, pdir = line.split()
|
||||
|
||||
if not tile.startswith('CMT_TOP'):
|
||||
continue
|
||||
|
||||
if 'UPPER_B' in tile:
|
||||
continue
|
||||
|
||||
pip_prefix, _ = pip.split(".")
|
||||
tile_from_pip, tile_type = pip_prefix.split('/')
|
||||
assert tile == tile_from_pip
|
||||
_, src = src.split("/")
|
||||
_, dst = dst.split("/")
|
||||
pnum = int(pnum)
|
||||
pdir = int(pdir)
|
||||
|
||||
if tile not in tiledata:
|
||||
tiledata[tile] = {
|
||||
"type": tile_type,
|
||||
"pips": set(),
|
||||
"srcs": set(),
|
||||
"dsts": set(),
|
||||
}
|
||||
|
||||
tiledata[tile]["pips"].add((src, dst))
|
||||
tiledata[tile]["srcs"].add(src)
|
||||
tiledata[tile]["dsts"].add(dst)
|
||||
|
||||
if pdir == 0:
|
||||
tiledata[tile]["srcs"].add(dst)
|
||||
tiledata[tile]["dsts"].add(src)
|
||||
|
||||
if dst.startswith('CMT_TOP_R_UPPER_T_CLK') or \
|
||||
dst.startswith('CMT_TOP_L_UPPER_T_CLK'):
|
||||
ignpip.add((src, dst))
|
||||
|
||||
for tile, pips_srcs_dsts in tiledata.items():
|
||||
tile_type = pips_srcs_dsts["type"]
|
||||
pips = pips_srcs_dsts["pips"]
|
||||
|
||||
for src, dst in pipdata[tile_type]:
|
||||
if (src, dst) in ignpip:
|
||||
pass
|
||||
elif (src, dst) in pips:
|
||||
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
|
||||
elif (src, dst) not in tiledata[tile]["pips"]:
|
||||
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
|
||||
|
||||
internal_feedback = False
|
||||
for src, dst in [
|
||||
('CMT_TOP_L_CLKFBOUT2IN', 'CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN'),
|
||||
('CMT_TOP_R_CLKFBOUT2IN', 'CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN'),
|
||||
]:
|
||||
if (src, dst) in pips:
|
||||
internal_feedback = True
|
||||
|
||||
segmk.add_tile_tag(tile, "EXTERNAL_FEEDBACK", not internal_feedback)
|
||||
|
||||
segmk.compile(bitfilter=bitfilter)
|
||||
segmk.write()
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
source "$::env(XRAY_DIR)/utils/utils.tcl"
|
||||
|
||||
proc write_pip_txtdata {filename} {
|
||||
puts "FUZ([pwd]): Writing $filename."
|
||||
set fp [open $filename w]
|
||||
set nets [get_nets -hierarchical]
|
||||
set nnets [llength $nets]
|
||||
set neti 0
|
||||
foreach net $nets {
|
||||
incr neti
|
||||
if {($neti % 100) == 0 } {
|
||||
puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)"
|
||||
}
|
||||
foreach pip [get_pips -of_objects $net] {
|
||||
set tile [get_tiles -of_objects $pip]
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
proc run {} {
|
||||
create_project -force -part $::env(XRAY_PART) design design
|
||||
read_verilog top.v
|
||||
synth_design -top top
|
||||
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
|
||||
|
||||
# Disable MMCM frequency etc sanity checks
|
||||
set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-126}]
|
||||
# PLL
|
||||
set_property IS_ENABLED 0 [get_drc_checks {PDRC-43}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {AVAL-78}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {AVAL-81}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {PDRC-38}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-13}]
|
||||
|
||||
place_design
|
||||
route_design
|
||||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
write_pip_txtdata design.txt
|
||||
}
|
||||
|
||||
run
|
||||
|
|
@ -0,0 +1,242 @@
|
|||
""" """
|
||||
import os
|
||||
import random
|
||||
random.seed(int(os.getenv("SEED"), 16))
|
||||
from prjxray import util
|
||||
from prjxray.db import Database
|
||||
|
||||
|
||||
def find_phasers_for_pll(grid, loc):
|
||||
gridinfo = grid.gridinfo_at_loc((loc[0], loc[1] + 13))
|
||||
|
||||
phasers = {
|
||||
'IN': [],
|
||||
'OUT': [],
|
||||
}
|
||||
|
||||
for site_name, site_type in gridinfo.sites.items():
|
||||
if site_type == 'PHASER_IN_PHY':
|
||||
phasers['IN'].append(site_name)
|
||||
elif site_type == 'PHASER_OUT_PHY':
|
||||
phasers['OUT'].append(site_name)
|
||||
|
||||
assert len(phasers['IN']) > 0
|
||||
assert len(phasers['OUT']) > 0
|
||||
|
||||
phasers['IN'].sort()
|
||||
phasers['OUT'].sort()
|
||||
|
||||
return phasers
|
||||
|
||||
|
||||
def gen_sites():
|
||||
db = Database(util.get_db_root())
|
||||
grid = db.grid()
|
||||
for tile_name in sorted(grid.tiles()):
|
||||
loc = grid.loc_of_tilename(tile_name)
|
||||
gridinfo = grid.gridinfo_at_loc(loc)
|
||||
|
||||
for site_name, site_type in gridinfo.sites.items():
|
||||
if site_type in ['PLLE2_ADV']:
|
||||
phasers = find_phasers_for_pll(grid, loc)
|
||||
yield site_name, phasers
|
||||
|
||||
|
||||
def main():
|
||||
print(
|
||||
'''
|
||||
module top();
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 dummy();
|
||||
''')
|
||||
|
||||
bufg_count = 0
|
||||
|
||||
for site, phasers in sorted(gen_sites(), key=lambda x: x[0]):
|
||||
drive_feedback = random.randint(0, 1)
|
||||
clkfbin_src = random.choice(('BUFH', '0', '1', None))
|
||||
|
||||
if drive_feedback:
|
||||
COMPENSATION = "INTERNAL"
|
||||
else:
|
||||
if clkfbin_src in ['0', '1']:
|
||||
COMPENSATION = 'EXTERNAL'
|
||||
else:
|
||||
COMPENSATION = "ZHOLD"
|
||||
|
||||
print(
|
||||
"""
|
||||
wire clkfbin_{site};
|
||||
wire clkin1_{site};
|
||||
wire clkin2_{site};
|
||||
wire clkfbout_mult_{site};
|
||||
wire clkout0_{site};
|
||||
wire clkout1_{site};
|
||||
wire clkout2_{site};
|
||||
wire clkout3_{site};
|
||||
wire clkout4_{site};
|
||||
wire clkout5_{site};
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
PLLE2_ADV #(
|
||||
.COMPENSATION("{COMPENSATION}")
|
||||
) pll_{site} (
|
||||
.CLKFBOUT(clkfbout_mult_{site}),
|
||||
.CLKOUT0(clkout0_{site}),
|
||||
.CLKOUT1(clkout1_{site}),
|
||||
.CLKOUT2(clkout2_{site}),
|
||||
.CLKOUT3(clkout3_{site}),
|
||||
.CLKOUT4(clkout4_{site}),
|
||||
.CLKOUT5(clkout5_{site}),
|
||||
.DRDY(),
|
||||
.LOCKED(),
|
||||
.DO(),
|
||||
.CLKFBIN(clkfbin_{site}),
|
||||
.CLKIN1(clkin1_{site}),
|
||||
.CLKIN2(clkin2_{site}),
|
||||
.CLKINSEL(),
|
||||
.DCLK(),
|
||||
.DEN(),
|
||||
.DWE(),
|
||||
.PWRDWN(),
|
||||
.RST(),
|
||||
.DI(),
|
||||
.DADDR());
|
||||
""".format(site=site, COMPENSATION=COMPENSATION))
|
||||
|
||||
for clkout in range(4, 6):
|
||||
# CLKOUT4 and CLKOUT5 can only drive one signal type
|
||||
if random.randint(0, 1) and bufg_count < 16:
|
||||
bufg_count += 1
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
BUFG (
|
||||
.I(clkout{idx}_{site})
|
||||
);""".format(idx=clkout, site=site))
|
||||
|
||||
any_phaser = False
|
||||
|
||||
for clkout in range(4):
|
||||
# CLKOUT0-CLKOUT3 can drive:
|
||||
# - Global drivers (e.g. BUFG)
|
||||
# - PHASER_[IN|OUT]_[CA|DB]_FREQREFCLK via BB_[0-3]
|
||||
drive_bufg = random.randint(0, 1) and bufg_count < 16
|
||||
drive_phaser = random.randint(0, 1)
|
||||
|
||||
if drive_bufg:
|
||||
bufg_count += 1
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
BUFG (
|
||||
.I(clkout{idx}_{site})
|
||||
);""".format(idx=clkout, site=site))
|
||||
|
||||
if drive_phaser and not any_phaser and False:
|
||||
any_phaser = True
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH, LOC="{phaser_loc}" *)
|
||||
PHASER_OUT phaser_{site}(
|
||||
.FREQREFCLK(clkout{idx}_{site})
|
||||
);""".format(idx=clkout, site=site, phaser_loc=phasers['OUT'][0]))
|
||||
|
||||
drive_bufg = random.randint(0, 1) and bufg_count < 16
|
||||
|
||||
if drive_bufg and clkfbin_src not in ['BUFH', 'BUFR']:
|
||||
bufg_count += 1
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
BUFG (
|
||||
.I(clkfbout_mult_{site})
|
||||
);""".format(site=site))
|
||||
|
||||
if drive_feedback:
|
||||
print(
|
||||
"""
|
||||
assign clkfbin_{site} = clkfbout_mult_{site};
|
||||
""".format(site=site))
|
||||
else:
|
||||
# If CLKFBIN is not using CLKFBOUT feedback, can be connected to:
|
||||
# - BUFHCE/BUFR using dedicated path
|
||||
# - Switch box clock port
|
||||
|
||||
if clkfbin_src is None:
|
||||
pass
|
||||
elif clkfbin_src == 'BUFH':
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
BUFH (
|
||||
.I(clkfbout_mult_{site}),
|
||||
.O(clkfbin_{site})
|
||||
);""".format(site=site))
|
||||
elif clkfbin_src == 'BUFR':
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
BUFR (
|
||||
.I(clkfbout_mult_{site}),
|
||||
.O(clkfbin_{site})
|
||||
);""".format(site=site))
|
||||
elif clkfbin_src == '0':
|
||||
print(
|
||||
"""
|
||||
assign clkfbin_{site} = 0;
|
||||
""".format(site=site))
|
||||
elif clkfbin_src == '1':
|
||||
print(
|
||||
"""
|
||||
assign clkfbin_{site} = 1;
|
||||
""".format(site=site))
|
||||
else:
|
||||
assert False, clkfbin_src
|
||||
|
||||
clkin_is_none = False
|
||||
|
||||
for clkin in range(2):
|
||||
clkin_src = random.choice((
|
||||
'BUFH',
|
||||
'BUFR',
|
||||
'0',
|
||||
'1',
|
||||
None,
|
||||
))
|
||||
if clkin == 1 and clkin_is_none and clkin_src is None:
|
||||
clkin_src = 'BUFH'
|
||||
|
||||
if clkin_src is None:
|
||||
pass
|
||||
elif clkin_src == 'BUFH':
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
BUFH (
|
||||
.O(clkin{idx}_{site})
|
||||
);""".format(idx=clkin + 1, site=site))
|
||||
elif clkin_src == 'BUFR':
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
BUFR (
|
||||
.O(clkin{idx}_{site})
|
||||
);""".format(idx=clkin + 1, site=site))
|
||||
elif clkin_src == '0':
|
||||
print(
|
||||
"""
|
||||
assign clkin{idx}_{site} = 0;
|
||||
""".format(idx=clkin + 1, site=site))
|
||||
elif clkin_src == '1':
|
||||
print(
|
||||
"""
|
||||
assign clkin{idx}_{site} = 1;
|
||||
""".format(idx=clkin + 1, site=site))
|
||||
else:
|
||||
assert False, clkfbin_src
|
||||
|
||||
print("endmodule")
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
|
|
@ -83,6 +83,8 @@ $(eval $(call fuzzer,027-bram36-config,005-tilegrid))
|
|||
$(eval $(call fuzzer,028-fifo-config,005-tilegrid))
|
||||
$(eval $(call fuzzer,029-bram-fifo-config,005-tilegrid))
|
||||
$(eval $(call fuzzer,030-iob,005-tilegrid))
|
||||
$(eval $(call fuzzer,032-cmt-pll,005-tilegrid))
|
||||
$(eval $(call fuzzer,034-cmt-pll-pips,005-tilegrid))
|
||||
$(eval $(call fuzzer,035-iob-ilogic,005-tilegrid))
|
||||
$(eval $(call fuzzer,036-iob-ologic,005-tilegrid))
|
||||
$(eval $(call fuzzer,040-clk-hrow-config,005-tilegrid))
|
||||
|
|
|
|||
|
|
@ -339,6 +339,8 @@ class Segmaker:
|
|||
-LIOB33 => IOB33
|
||||
'''
|
||||
tile_type_norm = re.sub("(_TOP|_BOT|LL|LM)?_[LR]$", "", tile_type)
|
||||
tile_type_norm = re.sub(
|
||||
"_TOP_[LR]_UPPER", "_UPPER", tile_type_norm)
|
||||
|
||||
if tile_type_norm in ['LIOB33', 'RIOB33']:
|
||||
tile_type_norm = 'IOB33'
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import os
|
||||
import os, sys
|
||||
from prjxray import util
|
||||
|
||||
|
||||
|
|
@ -21,9 +21,11 @@ def run(fn_ins, fn_out, strict=False, track_origin=False, verbose=False):
|
|||
if tag in tags:
|
||||
orig_bits, orig_line, orig_origin = tags[tag]
|
||||
if orig_bits != bits:
|
||||
print("WARNING: got duplicate tag %s" % (tag, ))
|
||||
print(" Orig line: %s" % orig_line)
|
||||
print(" New line : %s" % line)
|
||||
print(
|
||||
"WARNING: got duplicate tag %s" % (tag, ),
|
||||
file=sys.stderr)
|
||||
print(" Orig line: %s" % orig_line, file=sys.stderr)
|
||||
print(" New line : %s" % line, file=sys.stderr)
|
||||
assert not strict, "strict: got duplicate tag"
|
||||
origin = os.path.basename(os.getcwd())
|
||||
if track_origin and orig_origin != origin:
|
||||
|
|
@ -31,9 +33,11 @@ def run(fn_ins, fn_out, strict=False, track_origin=False, verbose=False):
|
|||
if bits in bitss:
|
||||
orig_tag, orig_line = bitss[bits]
|
||||
if orig_tag != tag:
|
||||
print("WARNING: got duplicate bits %s" % (bits, ))
|
||||
print(" Orig line: %s" % orig_line)
|
||||
print(" New line : %s" % line)
|
||||
print(
|
||||
"WARNING: got duplicate bits %s" % (bits, ),
|
||||
file=sys.stderr)
|
||||
print(" Orig line: %s" % orig_line, file=sys.stderr)
|
||||
print(" New line : %s" % line, file=sys.stderr)
|
||||
assert not strict, "strict: got duplicate bits"
|
||||
|
||||
if track_origin and origin is None:
|
||||
|
|
|
|||
|
|
@ -114,6 +114,12 @@ case "$1" in
|
|||
riob33)
|
||||
sed < "$2" > "$tmp1" -e 's/^IOB33\./RIOB33./' ;;
|
||||
|
||||
cmt_top_r_upper_t)
|
||||
sed < "$2" > "$tmp1" -e 's/^CMT_UPPER_T\./CMT_TOP_R_UPPER_T./' ;;
|
||||
|
||||
cmt_top_l_upper_t)
|
||||
sed < "$2" > "$tmp1" -e 's/^CMT_UPPER_T\./CMT_TOP_L_UPPER_T./' ;;
|
||||
|
||||
mask_*)
|
||||
db=$XRAY_DATABASE_DIR/$XRAY_DATABASE/$1.db
|
||||
ismask=true
|
||||
|
|
|
|||
|
|
@ -20,8 +20,8 @@ def run(fnin, fnout=None, strict=False, verbose=False):
|
|||
if mode != "always":
|
||||
assert not mode, "strict: got ill defined line: %s" % (line, )
|
||||
if tag in tags:
|
||||
print("Original line: %s" % tags[tag])
|
||||
print("New line: %s" % line)
|
||||
print("Original line: %s" % tags[tag], file=sys.stderr)
|
||||
print("New line: %s" % line, file=sys.stderr)
|
||||
assert 0, "strict: got duplicate tag %s" % (tag, )
|
||||
assert bits not in bitss, "strict: got duplicate bits %s: %s %s" % (
|
||||
bits, tag, bitss[bits])
|
||||
|
|
|
|||
Loading…
Reference in New Issue