mirror of
https://github.com/YosysHQ/nextpnr.git
synced 2026-10-06 09:53:22 +02:00
Remove long-unimplemented function and associated dead code
Signed-off-by: gatecat <[email protected]>
This commit is contained in:
@@ -54,8 +54,6 @@ struct Context : Arch, DeterministicRNG
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// provided by router1.cc
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bool checkRoutedDesign() const;
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bool getActualRouteDelay(WireId src_wire, WireId dst_wire, delay_t *delay = nullptr,
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dict<WireId, PipId> *route = nullptr, bool useEstimate = true);
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// --------------------------------------------------------------
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// Dispatch to the Arch API or pseudo-cell API accordingly
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@@ -1485,11 +1485,4 @@ bool Context::checkRoutedDesign() const
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return true;
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}
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bool Context::getActualRouteDelay(WireId src_wire, WireId dst_wire, delay_t *delay, dict<WireId, PipId> *route,
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bool useEstimate)
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{
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// FIXME
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return false;
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}
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NEXTPNR_NAMESPACE_END
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@@ -23,81 +23,6 @@
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NEXTPNR_NAMESPACE_BEGIN
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#define NUM_FUZZ_ROUTES 100000
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void ice40DelayFuzzerMain(Context *ctx)
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{
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std::vector<WireId> srcWires, dstWires;
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for (int i = 0; i < int(ctx->chip_info->wire_data.size()); i++) {
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WireId wire;
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wire.index = i;
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switch (ctx->chip_info->wire_data[i].type) {
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case WireInfoPOD::WIRE_TYPE_LUTFF_OUT:
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srcWires.push_back(wire);
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break;
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case WireInfoPOD::WIRE_TYPE_LUTFF_IN_LUT:
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dstWires.push_back(wire);
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break;
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default:
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break;
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}
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}
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ctx->shuffle(srcWires);
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ctx->shuffle(dstWires);
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int index = 0;
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int cnt = 0;
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while (cnt < NUM_FUZZ_ROUTES) {
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if (index >= int(srcWires.size()) || index >= int(dstWires.size())) {
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index = 0;
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ctx->shuffle(srcWires);
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ctx->shuffle(dstWires);
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}
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WireId src = srcWires[index];
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WireId dst = dstWires[index++];
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dict<WireId, PipId> route;
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#if NUM_FUZZ_ROUTES <= 1000
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if (!ctx->getActualRouteDelay(src, dst, nullptr, &route, false))
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continue;
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#else
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if (!ctx->getActualRouteDelay(src, dst, nullptr, &route, true))
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continue;
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#endif
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WireId cursor = dst;
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delay_t delay = 0;
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while (1) {
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delay += ctx->getWireDelay(cursor).maxDelay();
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printf("%s %d %d %s %s %d %d\n", cursor == dst ? "dst" : "src",
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int(ctx->chip_info->wire_data[cursor.index].x), int(ctx->chip_info->wire_data[cursor.index].y),
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ctx->getWireType(cursor).c_str(ctx), ctx->nameOfWire(cursor), int(delay),
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int(ctx->estimateDelay(cursor, dst)));
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if (cursor == src)
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break;
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PipId pip = route.at(cursor);
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delay += ctx->getPipDelay(pip).maxDelay();
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cursor = ctx->getPipSrcWire(pip);
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}
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cnt++;
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if (cnt % 100 == 0)
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fprintf(stderr, "Fuzzed %d arcs.\n", cnt);
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}
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}
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namespace {
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struct model_params_t
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@@ -81,7 +81,6 @@ po::options_description Ice40CommandHandler::getArchOptions()
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specific.add_options()("no-promote-globals", "disable all global promotion");
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specific.add_options()("no-promote-ce", "disable promotion of 'ce' globals");
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specific.add_options()("opt-timing", "run post-placement timing optimisation pass (experimental)");
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specific.add_options()("tmfuzz", "run path delay estimate fuzzer");
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specific.add_options()("pcf-allow-unconstrained", "don't require PCF to constrain all IO");
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return specific;
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@@ -117,9 +116,6 @@ void Ice40CommandHandler::customBitstream(Context *ctx)
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void Ice40CommandHandler::setupArchContext(Context *ctx)
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{
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if (vm.count("tmfuzz"))
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ice40DelayFuzzerMain(ctx);
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if (vm.count("read")) {
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std::string filename = vm["read"].as<std::string>();
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auto f = open_ifstream_and_log_error(filename, "ASC file");
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