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Gowin. GW5AT-60B clocks.

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This chip features an unusual layout in general, and a unique clock-wire
interconnection system in particular.  Most aspects can be handled using
specific logic blocks or at the `gowin_pack` stage; however, the
scenario where multiple switched connections exist between the clock
spines and the clock source must be addressed here.

In the global clock router, we allow a connection between the wire
serving as the clock source and any clock wire, regardless of how many
wires lie between that source and the spine.

Signed-off-by: YRabbit <[email protected]>
This commit is contained in:
YRabbit
2026-10-02 09:11:28 +02:00
committed by myrtle
parent f745549624
commit e2fe86b3ce
2 changed files with 6 additions and 4 deletions
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himbaechel/uarch/gowin/cst.cc
+1 -1
View File
@@ -168,7 +168,7 @@ struct GowinCstReader
}
adc_ios.insert(ctx->idf("%d/X%dY%d", std::stoi(match[1]), col - 1, row - 1));
} break;
case clock: { // CLOCK name BUFG|S=#
case clock: { // CLOCK_LOC name BUFG|S=#
std::string which_clock = match[2];
std::string lw = match[4];
int lw_idx = -1;
himbaechel/uarch/gowin/globals.cc
+5 -3
View File
@@ -82,13 +82,15 @@ struct GowinGlobalRouter
bool res;
if (src == src_wire && (src_type == id_PLL_O || (!src_is_outpin))) {
bool dst_is_spine = dst_name.str(ctx).rfind("SPINE", 0) == 0;
res = src_valid && (dst_is_spine || dst_type == id_PLL_O);
bool src_is_gate = gwu.wire_is_clock_gate(src);
res = (src_valid && (dst_is_spine || dst_type == id_PLL_O)) || (src_is_gate && dst_valid);
} else {
res = (src_valid && dst_valid) || (src_valid && is_local(dst_type)) || (is_local(src_type) && dst_valid);
}
if (ctx->debug && false /*&& res*/) {
log_info("%s <- %s [%s <- %s]\n", ctx->nameOfWire(ctx->getPipDstWire(pip)),
ctx->nameOfWire(ctx->getPipSrcWire(pip)), dst_type.c_str(ctx), src_type.c_str(ctx));
log_info("%s <- %s [%s <- %s] src:%s\n", ctx->nameOfWire(ctx->getPipDstWire(pip)),
ctx->nameOfWire(ctx->getPipSrcWire(pip)), dst_type.c_str(ctx), src_type.c_str(ctx),
ctx->nameOfWire(src_wire));
log_info(" res:%d, src_valid:%d, dst_valid:%d, src local:%d, dst local:%d, dst gate:%d\n", res, src_valid,
dst_valid, is_local(src_type), is_local(dst_type), gwu.wire_is_clock_gate(dst));
}