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4904 Commits

Author SHA1 Message Date
Lofty 77311a8cdd Clean up MsbRoutingCell 2025-07-01 11:48:48 +01:00
Lofty 012f78c9e3 Clean up CarryGenCell config 2025-07-01 11:06:28 +01:00
Lofty 9fa4bb8ba2 Remove A passthrough inversion option 2025-07-01 09:57:43 +01:00
Lofty b2d8123b17 fixed some undefined behaviour 2025-06-30 10:22:50 +01:00
Lofty 2d81d34991 current progress (013 seems to work?) 2025-06-30 10:22:50 +01:00
Lofty bdf235721e current progress 2025-06-30 10:22:50 +01:00
Lofty 7122a98c13 refactor multiplier structure into uarch 2025-06-30 10:22:50 +01:00
Lofty 4fd43f8928 current progress (passes 2x2\!) 2025-06-30 10:22:50 +01:00
Lofty f4179e0330 current progress 2025-06-30 10:22:50 +01:00
Lofty 091bc57eab current progress 2025-06-30 10:22:50 +01:00
Lofty 35c6fab0d0 current progress 2025-06-30 10:22:50 +01:00
Lofty fcecdb9397 current progress 2025-06-30 10:22:50 +01:00
Lofty 1ac1b67f7f current progress 2025-06-30 10:22:50 +01:00
Lofty 6a1051302f current progress 2025-06-30 10:22:50 +01:00
Lofty e66e6f4c11 wip multiplier support 2025-06-30 10:22:50 +01:00
YRabbit 39f020b033
Gowin. Unbreak the segment routing. (#1508) 
Use loop enumeration of PIPs instead of direct name construction for the
upper and lower ends of the segment wire.

Also do not allow clock wires for segments.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-06-30 10:14:21 +02:00
Lofty e642e21f9b
himbaechel: output normalised wire in getWireByName (#1506) 2025-06-25 18:46:19 +02:00
gatecat 9ade2d1877 himbaechel: Add Python binding for get_tile_wire_range 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-06-25 18:37:17 +02:00
gatecat 1cd1e4a8d9 xilinx: Fix packing of weird mux trees 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-06-25 12:38:11 +02:00
gatecat 23cf1d3b92 docs: Fix outdated content in generic.md 
Fixes #1263

Signed-off-by: gatecat <gatecat@ds0.me>
 2025-06-25 12:02:27 +02:00
gatecat ff695f26d5 sdc: Fix EOF handling during string parse 
Fixes #1490

Signed-off-by: gatecat <gatecat@ds0.me>
 2025-06-25 11:58:11 +02:00
gatecat f74aee7047 gowin: Remove logspam during build 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-06-25 11:49:45 +02:00
gatecat a77eb9e941 ice40: Fix accidental division by DIVR in 2_PAD mode 
Fixes #1500

Signed-off-by: gatecat <gatecat@ds0.me>
 2025-06-25 11:44:16 +02:00
Frans Skarman 0c86a218fd
Add sources to detailed timing report (#1502) 2025-06-25 11:39:25 +02:00
YRabbit 66f051d853
Gowin. BUGFIX. Stupid == vs = (#1504) 
he good thing is that these cases are very few.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-06-24 13:24:10 +02:00
Miodrag Milanovic 311a1a711d gatemate: do not use special serdes pins for auto placement 2025-06-18 09:56:54 +02:00
Miodrag Milanovic f58dd2d719 clangformat 2025-06-18 09:12:14 +02:00
Miodrag Milanović 7318d6a8ba
gatemate: Multi die support and primitives model improvement (#1501) 
* SER_CLK support

* Update constids

* wip

* CLK_FEEDBACK

* Handle SER_CLK and SER_CLK_N

* clangformat

* Cleanup

* Use _ as separator for PLL CFGs

* Remove unused clocking cells

* Do not use same name for IO models

* Fix IDDR merge

* Cleanup

* Properly handle user global signals

* Move signal inversion in bitstream creation

* Start adding multi die support

* Display die location for pins used

* Do not use constant s as locations

* Cleanup SB_DRIVE handling

* Use DDR locations from chip database

* Place only in prefered die for now

* Set D2D

* Fixed typos
 2025-06-18 08:32:57 +02:00
Lofty 5275c14ac0
gatemate: include DDR route-throughs in clock router (#1499) 
* route_clock: small cleanup

* gatemate: include DDR route-throughs for clock router
 2025-06-10 18:00:15 +02:00
YRabbit 000faab213
Gowin. BUGFIX. Fix routing of the FF inputs. (#1498) 
A segment router replaces the source-to-sink connection by
general-purpose PIPs with bus-branch segment network connections.

The problem arises when the source is connected to the sinks directly
without switching as in the case of LUT->DFF, such wires should be left
as is, which is what this PR does.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-06-10 07:54:20 +02:00
Miodrag Milanovic fd3b4d36e7 gatemate: fix CLK inversion 2025-06-04 18:53:58 +02:00
Miodrag Milanovic bac5a9145f gatemate: memory clock signal handling 2025-05-29 13:26:35 +02:00
Miodrag Milanovic 9994fdb393 gatemate: make sure to use latest chipdb 2025-05-27 15:37:25 +02:00
Miodrag Milanović 12f597dcd1
gatemate: propagate clock constraints on input ports (#1497) 2025-05-26 11:16:45 +02:00
Miodrag Milanovic e7f52d1b6b gatemate: enable only used banks, including CFG one 2025-05-24 14:56:07 +02:00
Lofty 9cfc7ee263
gatemate: improve estimateDelay (#1494) 2025-05-22 09:15:12 +02:00
Lofty 06d3408ba4
Use clock router even for non-global clocks (#1493) 2025-05-21 16:17:20 +02:00
gatecat 226a2dfdb4 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-05-20 13:19:52 +02:00
Miodrag Milanovic 77a6df131c gatemate: use BUFG input in case it is routed to PLL 2025-05-20 09:30:27 +02:00
Lofty 520616248e
Reserve all CPE control signals in clock router (#1492) 2025-05-19 14:55:12 +02:00
Lofty 2b33800d77
Reserve EN and SR wires in GateMate clock router (#1491) 2025-05-19 12:36:16 +02:00
Miodrag Milanović b0c29aa634
gatemate: PLL priority for BUFG (#1488) 2025-05-19 09:55:39 +02:00
Miodrag Milanović 6c3956c3b9
gatemate: BRAM cascade mode support (#1487) 
* BRAM cascade mode support

* Removed unused connections

* Exclusive connection
 2025-05-19 09:55:11 +02:00
Miodrag Milanovic 23a99989d1 gatemate: invert output enable for io buffer 2025-05-19 09:47:17 +02:00
Lofty 27594f904f
Reserve sinks in GateMate clock router (#1486) 2025-05-15 16:53:06 +02:00
Miodrag Milanović 0bbe031a4b
set CXX standard for bba and remove boost lib (#1485) 2025-05-14 13:42:47 +02:00
William D. Jones b127fa9c11 bba: fix `#embed` on Windows. 2025-05-14 05:38:30 +01:00
Catherine 7a821623f0 bba: use `std::filesystem` instead of `boost::filesystem`. 
Also, convert paths to UTF-8 for Windows builds. See #1479.
 2025-05-14 05:38:30 +01:00
Lofty 46fbe7c6d7
GateMate clock router (#1483) 
* gatemate: clock router

Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>

* Re-add clock router pip binding

* Refactoring

* Require globals to use a BUFG

* Fix misunderstanding of GPIO/RAM clocking

* Add plane info to chipdb

* Force clock routing along a specific plane

* Remove overly-limiting condition

* Move clock router into its own file

* Clock router based on delay

* Refine clock router conditions

* More detailed clock routing output

* Clean up debug messages

* clangformat

---------

Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
 2025-05-13 16:07:47 +02:00
YRabbit b1c147083d Gowin. Fill in delay values in HCLK. 
Fill in the delays for PIP classes related to HCLK and IODELAY.  Also:

 - if clock routing fails, we try to use the next fastest mechanism - segment networks;

 - fixing harmless typos.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-05-13 12:11:36 +01:00