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gatemate: memory clock signal handling

This commit is contained in:
Miodrag Milanovic 2025-05-29 13:26:35 +02:00
parent 9994fdb393
commit bac5a9145f
1 changed files with 16 additions and 4 deletions
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20
himbaechel/uarch/gatemate/pack_bram.cc
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@ -55,19 +55,31 @@ uint8_t GateMatePacker::ram_clk_signal(CellInfo *cell, IdString port)
switch (index) {
case 0:
val = 0b00100011;
cell->renamePort(port, id_CLOCK1);
if (!cell->getPort(id_CLOCK1))
cell->renamePort(port, id_CLOCK1);
else
cell->disconnectPort(port);
break;
case 1:
val = 0b00110011;
cell->renamePort(port, id_CLOCK2);
if (!cell->getPort(id_CLOCK2))
cell->renamePort(port, id_CLOCK2);
else
cell->disconnectPort(port);
break;
case 2:
val = 0b00000011;
cell->renamePort(port, id_CLOCK3);
if (!cell->getPort(id_CLOCK3))
cell->renamePort(port, id_CLOCK3);
else
cell->disconnectPort(port);
break;
case 3:
val = 0b00010011;
cell->renamePort(port, id_CLOCK4);
if (!cell->getPort(id_CLOCK4))
cell->renamePort(port, id_CLOCK4);
else
cell->disconnectPort(port);
break;
}
return val;