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gatemate: fix CLK inversion

This commit is contained in:
Miodrag Milanovic 2025-06-04 18:53:58 +02:00
parent bac5a9145f
commit fd3b4d36e7
1 changed files with 1 additions and 2 deletions
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3
himbaechel/uarch/gatemate/pack_io.cc
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@ -463,7 +463,6 @@ void GateMatePacker::pack_io_sel()
ci.params[id_USE_DDR] = Property(Property::State::S1);
packed_cells.emplace(oddr->name);
ci.disconnectPort(id_A);
// TODO: check mapping
oddr->movePortTo(id_D0, &ci, id_OUT2);
oddr->movePortTo(id_D1, &ci, id_OUT1);
const auto &pad = ctx->get_package_pin(ctx->id(loc));
@ -482,7 +481,7 @@ void GateMatePacker::pack_io_sel()
}
use_custom_clock = set_out_clk(oddr, &ci);
bool invert = bool_or_default(oddr->params, id_CLK_INV, 0);
if (invert) {
if (!invert) {
ci.params[id_INV_OUT1_CLOCK] = Property(Property::State::S1);
} else {
ci.params[id_INV_OUT2_CLOCK] = Property(Property::State::S1);