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gatemate: make sure to use latest chipdb

This commit is contained in:
Miodrag Milanovic 2025-05-27 15:37:25 +02:00
parent 12f597dcd1
commit 9994fdb393
2 changed files with 27 additions and 0 deletions
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23
himbaechel/uarch/gatemate/gen/arch_gen.py
View File

@ -140,6 +140,8 @@ def set_timings(ch):
dff.add_setup_hold("CLK", "IN4", ClockEdge.RISING, TimingValue(60), TimingValue(50))
dff.add_clock_out("CLK", "OUT", ClockEdge.RISING, TimingValue(60))
EXPECTED_VERSION = 1.1
def main():
# Range needs to be +1, but we are adding +2 more to coordinates, since
# they are starting from -2 instead of zero required for nextpnr
@ -148,6 +150,27 @@ def main():
# Init constant ids
ch.strs.read_constids(path.join(path.dirname(__file__), "..", "constids.inc"))
ch.read_gfxids(path.join(path.dirname(__file__), "..", "gfxids.inc"))
try:
if chip.get_version()!=EXPECTED_VERSION:
print("==============================================================================")
print(f"ERROR: Expected v{EXPECTED_VERSION} and current v{chip.get_version()} chip database mismatch")
print(" Please update prjpeppercorn and/or nextpnr")
print("==============================================================================")
os._exit(-1)
except AttributeError:
print("==============================================================================")
print("ERROR: Unable to determine prjpepercorn version")
print(" Please update prjpeppercorn and/or nextpnr")
print("==============================================================================")
os._exit(-1)
if not chip.check_dly_available():
print("==============================================================================")
print("ERROR: Delay files not, found")
print(" Run delay.sh in prjpeppercorn to download needed files")
print("==============================================================================")
os._exit(-1)
for type_name in sorted(die.get_tile_type_list()):
tt = ch.create_tile_type(type_name)

4
himbaechel/uarch/gatemate/pack_bram.cc
View File

@ -55,15 +55,19 @@ uint8_t GateMatePacker::ram_clk_signal(CellInfo *cell, IdString port)
switch (index) {
case 0:
val = 0b00100011;
cell->renamePort(port, id_CLOCK1);
break;
case 1:
val = 0b00110011;
cell->renamePort(port, id_CLOCK2);
break;
case 2:
val = 0b00000011;
cell->renamePort(port, id_CLOCK3);
break;
case 3:
val = 0b00010011;
cell->renamePort(port, id_CLOCK4);
break;
}
return val;