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Lofty
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@ -17,8 +17,10 @@
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*
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*/
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#include "idstring.h"
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#include "nextpnr_assertions.h"
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#include "nextpnr_namespaces.h"
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#include "nextpnr_types.h"
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#include "pack.h"
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#include "property.h"
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#include "util.h"
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@ -28,32 +30,232 @@
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NEXTPNR_NAMESPACE_BEGIN
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// Propagate A0 through OUT1 and A1 through OUT2
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//
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// TODO: do we need this cell?
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struct APassThroughCell
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{
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APassThroughCell(CellInfo *lower, CellInfo *upper, IdString name) : lower{lower}, upper{upper}
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{
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lower->cluster = name;
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lower->constr_abs_z = false;
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lower->params[id_INIT_L00] = Property(0b0101, 4); // IN1
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lower->params[id_INIT_L01] = Property(0b0000, 4); // 0 (unused)
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lower->params[id_INIT_L10] = Property(0b0101, 4); // L00 -> OUT2
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upper->cluster = name;
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upper->constr_abs_z = false;
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upper->params[id_INIT_L02] = Property(0b0101, 4); // IN5
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upper->params[id_INIT_L03] = Property(0b0000, 4); // 0 (unused)
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upper->params[id_INIT_L11] = Property(0b0101, 4); // L02
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upper->params[id_INIT_L20] = Property(0b0101, 4); // L11 -> OUT1
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}
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PortRef a0() const { return PortRef{upper, id_IN1}; }
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PortRef a1() const { return PortRef{lower, id_IN1}; }
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CellInfo *upper;
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CellInfo *lower;
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};
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// Propagate B0 through POUTY1 and B1 through COUTY1
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//
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// CITE: CPE_ges_Bin.pdf
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// TODO: is it worth trying to unify this with APassThroughCell?
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struct BPassThroughCell
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{
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BPassThroughCell(CellInfo *lower, CellInfo *upper, IdString name) : lower{lower}, upper{upper}
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{
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lower->cluster = name;
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lower->constr_abs_z = false;
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lower->params[id_INIT_L00] = Property(0b0101, 4); // IN1
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lower->params[id_INIT_L01] = Property(0b0000, 4); // 0 (unused)
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lower->params[id_INIT_L10] = Property(0b0101, 4); // L00 -> OUT2
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upper->cluster = name;
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upper->constr_abs_z = false;
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upper->params[id_INIT_L02] = Property(0b0101, 4); // IN5
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upper->params[id_INIT_L03] = Property(0b0000, 4); // 0 (unused)
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upper->params[id_INIT_L11] = Property(0b0101, 4); // L02
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upper->params[id_INIT_L20] = Property(0b0101, 4); // L11 -> OUT1
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upper->params[id_C_SEL_C] = Property(0, 1); // OUT2 -> CY1_VAL
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upper->params[id_C_SEL_P] = Property(0, 1); // OUT1 -> PY_VAL
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upper->params[id_C_SELY1] = Property(0, 1); // OUT1 -> PY1_VAL; OUT2 -> CY1_VAL
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upper->params[id_C_CY1_I] = Property(1, 1); // CY1_VAL -> COUTY1
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upper->params[id_C_PY1_I] = Property(1, 1); // PY1_VAL -> POUTY1
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}
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PortRef b0() const { return PortRef{upper, id_IN1}; }
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PortRef b1() const { return PortRef{lower, id_IN1}; }
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CellInfo *upper;
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CellInfo *lower;
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};
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// Multiply two bits of A with two bits of B.
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//
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// CITE: CPE_MULT.pdf
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struct MultCell
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{
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MultCell(CellInfo *lower, CellInfo *upper, IdString name) : lower{lower}, upper{upper}
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{
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lower->cluster = name;
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lower->constr_abs_z = false;
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lower->params[id_INIT_L00] = Property(0b1000, 4); // AND
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lower->params[id_INIT_L01] = Property(0b1100, 4); // CINX
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lower->params[id_INIT_L10] = Property(0b0110, 4); // XOR
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upper->cluster = name;
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upper->constr_abs_z = false;
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upper->params[id_INIT_L02] = Property(0b1000, 4); // AND
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upper->params[id_INIT_L03] = Property(0b1100, 4); // PINX
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upper->params[id_INIT_L11] = Property(0b0110, 4); // XOR
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upper->params[id_INIT_L20] = Property(0b1100, 4); // L11
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upper->params[id_C_FUNCTION] = Property(C_MULT, 3);
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upper->params[id_C_I1] = Property(1, 1); // PINY1 for L00
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upper->params[id_C_I2] = Property(1, 1); // CINX for L01
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upper->params[id_C_I3] = Property(1, 1); // PINY1 for L02
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upper->params[id_C_I4] = Property(1, 1); // PINX for L03
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}
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CellInfo *upper;
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CellInfo *lower;
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};
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// This seems to prepare B bits for multiplication.
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//
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// CITE: CPE_MULTFab.pdf
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struct MultfabCell
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{
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MultfabCell(CellInfo *lower, CellInfo *upper, IdString name, bool is_even_x) : lower{lower}, upper{upper}
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{
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lower->cluster = name;
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lower->constr_abs_z = false;
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lower->params[id_INIT_L00] = Property(0b1100, 4); // PINY1
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lower->params[id_INIT_L01] = Property(0b1100, 4); // CINX
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lower->params[id_INIT_L10] = Property(0b0110, 4); // XOR
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upper->cluster = name;
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upper->constr_abs_z = false;
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upper->params[id_INIT_L02] = Property(0b1100, 4); // PINY1
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upper->params[id_INIT_L03] = Property(0b0000, 4); // 0 (unused)
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upper->params[id_INIT_L11] = Property(0b0101, 4); // L02
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if (is_even_x) {
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// TODO: the diagrams suggest that AND has L10 inverted? need to check.
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upper->params[id_INIT_L20] = Property(0b1000, 4); // L10 AND L11 -> OUT1
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} else {
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upper->params[id_INIT_L20] = Property(0b1110, 4); // L10 OR L11 -> OUT1
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}
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upper->params[id_INIT_L30] = Property(0b1100, 4); // L10 -> COMP_OUT
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upper->params[id_C_FUNCTION] = Property(C_MULT, 3);
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upper->params[id_C_I1] = Property(1, 1); // PINY1 for L00
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upper->params[id_C_I2] = Property(1, 1); // CINX for L01
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upper->params[id_C_I3] = Property(1, 1); // PINY1 for L02
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upper->params[id_C_CX_I] = Property(1, 1); // CX_VAL -> COUTX
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upper->params[id_C_CY1_I] = Property(1, 1); // CY1_VAL -> COUTY1
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upper->params[id_C_PY1_I] = Property(1, 1); // PY1_VAL -> POUTY1
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upper->params[id_C_SELX] = Property(1, 1); // inverted CINY2 -> CX_VAL
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upper->params[id_C_SELY1] = Property(0, 1); // COMP_OUT -> CY1_VAL; OUT1 -> PY1_VAL
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upper->params[id_C_Y12] = Property(1, 1); // inverted CINY2 -> CX_VAL
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upper->params[id_C_SEL_C] = Property(1, 1); // inverted CINY2 -> CX_VAL; COMP_OUT -> CY1_VAL
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upper->params[id_C_SEL_P] = Property(0, 1); // OUT1 -> PY1_VAL
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}
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CellInfo *upper;
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CellInfo *lower;
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};
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// CITE: CPE_ges_carry-gen.pdf
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struct CarryGenCell
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{
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CarryGenCell(CellInfo *lower, CellInfo *upper, IdString name, bool is_even_x) : lower{lower}, upper{upper}
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{
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lower->cluster = name;
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lower->constr_abs_z = false;
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lower->params[id_INIT_L00] = Property(0b0000, 4); // 0 (unused)
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lower->params[id_INIT_L01] = Property(0b1100, 4); // CINX
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lower->params[id_INIT_L10] = Property(0b1100, 4); // L01 -> OUT2
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upper->cluster = name;
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upper->constr_abs_z = false;
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upper->params[id_INIT_L02] = Property(0b1100, 4); // PINY1
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upper->params[id_INIT_L03] = Property(0b0000, 4); // 0 (unused)
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if (is_even_x) {
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upper->params[id_INIT_L11] = Property(0b1000, 4); // AND
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upper->params[id_INIT_L20] = Property(0b1000, 4); // AND
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} else {
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upper->params[id_INIT_L11] = Property(0b1110, 4); // OR
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upper->params[id_INIT_L20] = Property(0b1110, 4); // OR
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}
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upper->params[id_INIT_L30] = Property(0b0101, 4); // OUT1 -> COMP_OUT
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upper->params[id_C_I2] = Property(1, 1); // CINX for L01
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upper->params[id_C_I3] = Property(1, 1); // PINY1 for L02
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// TODO: how do I get B1 through CIN??
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upper->params[id_C_PY1_I] = Property(0, 1); // PINY1 -> POUTY1
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upper->params[id_C_CY1_I] = Property(0, 1); // CINY1 -> COUTY1
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upper->params[id_C_CY2_I] = Property(1, 1); // CY2_VAL -> COUTY2
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upper->params[id_C_SEL_C] = Property(1, 1); // COMP_OUT -> CY2_VAL
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upper->params[id_C_SELY2] = Property(0, 1); // COMP_OUT -> CY2_VAL
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}
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CellInfo *upper;
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CellInfo *lower;
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};
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// CITE: CPE_ges_f-routing-1.pdf
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// TODO:
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struct FRoutingCell
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{
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CellInfo *upper;
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CellInfo *lower;
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};
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// CITE: CPE_ges_MSB-routing.pdf
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struct MsbRoutingCell
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{
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CellInfo *upper;
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CellInfo *lower;
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};
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struct MultiplierColumn
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{
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MsbRoutingCell msb_route;
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std::vector<MultCell> mults;
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MultfabCell multfab;
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FRoutingCell f_route;
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BPassThroughCell b_passthru;
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};
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// A GateMate multiplier is made up of columns of 2x2 multipliers.
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struct Multiplier
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{
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std::vector<APassThroughCell> a_passthrus;
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std::vector<MultiplierColumn> cols;
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};
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void GateMatePacker::pack_mult()
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{
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auto create_mult_cell = [&](IdString name) {
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// instantiate a full CPE by creating two halves.
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auto* cpe_l = create_cell_ptr(id_CPE_HALF_L, ctx->idf("%s$lower", name.c_str(ctx)));
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cpe_l->cluster = name;
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cpe_l->constr_abs_z = false;
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cpe_l->params[id_INIT_L00] = Property(0b1000, 4); // AND
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cpe_l->params[id_INIT_L01] = Property(0b1000, 4); // AND
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cpe_l->params[id_INIT_L10] = Property(0b0110, 4); // XOR
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auto *lower = create_cell_ptr(id_CPE_HALF_L, ctx->idf("%s$lower", name.c_str(ctx)));
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auto *upper = create_cell_ptr(id_CPE_HALF_U, ctx->idf("%s$upper", name.c_str(ctx)));
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return MultCell{lower, upper, name};
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};
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auto* cpe_u = create_cell_ptr(id_CPE_HALF_U, ctx->idf("%s$upper", name.c_str(ctx)));
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cpe_u->cluster = name;
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cpe_u->constr_abs_z = false;
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cpe_u->params[id_INIT_L02] = Property(0b1000, 4); // AND
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cpe_u->params[id_INIT_L03] = Property(0b1000, 4); // AND
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cpe_u->params[id_INIT_L11] = Property(0b0110, 4); // XOR
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cpe_u->params[id_INIT_L20] = Property(0b0101, 4); // D1
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cpe_u->params[id_C_FUNCTION] = Property(C_MULT, 3);
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return std::make_pair(cpe_l, cpe_u);
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auto create_multfab_cell = [&](IdString name, bool is_multfa) {
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// instantiate a full CPE by creating two halves.
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auto *lower = create_cell_ptr(id_CPE_HALF_L, ctx->idf("%s$lower", name.c_str(ctx)));
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auto *upper = create_cell_ptr(id_CPE_HALF_U, ctx->idf("%s$upper", name.c_str(ctx)));
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return MultfabCell{lower, upper, name, is_multfa};
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};
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log_info("Packing multipliers...\n");
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auto mults = std::vector<CellInfo*>{};
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auto mults = std::vector<CellInfo *>{};
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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@ -61,18 +263,17 @@ void GateMatePacker::pack_mult()
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mults.push_back(ci);
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}
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for (auto* mult : mults) {
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for (auto *mult : mults) {
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auto a_width = int_or_default(mult->params, id_A_WIDTH);
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auto b_width = int_or_default(mult->params, id_B_WIDTH);
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auto p_width = int_or_default(mult->params, id_P_WIDTH);
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log_info(" Configuring '%s' as a %d * %d = %d multiplier\n", mult->name.c_str(ctx), a_width, b_width, p_width);
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log_info(" Configuring '%s' as a %d * %d = %d multiplier\n", mult->name.c_str(ctx), a_width, b_width,
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p_width);
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NPNR_ASSERT(a_width <= 2);
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NPNR_ASSERT(b_width <= 2);
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auto [mult_l, mult_u] = create_mult_cell(mult->name);
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}
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}
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