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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2025-05-20 13:19:52 +02:00
parent 77a6df131c
commit 226a2dfdb4
15 changed files with 53 additions and 53 deletions
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2
common/kernel/command.cc
View File

@ -30,11 +30,11 @@
#include <boost/algorithm/string/join.hpp>
#include <boost/filesystem/path.hpp>
#include <boost/program_options.hpp>
#include <cinttypes>
#include <fstream>
#include <iostream>
#include <random>
#include <set>
#include <cinttypes>
#include "command.h"
#include "design_utils.h"

5
common/kernel/pybindings.cc
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@ -319,10 +319,7 @@ void init_python(const char *executable)
python_sighandler = signal(SIGINT, SIG_DFL);
}
void deinit_python()
{
py::finalize_interpreter();
}
void deinit_python() { py::finalize_interpreter(); }
void execute_python_file(const char *python_file)
{

6
common/route/router2.cc
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@ -1193,7 +1193,8 @@ struct Router2
void write_congestion_by_coordinate_heatmap(std::ostream &out)
{
auto util_by_coord = std::vector<std::vector<int>>(ctx->getGridDimX() + 1, std::vector<int>(ctx->getGridDimY() + 1, 0));
auto util_by_coord =
std::vector<std::vector<int>>(ctx->getGridDimX() + 1, std::vector<int>(ctx->getGridDimY() + 1, 0));
for (auto &wd : flat_wires)
if (wd.curr_cong > 1)
util_by_coord[wd.x][wd.y] += wd.curr_cong;
@ -1484,7 +1485,8 @@ struct Router2
std::string filename(cfg.heatmap + "_congestion_by_coordinate_" + std::to_string(iter) + ".csv");
std::ofstream cong_map(filename);
if (!cong_map)
log_error("Failed to open congestion-by-coordinate heatmap %s for writing.\n", filename.c_str());
log_error("Failed to open congestion-by-coordinate heatmap %s for writing.\n",
filename.c_str());
write_congestion_by_coordinate_heatmap(cong_map);
log_info(" wrote congestion-by-coordinate heatmap to %s.\n", filename.c_str());
}

24
ecp5/pack.cc
View File

@ -2877,28 +2877,28 @@ class Ecp5Packer
vco_freq, ci->name.c_str(ctx));
if (str_or_default(ci->params, id_OUTDIVIDER_MUXA, "DIVA") == "REFCLK")
copy_constraint(ci, id_CLKI, id_CLKOP, 1);
copy_constraint(ci, id_CLKI, id_CLKOP, 1);
else
set_constraint(ci, id_CLKOP,
simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOP_DIV, 1)));
set_constraint(ci, id_CLKOP,
simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOP_DIV, 1)));
if (str_or_default(ci->params, id_OUTDIVIDER_MUXB, "DIVB") == "REFCLK")
copy_constraint(ci, id_CLKI, id_CLKOS, 1);
copy_constraint(ci, id_CLKI, id_CLKOS, 1);
else
set_constraint(ci, id_CLKOS,
simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS_DIV, 1)));
set_constraint(ci, id_CLKOS,
simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS_DIV, 1)));
if (str_or_default(ci->params, id_OUTDIVIDER_MUXC, "DIVC") == "REFCLK")
copy_constraint(ci, id_CLKI, id_CLKOS2, 1);
copy_constraint(ci, id_CLKI, id_CLKOS2, 1);
else
set_constraint(ci, id_CLKOS2,
simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS2_DIV, 1)));
set_constraint(ci, id_CLKOS2,
simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS2_DIV, 1)));
if (str_or_default(ci->params, id_OUTDIVIDER_MUXD, "DIVD") == "REFCLK")
copy_constraint(ci, id_CLKI, id_CLKOS3, 1);
copy_constraint(ci, id_CLKI, id_CLKOS3, 1);
else
set_constraint(ci, id_CLKOS3,
simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1)));
set_constraint(ci, id_CLKOS3,
simple_clk_contraint(vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1)));
} else if (ci->type == id_OSCG) {
int div = int_or_default(ci->params, id_DIV, 128);
set_constraint(ci, id_OSC, simple_clk_contraint(delay_t((1.0e6 / (2.0 * 155)) * div)));

5
frontend/frontend_base.h
View File

@ -539,8 +539,9 @@ template <typename FrontendType> struct GenericFrontend
auto type = impl.get_cell_type(cd);
import_module(submod, name, type, mod_refs.at(type));
// Add current cell attributes to the imported module
impl.foreach_attr( cd, [&](const std::string &name, const Property &value)
{ ctx->hierarchy[submod.path].attrs[ctx->id(name)] = value; } );
impl.foreach_attr(cd, [&](const std::string &name, const Property &value) {
ctx->hierarchy[submod.path].attrs[ctx->id(name)] = value;
});
}
// Import the cells section of a module

3
generic/arch.cc
View File

@ -296,7 +296,8 @@ BelId Arch::getBelByLocation(Loc loc) const
return BelId();
}
const std::vector<BelId> &Arch::getBelsByTile(int x, int y) const {
const std::vector<BelId> &Arch::getBelsByTile(int x, int y) const
{
static const std::vector<BelId> empty_list;
return y < int(bels_by_tile.at(x).size()) ? bels_by_tile.at(x).at(y) : empty_list;
}

2
generic/viaduct/fabulous/fabric_parsing.h
View File

@ -151,7 +151,7 @@ struct parser_view
struct CsvParser
{
explicit CsvParser(std::istream &in) : in(in) {};
explicit CsvParser(std::istream &in) : in(in){};
std::istream &in;
std::string buf;
parser_view view;

7
himbaechel/arch.cc
View File

@ -293,8 +293,7 @@ PipId Arch::getPipByName(IdStringList name) const
IdString(tdata.wires[tdata.pips[pip].src_wire].name) == name[2]) {
const auto tmp_pip = PipId(tile, pip);
if ((name.size() == 3 && !isPipInverting(tmp_pip)) ||
(name.size() == 4 && isPipInverting(tmp_pip))) {
if ((name.size() == 3 && !isPipInverting(tmp_pip)) || (name.size() == 4 && isPipInverting(tmp_pip))) {
return tmp_pip;
}
}
@ -307,8 +306,8 @@ IdStringList Arch::getPipName(PipId pip) const
const auto &tdata = chip_tile_info(chip_info, pip.tile);
const auto &pdata = tdata.pips[pip.index];
const auto name = IdStringList::concat(tile_name.at(pip.tile),
IdStringList::concat(IdString(tdata.wires[pdata.dst_wire].name),
IdString(tdata.wires[pdata.src_wire].name)));
IdStringList::concat(IdString(tdata.wires[pdata.dst_wire].name),
IdString(tdata.wires[pdata.src_wire].name)));
if (isPipInverting(pip))
return IdStringList::concat(name, id("INV"));
return name;

4
himbaechel/arch.h
View File

@ -662,9 +662,7 @@ struct Arch : BaseArch<ArchRanges>
uarch->notifyPipChange(pip, nullptr);
BaseArch::unbindPip(pip);
}
bool isPipInverting(PipId pip) const override {
return uarch->isPipInverting(pip);
}
bool isPipInverting(PipId pip) const override { return uarch->isPipInverting(pip); }
// -------------------------------------------------

3
himbaechel/uarch/example/example.cc
View File

@ -329,7 +329,8 @@ struct ExampleArch : HimbaechelArch
{
ExampleArch() : HimbaechelArch("example") {};
bool match_device(const std::string &device) override { return device == "EXAMPLE"; }
std::unique_ptr<HimbaechelAPI> create(const std::string &device, const dict<std::string, std::string> &args) override
std::unique_ptr<HimbaechelAPI> create(const std::string &device,
const dict<std::string, std::string> &args) override
{
return std::make_unique<ExampleImpl>();
}

2
himbaechel/uarch/gowin/cst.cc
View File

@ -20,7 +20,7 @@ struct GowinCstReader
Context *ctx;
std::istream &in;
GowinCstReader(Context *ctx, std::istream &in) : ctx(ctx), in(in) {};
GowinCstReader(Context *ctx, std::istream &in) : ctx(ctx), in(in){};
const PadInfoPOD *pinLookup(const PadInfoPOD *list, const size_t len, const IdString idx)
{

3
himbaechel/uarch/ng-ultra/ng_ultra.cc
View File

@ -1060,7 +1060,8 @@ struct NgUltraArch : HimbaechelArch
{
NgUltraArch() : HimbaechelArch("ng-ultra") {};
bool match_device(const std::string &device) override { return device == "NG-ULTRA"; }
std::unique_ptr<HimbaechelAPI> create(const std::string &device, const dict<std::string, std::string> &args) override
std::unique_ptr<HimbaechelAPI> create(const std::string &device,
const dict<std::string, std::string> &args) override
{
return std::make_unique<NgUltraImpl>();
}

34
himbaechel/uarch/xilinx/xdc.cc
View File

@ -161,8 +161,7 @@ void XilinxImpl::parse_xdc(const std::string &filename)
log_nonfatal_error("expected at least four arguments to 'set_property' (on line %d)\n", lineno);
num_errors++;
goto nextline;
}
else if (arguments.at(1) == "-dict") {
} else if (arguments.at(1) == "-dict") {
std::vector<std::string> dict_args = split_to_args(strip_quotes(arguments.at(2)), false);
if ((dict_args.size() % 2) != 0) {
log_nonfatal_error("expected an even number of argument for dictionary (on line %d)\n", lineno);
@ -190,16 +189,19 @@ void XilinxImpl::parse_xdc(const std::string &filename)
for (int cursor = 3; cursor < int(arguments.size()); cursor++) {
std::vector<CellInfo *> dest_loc = get_cells(arguments.at(cursor));
if (dest_loc.empty())
log_warning("found set_property with no cells matching '%s' (on line %d)\n", arguments.at(cursor).c_str(), lineno);
log_warning("found set_property with no cells matching '%s' (on line %d)\n",
arguments.at(cursor).c_str(), lineno);
dest.insert(dest.end(), dest_loc.begin(), dest_loc.end());
}
for (auto c : dest) {
for (const auto &pair : arg_pairs) {
IdString id_prop = ctx->id(pair.first);
if (ctx->debug)
log_info("applying property '%s' = '%s' to cell '%s' (on line %d)\n", pair.first.c_str(), pair.second.c_str(), c->name.c_str(ctx), lineno);
if(c->attrs.find(id_prop) != c->attrs.end()) {
log_nonfatal_error("found multiple properties '%s' for cell '%s' (on line %d)\n", pair.first.c_str(), c->name.c_str(ctx), lineno);
log_info("applying property '%s' = '%s' to cell '%s' (on line %d)\n", pair.first.c_str(),
pair.second.c_str(), c->name.c_str(ctx), lineno);
if (c->attrs.find(id_prop) != c->attrs.end()) {
log_nonfatal_error("found multiple properties '%s' for cell '%s' (on line %d)\n",
pair.first.c_str(), c->name.c_str(ctx), lineno);
num_errors++;
}
c->attrs[id_prop] = std::string(pair.second);
@ -213,17 +215,14 @@ void XilinxImpl::parse_xdc(const std::string &filename)
std::string opt = arguments.at(cursor);
if (opt == "-add") {
log_warning("ignoring unsupported XDC option '%s' (on line %d)\n", opt.c_str(), lineno);
}
else if (opt == "-name" || opt == "-waveform") {
} else if (opt == "-name" || opt == "-waveform") {
log_warning("ignoring unsupported XDC option '%s' (on line %d)\n", opt.c_str(), lineno);
cursor++;
}
else if (opt == "-period") {
} else if (opt == "-period") {
cursor++;
period = std::stod(arguments.at(cursor));
got_period = true;
}
else
} else
break;
}
if (!got_period) {
@ -235,17 +234,19 @@ void XilinxImpl::parse_xdc(const std::string &filename)
std::vector<NetInfo *> dest;
if (cursor >= int(arguments.size()))
log_warning("found create_clock without designated nets (on line %d)\n", lineno);
for ( ; cursor < (int)arguments.size(); cursor++) {
for (; cursor < (int)arguments.size(); cursor++) {
std::vector<NetInfo *> dest_loc = get_nets(arguments.at(cursor));
if (dest_loc.empty())
log_warning("found create_clock with no nets matching '%s' (on line %d)\n", arguments.at(cursor).c_str(), lineno);
log_warning("found create_clock with no nets matching '%s' (on line %d)\n",
arguments.at(cursor).c_str(), lineno);
dest.insert(dest.end(), dest_loc.begin(), dest_loc.end());
}
for (auto n : dest) {
if (ctx->debug)
log_info("applying clock period constraint on net '%s' (on line %d)\n", n->name.c_str(ctx), lineno);
if (n->clkconstr.get() != nullptr) {
log_nonfatal_error("found multiple clock constraints on net '%s' (on line %d)\n", n->name.c_str(ctx), lineno);
log_nonfatal_error("found multiple clock constraints on net '%s' (on line %d)\n",
n->name.c_str(ctx), lineno);
num_errors++;
}
n->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint);
@ -257,8 +258,7 @@ void XilinxImpl::parse_xdc(const std::string &filename)
log_warning("ignoring unsupported XDC command '%s' (on line %d)\n", cmd.c_str(), lineno);
}
nextline:
; // Phony statement to have something legal after the label
nextline:; // Phony statement to have something legal after the label
}
if (!isempty(linebuf)) {
log_nonfatal_error("unexpected end of XDC file\n");

3
himbaechel/uarch/xilinx/xilinx.cc
View File

@ -569,7 +569,8 @@ struct XilinxArch : HimbaechelArch
{
XilinxArch() : HimbaechelArch("xilinx") {};
bool match_device(const std::string &device) override { return device.size() > 3 && device.substr(0, 3) == "xc7"; }
std::unique_ptr<HimbaechelAPI> create(const std::string &device, const dict<std::string, std::string> &args) override
std::unique_ptr<HimbaechelAPI> create(const std::string &device,
const dict<std::string, std::string> &args) override
{
return std::make_unique<XilinxImpl>();
}

3
rust/rust.cc
View File

@ -55,8 +55,7 @@ static inline PipId unwrap_pip(const uint64_t pip) noexcept { return unwrap<PipI
static inline WireId unwrap_wire(const uint64_t wire) noexcept { return unwrap<WireId>(wire); }
} // namespace
template<typename T>
struct IterWrapper
template <typename T> struct IterWrapper
{
T current;
T end;