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Tim Edwards 66cf2b82d9 Merge branch 'master' into netgen-1.5 2021-08-30 03:00:02 -04:00
Tim Edwards d7355cea95 Updated the vezzal docker image version for CI. 2021-08-29 19:41:14 -04:00
Tim Edwards bc4192496b Merge branch 'master' into netgen-1.5 2021-08-28 13:15:58 -04:00
Tim Edwards 32585a572c Corrected the badge link at the top of README.md to point to my
own repository instead of a fork.
2021-08-28 13:14:11 -04:00
Tim Edwards 168e5502a1 Merge branch 'master' into netgen-1.5 2021-08-06 11:38:38 -04:00
Tim Edwards e773739e7d Updated VERSION as a forced change to check continuous integration
on github.
2021-08-06 11:37:29 -04:00
Tim Edwards 8d4b621b7d Merge branch 'master' into netgen-1.5 2021-08-06 11:25:01 -04:00
Tim Edwards 583cc3a151 Updated VERSION to go along with the merge of pull request #27 from
Sai Charan.  Subsequent mirror pushes to github should trigger the
continuous integration.
2021-08-06 11:18:56 -04:00
Sai Charan Lanka bdd7d25943 Update main.yml 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 903b813821 Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 1f9d4317e3 Update main.yml 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 7b8086fc3a Update main.yml 2021-08-06 11:18:32 -04:00
Sai Charan Lanka e80f70e67b Update main.yml 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 6cc898b34b Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 30bbc28c17 Update README.md 2021-08-06 11:18:32 -04:00
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Sai Charan Lanka aeedf5fae9 Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka f50dfd9261 Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 409ce224ad Update README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka f50093e6c6 Rename README to README.md 2021-08-06 11:18:32 -04:00
Sai Charan Lanka a27ac8c679 Update README 2021-08-06 11:18:32 -04:00
Sai Charan Lanka 883755eed3 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 484cb26eee Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 7cc6996017 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 7f9acf6a1a Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka e1a3ae5619 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 4e75889605 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka e017811239 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 4468d36462 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka b99fb96259 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka ec8299ea14 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 376296eda5 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 30acb8be63 Update main.yml 2021-08-06 11:18:31 -04:00
Sai Charan Lanka 7e15a26417 Create main.yml 2021-08-06 11:18:31 -04:00
Tim Edwards ba3e862552 Merge branch 'master' into netgen-1.5 2021-07-30 03:00:29 -04:00
Tim Edwards 21750da6c4 Corrected the Makefile in the python directory to set the
lvs_manager.py script to be executable, or else "netgen -gui" will
not work.
2021-07-29 10:45:44 -04:00
Tim Edwards cf6dd2a638 Merge branch 'master' into netgen-1.5 2021-07-16 03:00:11 -04:00
Tim Edwards a332c23524 Corrected an error in "series_sort" that will overwrite memory
randomly if combining series devices that do not have an "S"
property (which is the typical case).  This will normally result in
a crash.
2021-07-15 16:03:43 -04:00
Tim Edwards b6d896e73f Merge branch 'master' into netgen-1.5 2021-07-12 03:00:10 -04:00
Tim Edwards 064195ecc9 Reinstated some code that had been commented out that prints pin
information for a non-matching pin in circuit1 and generates a
proxy pin in circuit2---there is some case where this is redundant,
I think, but I need to find the example.
2021-07-11 17:04:50 -04:00
Tim Edwards 88d53fab15 Correction to the verilog parser to recognize modifiers such as
"~", "!", or "-" in front of variable names in a pin list that would
render the module behavioral verilog.
2021-07-11 12:06:16 -04:00
Tim Edwards c287b6cd28 A previous attempt (in revision 193) to make the "lvs" script stop
saying that pins were mismatched when pin matching was never run
accidentally resulted in pin matching not being applied to black-box
entries.  This has been corrected.
2021-07-11 10:58:30 -04:00
Tim Edwards 9251ce2a48 Merge branch 'master' into netgen-1.5 2021-07-11 03:00:33 -04:00
Tim Edwards 0a0a6bcf63 Modified the handling of missing pins (again) such that netgen
continues to allow missing pins to match unconnected pins, but
*only* on subcircuits below the top level.  This essentially forces
layouts to separate merged pins with metal resistors, although
there should be an option in magic's ext2spice routine that allows
"equiv" statements, when declaring equivalence of two ports, to be
replaced by a zero volt source or zero ohm ideal resistor.
2021-07-10 13:54:14 -04:00
Tim Edwards 72ef2f2637 Corrected the pin matching so that it runs the same loop on unmatched
pins on non-black-boxed circuits as it does not black-boxed circuits,
but specifically looking for pins that are disconnected on both sides,
since those do not appear in the node list and are not otherwise
handled.  Otherwise, disconnected pins will appear to have disappeared
from the first netlist.
2021-07-10 11:25:07 -04:00
Tim Edwards aa82164c08 Merge branch 'master' into netgen-1.5 2021-07-09 03:00:34 -04:00
Tim Edwards 287f5963d1 Corrected an error that crept into the netgen.tcl script that causes
the "failed pin matching" error message to appear for cells mismatching
topology (in which case pin matching is never done).
2021-07-08 08:56:52 -04:00
Tim Edwards fb7876c7a6 Merge branch 'master' into netgen-1.5 2021-07-03 03:00:13 -04:00
Tim Edwards a984ac1a4d Corrected an error in a recent update that handles the case where
a final parallel or series combination needs to be done but there
are still multiple property records.  The multiplier was being
incorrectly applied twice, causing an automatic mismatch in
parameter values.
2021-07-02 10:51:44 -04:00
Tim Edwards e31caa3500 Merge branch 'master' into netgen-1.5 2021-06-26 03:00:10 -04:00
Tim Edwards 738c1f7b37 Corrected an error probably introduced into the code with the handling
of multiple devices during flattening, that will skip over a node
record at the end of a subcircuit call being flattened and therefore
remove it from the netlist.
2021-06-25 13:16:42 -04:00
Tim Edwards c3cf6c3765 Made another correction that prevents netgen from truncating the pin
list that it prints in the side-by-side element mismatch comparison
for an element, when there is no node record associated with the pin
connection.  This makes the output clearer.
2021-06-25 12:35:11 -04:00
Tim Edwards 99dcc20c0a Corrected MatchPins so that it returns an error code of 0 when pins are
swapped, so that if pin names are swapped on the top level, netgen will
report this as a final error message.  Otherwise, the mismatch is only
reported back in the pin list where it is not obvious.
2021-06-25 10:27:24 -04:00
Tim Edwards c1355bee45 Merge branch 'master' into netgen-1.5 2021-06-25 03:00:10 -04:00
Tim Edwards 4bbc496749 Corrected an error in the "run converge" and "run resolve" methods.
The algorithm is to run without exhaustive subdivision until the
last step because this is much faster.  The final iteration must
be run with exhaustive subdivision on, or else it is possible to
have cells with swapped pins matching.  The routines that resolve
automorphisms were setting exhaustive subdivision for the final
iteration.  But simple "run converge" and "run resolve" were not.
2021-06-24 14:53:24 -04:00
Tim Edwards 4fb8b59a2f Merge branch 'master' into netgen-1.5 2021-06-19 03:00:10 -04:00
Tim Edwards c4f03eabaf Corrected an error not checking for running off the end of a list,
in code from a recent commit.
2021-06-18 21:23:21 -04:00
Tim Edwards 6a555ad6ed Added a missing method from parallel/series matching which is to
add properties across multiple property records in the last matching
step, if there are still multiple properties and the values can be
combined.  Previously, netgen had been assuming that there would only
be one property record left at this point, which is not true.  This
shows up particularly for BSIM fingered devices, since "nf" is
ignored.
2021-06-18 10:44:44 -04:00
Tim Edwards 626faf22f9 Merge branch 'master' into netgen-1.5 2021-06-17 03:00:10 -04:00
Tim Edwards 1c5457e180 Corrected a minor issue that cropped up today in which the search
for file extensions is greedy and picks the first matching extension
starting at the front of the string, such that, e.g., "file.ext.spice"
is interpreted as a ".ext" file and not a ".spice" file.
2021-06-16 15:20:39 -04:00
Tim Edwards 7d246c36a6 Corrected an issue with flattening when the instances to be flattened
run to the end of the list of circuit elements.  Also corrected
another issue caused by the flag to denote multiple no-connect pins,
which can be on an instance pin and so cannot share the data from the
instance record.
2021-06-16 14:32:14 -04:00
Tim Edwards 550234dce5 Merge branch 'master' into netgen-1.5 2021-06-15 03:00:36 -04:00
Tim Edwards 92dfa74403 Corrected an issue that was caused by introducing a type of parallel
device with one or more no-connect pins.  The flag that indicates a
no-connect pin was checked incorrectly, potentially causing obscure
and misleading property mismatch messages to be generated.
2021-06-14 14:30:10 -04:00
Tim Edwards a4c0028706 Merge branch 'master' into netgen-1.5 2021-06-13 03:00:32 -04:00
Tim Edwards d53541d1d3 Correction to previous commit (failed to link to last pointer
after processing properties during flattening).
2021-06-12 20:15:55 -04:00
Tim Edwards 57b2d21221 Modified the way flattening is done to account for multiple property
records, which were being ignored.  This really only applies to
parallel subcircuits being flattened.  To flatten correctly requires
that any circuit with N property records must be flattened into the
parent at least N times.  To do:  Must look for M > 1 records in the
properties and flatten (M - 1) additional times.
2021-06-12 17:37:50 -04:00
Tim Edwards e7ae84bbc8 Merge branch 'master' into netgen-1.5 2021-06-10 03:00:09 -04:00
Tim Edwards dfabdaa367 Modified the JSON output so that missing pins which do not match
unconnected pins in the other netlist are marked as "(no pin)"
rather than "(no matching pin)".  This allows a script parsint the
JSON file (e.g., count_lvs.py from qflow) to distinguish between a
real pin error and one that can be ignored.
2021-06-09 09:34:02 -04:00
Tim Edwards c5c1306f6a Corrected a minor error where the property mismatch check outputs
an error message while doing a non-final iteration, where all
output is supposed to be suppressed.
2021-06-09 09:20:45 -04:00
Tim Edwards 43c018f3bc Merge branch 'master' into netgen-1.5 2021-06-09 03:00:10 -04:00
Tim Edwards 0614461c84 Modified MatchPins so that pin mismatches on nets that are not
connected to anything are once again ignored (the prior commit
to prevent netgen from not reporting swapped pins as an error
overcorrected).
2021-06-08 17:25:17 -04:00
Tim Edwards 6e94886b65 Messed up basic pin comparison between black-box vs. non-black-box
subcircuit situations in the last commit.  This commit fixes it.
2021-06-08 16:52:57 -04:00
Tim Edwards ca119edc0a Merge branch 'master' into netgen-1.5 2021-06-04 03:00:10 -04:00
Tim Edwards 0556abf3c1 Finally corrected the issue with pins being able to be swapped
without netgen noticing---this behavior got broken by an
exception for "black box" circuits, but failed to check if the
circuit really was marked as a "black box" or not.  Fixing that
revealed another issue with verilog implicit pins.  Both issues
have now been corrected.
2021-06-03 17:42:54 -04:00
Tim Edwards 84348d2fe1 Merge branch 'master' into netgen-1.5 2021-05-31 03:00:10 -04:00
Tim Edwards 3356dd784e Made a number of usability corrections to the python GUI for
netgen.  More work will be done later.  Also:  Removed the
derived file lvs_manager.py from the repository, and modified
the Makefile to remove it as part of "make clean".
2021-05-30 20:39:47 -04:00
Tim Edwards 813b29cdc4 Merge branch 'master' into netgen-1.5 2021-05-29 03:00:10 -04:00
Tim Edwards 00949970b4 The previous method change for sorting to accommodate capacitors and
other devices that do not have a "critical property" that determines
which properties can add together was flawed and messed up the sorting
of devices like transistors and resistors that do have a critical
property.  Reworked the sorting order so that it makes sense for both
situations.
2021-05-28 21:20:39 -04:00
Tim Edwards ccf4a0a900 Merge branch 'master' into netgen-1.5 2021-05-27 03:00:32 -04:00
Tim Edwards c83b6def5b Corrected an issue with swapped arguments to PromoteProperty().
Also corrected a superficial issue with an attempt to print out an
instance name that doesn't exist.  There is an underlying bug here
related to cells that have no pins and/or no contents which has not
been debugged.  The fix just keeps netgen from segfaulting.
2021-05-26 12:46:57 -04:00
Tim Edwards e34166fdb9 Merge branch 'master' into netgen-1.5 2021-05-26 03:00:32 -04:00
Tim Edwards 8fc2c097d2 Added one modification that automatically ignores any cell that has
no pins at all.  This overrides the default behavior of treating
empty cells as "black-box" entries, and avoids attempts to compare
cells like logo artwork.
2021-05-25 12:41:57 -04:00
Tim Edwards a13491e358 Merge branch 'master' into netgen-1.5 2021-05-25 03:00:09 -04:00
Tim Edwards 2ac2a3b6f8 Fixed a bad assumption; PropertyOptimize allows devices with
different additive properties (like transistor width) to combine;
this is totally wrong and may have been left over from code written
before the routine was split into simple combinations (add similar
devices) and agressive combinations (e.g., add widths together).
2021-05-24 10:05:10 -04:00
Tim Edwards 1d05b8b676 Merge branch 'master' into netgen-1.5 2021-05-20 03:00:31 -04:00
Tim Edwards 759d63cea9 Changed a comment in the code that no longer applies after the last
modification.
2021-05-19 16:42:03 -04:00
Tim Edwards 476da015f0 Added support for expression parameters to be added to a device
class during setup, for the purpose of generating some derived
value that is used for merging and sorting, such as area = l*w.
Note that this likely needs adjusting so that the expression is
evaluated but not replaced for the purpose of sorting, since the
values to the parameter may change after parallel and series
merging.
2021-05-19 16:27:52 -04:00
Tim Edwards 4aa8a72769 Corrected an error found in ResolveAutomorphsByProperty which would
cause inexplicable output in case of a property error by showing a
netlist topography error instead of a property error (but the output
shows that the netlists match, and there is no reporting of any
property errors).  This error was discovered while implementing a
better sorting method for parallel combination.  The improved method
sorts on two properties rather than one, and so should not fall into
the error where, say, devices are sorted on W but have different L
for a device like a capacitor where no "critical" property is
specified (and other similar cases, although that is a common one).
2021-05-19 14:56:38 -04:00
Tim Edwards e97d6f1aeb Merge branch 'master' into netgen-1.5 2021-05-14 03:00:10 -04:00
Tim Edwards 47e7367c26 Updated the versio with the last commit. 2021-05-13 15:58:49 -04:00
Tim Edwards 362fb7120b Modified the behavior of the parallel combination of devices with
"similar no connect" pins so that it is not done on top-level
netlists.  This is mainly to deal with the problem where connections
that would normally be pins (but may have, for example, been
connected to a voltage source in a schematic that was deleted because
it was not a netlistable device) are treated as no-connects.
The parallel combination of devices with similar no-connects can then
differ between netlists that differ in describing transistors as
fingered vs. individual devices.  This is an obscure case, but the
output of netgen then becomes not only wrong but difficult to
understand what happened, so it is better to avoid.
2021-05-13 15:50:12 -04:00
Tim Edwards fb4759a8cd Merge branch 'master' into netgen-1.5 2021-05-04 03:00:10 -04:00
Tim Edwards 92e8fed8be Corrected an error in checking merge flags when doing sorting of
parallel and series devices.  This was a fairly major error
undermining the property sorting (the case where the same number
of devices are in parallel in both circuits and need to be sorted
by, e.g., width, prior to checking for matches).
2021-05-03 11:20:44 -04:00
Tim Edwards 45d4004d43 Merge branch 'master' into netgen-1.5 2021-05-02 03:00:09 -04:00
Tim Edwards 01b2484be3 Updated version. 2021-05-01 22:49:59 -04:00
Tim Edwards fe47d84ace Missed a corner case in the series combination code where a device
has been shuffled to the beginning of the cell, which requires
different handling.
2021-05-01 22:48:59 -04:00
Tim Edwards 0b014e6efd Merge branch 'master' into netgen-1.5 2021-03-20 03:00:09 -04:00
Tim Edwards 0a2adeb593 Modified the "flatten" command to allow class "module" to be
flattened.  This is marginally useful---since the "module" class
is a black box, it is essentially the same as using the "ignore"
command.
2021-03-19 13:57:11 -04:00
Tim Edwards 330b34139c Slight modification to print the list of cells being forced to
match for both the filename option and immediate list.
2021-03-19 10:51:42 -04:00
Tim Edwards 62d0352149 Modified the "-noflatten" command option to "lvs" so that it can be
given a filename as a value in addition to being passed a list of
cells directly.
2021-03-19 09:41:42 -04:00
Tim Edwards 9ca713dfd9 Merge branch 'master' into netgen-1.5 2021-03-18 03:00:29 -04:00
Tim Edwards b1b04b8e87 Corrected a statement related to proxy pins that can cause a
segfault condition.
2021-03-17 16:31:22 -04:00
Tim Edwards 851a1f941e Merge branch 'master' into netgen-1.5 2021-03-06 03:00:09 -05:00
Tim Edwards 6b9d92de65 Corrected some pointer-to-int and int-to-pointer conversions to
keep the compiler happy.
2021-03-05 20:19:04 -05:00
Tim Edwards d763ad0e60 First and simplest (but most effective) cut at aligning the two
sides of the output when presenting side-by-side results.  This
matches up net or device names within a partition.  Where net or
device names match, the contents are also aligned on either side.
I attempted to also do a "best match" of contents between sides,
but as this involves a lot of analyzing the contents, it is very
computationally expensive, and so the code has been disabled.  It
could be added back in as an option.  There are also various ways
to optimize it for speed.
2021-03-05 17:23:22 -05:00
Tim Edwards fd72e24a86 Corrected an error in the code that handles no-connects as valid
pins for enabling parallel combinations, which could cause a crash.
Added a "-force" option to "equate pins" to allow pins to be matched
even on subcircuits that did not correctly match;  this was done in
conjuction with an extra option to the "lvs" command "-noflatten="
to pass a list of cellname to not be flattened even if they do not
match.  This is generally discouraged, as it prevents netgen from
resolving differences between layout and schematic hierarchy, but it
can be useful for checking that the hierarchy above a certain cell
is correct, given that if a subcell is really unmatched, then its
errors will keep propagating up the top level, making additional
errors hard to diagnose.
2021-03-05 11:32:17 -05:00
Tim Edwards 20077d3d56 Modifed the handling of parallelized no-connects so that the behavior
can be turned on or off from the setup using "property parallel open"
to allow parallelizing devices with no-connect pins vs. "property
parallel connected" to only allow parallelizing of devices with all
pins connected.
2021-03-03 17:31:45 -05:00
Tim Edwards fb798d6ce7 Merge branch 'master' into netgen-1.5 2021-03-03 03:00:12 -05:00
Tim Edwards a21ba820e9 Corrected a missing variable in a print statement in the SPICE read
routine that can cause a segfault.
2021-03-02 21:48:48 -05:00
Tim Edwards 792c5e569a Resolved the case mentioned in a prior commit where the case of N
devices in parallel with unconnected pins would be confused with
N devices in parallel with those pins all tied together.  This is
treated as a property error.
2021-03-02 16:49:03 -05:00
Tim Edwards f92192efd4 Corrected an error from yesterday's commit; the test case for
parallel combinations with disconnected nodes works with the error,
but in general it won't.
2021-03-02 10:58:36 -05:00
Tim Edwards 1f50c7ccc5 Updating VERSION with pull request #18 on github. 2021-03-02 10:16:54 -05:00
Ahmed Ghazy 8282460774 Remove netgen.{sh,tcl} and add them to .gitignore 2021-03-02 10:24:17 +02:00
Tim Edwards a888502038 Merge branch 'master' into netgen-1.5 2021-03-02 03:00:35 -05:00
Tim Edwards ea07642172 Removed the symmetry breaking option from the scripted "lvs"
command.
2021-03-01 16:57:49 -05:00
Tim Edwards e9da037001 Removed the code for fast symmetry breaking, as it has been found
to generate incorrect results on occasion.  The method to parallelize
cells with the same no-connect pins should avoid the worst-case
symmetry breaking that was previously plaguing the LVS of large
standard-cell layouts.
2021-03-01 16:55:07 -05:00
Tim Edwards 7ee50a3f8f Modified the parallel combination code to treat cells as equivalently
parallel if the same pins are no-connects.  These were previously not
treated as parallel because each no-connect has a unique node number,
and cells were only considered as parallel if all pins connected to
the same node numbers.  This avoids issues with long-running symmetry
breaking on standard cell designs due to cells like antenna taps or
any cell that is placed without connecting it up.  To do:  This
makes indistinguishable certain cases, e.g., N cells in circuit 1
with pin X open vs. N cells in circuit 2 with pin X all tied together.
This could be caught during property matching.
2021-03-01 16:33:55 -05:00
Tim Edwards c16258d4d1 Merge branch 'master' into netgen-1.5 2021-02-25 03:00:36 -05:00
Tim Edwards c7848c9c02 Corrected an error that (in a rare circumstance) can cause netgen
to go into an infinite loop and fill memory until it crashes, due
to a complete pin mismatch between devices causing one device to
have its pins removed and replaced with proxy pins.
2021-02-24 16:12:19 -05:00
Tim Edwards 5341d7a5fd Merge branch 'master' into netgen-1.5 2021-02-17 03:00:31 -05:00
Tim Edwards 402e1f0f25 Found a chokepoint in FlattenInstancesOf that was unnecessary as it
was running through the entire object linked list to find the
predecessor of a record that it had already found.  Solved by simply
keeping track of the predecessor record.
2021-02-16 17:12:00 -05:00
Tim Edwards 8395df633c Merge branch 'master' into netgen-1.5 2021-02-10 03:00:16 -05:00
Tim Edwards 19471275df Added handling of control blocks (.CONTROL ... .ENDC) in ngspice-
format files to the SPICE parser, so that netgen can be run
directly on a testbench file and not generate errors due to
statements in the control block.
2021-02-09 09:30:27 -05:00
Tim Edwards e75f5661e2 Added a zero-value current source to the zero-valued devices handled
by the pre-matching method.  The current source is treated like the
others except that it forms an open circuit rather than a short.
2021-02-09 09:12:22 -05:00
Tim Edwards 6554063df3 Merge branch 'master' into netgen-1.5 2021-01-22 03:00:40 -05:00
Tim Edwards a034fc16d6 Updated VERSION. 2021-01-21 13:41:20 -05:00
Tim Edwards 62fbd422e2 Modified netcmp.c "addproxies" routine to not get confused by cells
with no pins marked with a "(no pins)" placeholder.  Otherwise it
goes into an infinite loop and eats up memory until it crashes.
2021-01-21 13:38:44 -05:00
Tim Edwards 4416a380b3 Merge branch 'master' into netgen-1.5 2021-01-18 03:00:51 -05:00
Tim Edwards d0bae6aff4 Updated VERSION with the merge of pull request #15 from Alessandro de
Laurenzis.
2021-01-17 11:38:11 -05:00
Alessandro De Laurenzis 8a7bb7f2ca Fix missing prototype for ReadVerilogFile function
Unbreak OpenBSD port for mips64 arch
2021-01-17 10:21:52 +01:00
Tim Edwards 46394b2000 Merge branch 'master' into netgen-1.5 2021-01-17 03:00:15 -05:00
Tim Edwards 0df6c83df5 Updated VERSION to go along with the merge of pull request #14
from Anton Blanchard.
2021-01-16 12:05:52 -05:00
Anton Blanchard 8996fe03dc Increase OBJHASHSIZE
I have a design that is taking quite a long time for netgen to complete LVS
checking. Profiles show a large chunk of runtime is in the hash functions.

Some of the hashtables are very sparsely populated, but others are
heavily used. One hashtable has chains of over 250. Longer term it would
be worth investigating resizing the hashtables (or perhaps using other
data strutures), but for now I looked at what changing the number of
hash buckets (OBJHASHSIZE) does for performance:

OBJHASHSIZE	time (mm:ss)
997		24:18
10093		 4:42
42073		 3:12
104729		 2:51

I somewhat arbitrarily chose 42073 which gives us a 7.6x improvement in
runtime.
2021-01-15 18:24:34 -07:00
Tim Edwards 3fe3bc4cfa Merge branch 'master' into netgen-1.5 2021-01-09 03:00:32 -05:00
Tim Edwards f3cebd9099 Corrected a potential crash condition while doing series combination. 2021-01-08 09:55:00 -05:00
Tim Edwards 6661910672 Merge branch 'master' into netgen-1.5 2020-12-21 03:00:30 -05:00
Tim Edwards 920c6e6928 Corrected a problem causing a segfault during a property record
copy if the property record does not have a model.class record
(should it always?).
2020-12-20 11:55:20 -05:00
Tim Edwards e7a36630f6 Merge branch 'master' into netgen-1.5 2020-12-16 03:00:54 -05:00
Tim Edwards 69780aa048 Added patch from Mitch Bailey which sorts the objects in a verilog
file input so that pins occur first before nodes, as they do in a
SPICE netlist.  Certain parts of the comparison code depend on pins
being first in the netlist, and reordering them when reading input
is easier than rewriting the rest of the code.
2020-12-15 09:57:49 -05:00
Tim Edwards f32b0b34a3 Merge branch 'master' into netgen-1.5 2020-12-06 03:00:10 -05:00
Tim Edwards 2a0ebfde93 Updated VERSION with the commit. 2020-12-05 15:46:45 -05:00
Tim Edwards 6e9e6abe98 Removed the netgen.sh and netgen.tcl scripts from the repository,
which are generated by ./configure and should not be in the repo.
2020-12-05 15:46:03 -05:00
Tim Edwards 6b731ddd7a Merge branch 'master' into netgen-1.5 2020-12-04 03:00:27 -05:00
Tim Edwards b9769b9f55 Updated version to go along with pull request merge from github. 2020-12-03 20:17:59 -05:00
Tim 'mithro' Ansell 7e42483986 Fix configure script to not clobber CFLAGS.
Signed-off-by: Tim 'mithro' Ansell <[email protected]>
2020-11-29 16:39:28 -08:00
Tim 'mithro' Ansell 97b0d08e4f Rework configure script so exit code works.
The previous script would swallow the exit code of the `./configure`
script and thus it looked like doing a configure always succeeded.

Signed-off-by: Tim 'mithro' Ansell <[email protected]>
2020-11-29 16:35:47 -08:00
Tim Edwards 99e35d8b11 Merge branch 'master' into netgen-1.5 2020-10-09 03:00:25 -04:00
Tim Edwards d2c356f9e2 Added a "-full" switch to the scripted "lvs" command that switches
to the old symmetry breaking method (see previous commit message).
2020-10-08 09:57:01 -04:00
Tim Edwards 5e99fd5ef9 Found a counterexample which shows that the fast symmetry breaking
introduced in revision 150 can result in an incorrect result
reporting a bad match where the match is actually good (as proven
by running the full symmetry breaking on the same netlist).
Because the fast symmetry breaking is orders of magnitude faster
for large circuits, and because the false positive result appears
to be rare, I have introduced a command "symmetry" to switch
methods between fast and full.  So fast symmetry breaking can be
run unless the result fails on symmetry breaking, in which case
the method can be switched to full to see if the problem is a
false positive or not.  This is not an ideal solution, and some
investigation is needed to determine if there is a way to apply
fast symmetry breaking without encountering a false positive
error.
2020-10-08 09:43:25 -04:00
Tim Edwards 65b542f0ab Merge branch 'master' into netgen-1.5 2020-10-08 03:00:22 -04:00
Tim Edwards 04dd4a64d5 Corrected problems with the port count routine not being specified
with the file number, so that it can get confused between libraries.
Also made a fix to coerce one cell class to be forced to be the
same in both circuits under some circumstances.
2020-10-07 21:32:07 -04:00
Tim Edwards b826870be9 Merge branch 'master' into netgen-1.5 2020-08-09 03:01:40 -04:00
Tim Edwards 50b0e9cb65 Found examples where the automated "pin matching" algorithm causes
the top level circuits to be declared matching with no errors even
though the pins do not match.  "proxy pins" are fine for subcells
to detect cases where one subcell has an unused pin and the matching
subcell does not declare it, but that should not be allowed on the
top level, as it cannot be known whether the pin is unused or not.
2020-08-08 13:19:26 -04:00
Tim Edwards ed5276d67b Merge branch 'master' into netgen-1.5 2020-08-04 03:00:31 -04:00
Tim Edwards 82be18ec4b Corrected a bounds check on sub-arrays inside bundles, that prevents
the bundle from being parsed correctly when any sub-array is only one
bit wide.
2020-08-03 22:57:19 -04:00
Tim Edwards 4ee3a1464b Corrected the left-hand side assignment for "assign" statements and
corrected the error statement so that it refers both to the (corrected)
left-hand side and also the portion of the right-hand side that cannot
be parsed as structural verilog.
2020-08-03 11:49:09 -04:00
Tim Edwards 69c9d85be7 Merge branch 'master' into netgen-1.5 2020-08-01 03:00:23 -04:00
Tim Edwards 8e215d3b66 Corrected the PropertyMatch() routine; previously the symmetry
breaking by property was only matching properties between circuits but
not within the same circuit, which is needed for correct symmetry
breaking.  But the PropertyMatch() routine assumed that it is passed
one item from each circuit, leading to a segfault when running the
symmetry breaking within a single circuit.  This has been fixed.
2020-07-31 12:56:20 -04:00
Tim Edwards c45d51e950 Tracked down and fixed problems with implicit pins in verilog (pins
that are not declared in the verilog netlist because they don't
connect to anything, and their presence is not required by verilog
syntax) and the printing of proxy pins created to act as placeholders
for those implicit pins.  Also removed the pinting of the "disconnected
pin" messages for black-box modules (since by definition they have
disconnected pins, because black-box modules have no contents).
2020-07-31 12:22:50 -04:00
Tim Edwards ad05d059c7 Merge branch 'master' into netgen-1.5 2020-07-31 03:00:27 -04:00
Tim Edwards 85eb34c01e Made several corrections to handling of proxy pins when matching
black-box circuits, especially those coming from verilog netlists
where a pin does not need to be declared and is implicitly floating.
This prevents the need to have an explicit black-box entry for any
verilog module that may have an instance that does not declare all
the pin connections.  Also corrected an error which causes mysterious
failures if a verilog netlist is read before a SPICE netlist,
because the former gets hashed case-sensitive and the latter changes
the hashing to case-insensitive.  Modified to force the SPICE
netlist to be treated case-sensitive, which may cause errors, but
is consistent with the reverse order handling, and doesn't cause
unexplained errors.
2020-07-30 22:51:34 -04:00
Tim Edwards 8a24c6c3ca Modified the ResolveAutomorphisms() routine once again, to break
symmetry of all elements in all symmetric partitions, rather than
(as previously done) all elements in each partition, before re-
running iterations to convergence.  This solves the problem of
having a very large number of partitions with a few elements each
taking a long time to run.
2020-07-30 14:48:08 -04:00
Tim Edwards 46cdf48bc4 Updated the version to force the tarball and github mirror. 2020-07-30 08:10:09 -04:00
Tim Edwards 9d542b92b0 Corrected one logical error in netcmp.c from the last commit,
discovered and fixed by Ahmed Ghazy.
2020-07-30 08:06:44 -04:00
Tim Edwards 1b2cd1497c Merge branch 'master' into netgen-1.5 2020-07-30 03:00:28 -04:00
Tim Edwards 71ad228d8d Modified the symmetry breaking routine that arbitrarily resolves
automorphisms so that it arbitrarily assigns all pairs from
circuit1 and circuit2 at once rather than assigning one pair at
a time and rerunning to convergence.  I'm not sure of the validity
of this, other than that I have never seen a circuit fail to match
after resolving automorphisms, leading me to believe that the way
the symmetry breaking is done is irrelevant.
2020-07-29 21:13:45 -04:00
Tim Edwards 339a0d5d4e Updated version to force the new tarball and github mirror. 2020-07-29 13:59:24 -04:00
Tim Edwards 9cebb76787 Corrected a problem in ResolveAutomorphsByProperty() that causes
long run-times even when there are no properties to check.  Corrected
a problem with SPICE and verilog netlist reading which arbitrarily
replaces file extensions even when a file extension is given,
resulting in reading the wrong file.
2020-07-29 13:57:08 -04:00
Tim Edwards d9d5a46c6e Merge branch 'master' into netgen-1.5 2020-07-25 03:00:09 -04:00
Tim Edwards 251622c8bc Corrected the routines DescendCountQueue and DescendCompareQueue
to include type CLASS_MODULE in the list of types to descend into,
since "module" (black-box) types need to be checked for pin
matching even if they have no contents.  This allows two verilog
netlists to be compared against each other.
2020-07-24 20:50:07 -04:00
Tim Edwards d73b711e3a Merge branch 'master' into netgen-1.5 2020-07-02 03:00:09 -04:00
Tim Edwards 18739235a9 Extended the code from the last commit to cover cases in which the
definition covers multiple lines;  this also is a general handler
of the backslash-newline continuation line.
2020-07-01 16:00:54 -04:00
Tim Edwards 07c493c796 Corrected the verilog parser's behavior with respect to string
definitions:  Now correctly parses everything from the definition
name to the end of line as the definition value.  Also:  The
search for definitions in the body of the text does not reject
non-alphanumerics "_" and "$" in the definition name, without
which definition names containing those characters will go
unrecongized.  Have not yet extended this to multi-line definition
values.
2020-07-01 14:28:00 -04:00
Tim Edwards cca0e4b3f3 Corrected an error in bundle assignment that failed to make a copy
of the root name of the LHS net, and so would use the last root
name copied, which might have belonged to something entirely
different, or nothing at all.
2020-07-01 13:11:37 -04:00
Tim Edwards 1428580109 Merge branch 'master' into netgen-1.5 2020-06-17 03:00:38 -04:00
Tim Edwards fb0e1d10b0 Added back a correction that did not get made in this code base
and so didn't make it into the commit.  Handles implicit pins in
verilog.
2020-06-16 17:16:30 -04:00
Tim Edwards 6f81e1d294 Removed a restriction on the "equate pins" command such that pins
are matched on circuits that have no elements.  This condition
does not necessarily indicate an error, and matching pins has no
adverse affect (while refusing to match them certainly can).
2020-06-16 15:56:59 -04:00
Tim Edwards cec6d89474 Corrected an uninitialized variable error in the verilog reading code
that produces a segfault condition.
2020-06-16 12:52:29 -04:00
Tim Edwards 210dfb25c3 Merge branch 'master' into netgen-1.5 2020-06-04 03:00:24 -04:00
Tim Edwards 9bcca3ac21 Corrected the verilog parsing (yet again!) so that it does not
mistakenly flag bus delimiter characters inside backslash-escaped
names when looking for bus delimiters.
2020-06-03 17:00:42 -04:00
Tim Edwards 27f2ab8b3f Merge branch 'master' into netgen-1.5 2020-03-28 03:00:24 -04:00
Tim Edwards 6ae6a246e9 Some additional changes to better identify behavioral verilog
blocks.
2020-03-27 15:09:56 -04:00
Tim Edwards d985ea340e One more bug fix. . . unitialized variable error. 2020-03-27 12:47:24 -04:00
Tim Edwards 5ea7916ff1 Final (I hope) correction to netgen for handling signal wraparound
for buses applied to instance arrayes.
2020-03-27 12:15:57 -04:00
Tim Edwards cf9dedb2f7 Additional corrections; needed to maintain port width in the
scan structure because it is used in two different places and
would have to run a cost-prohibitive search of the cell's
object list.  Also, was missing recording a bus input/output
signal from an "input" or "output" statement (as opposed to
in-line signals in the I/O list).
2020-03-27 11:31:21 -04:00
Tim Edwards da667c3b17 Corrected handling of wire bundles in the verilog parser. 2020-03-27 08:48:48 -04:00
Tim Edwards 1be00bbd99 Merge branch 'master' into netgen-1.5 2020-03-27 03:00:21 -04:00
Tim Edwards 36aa373fb2 Corrected an error in the verilog read to correctly assign signals
to bus pins over an array of instances.  Takes care of the three
situations where the length of the signal bus equals the number of
instances;  where the length of the signal bus is a multiple of
the number of instances;  and where the number of instances is a
multiple of the length of the signal bus.
2020-03-26 11:53:52 -04:00
Tim Edwards 18f230fc46 Changed the default string size for tmpstr in flattenInstancesOf
from 200 to 1024.  Probably this should be dynamically allocated
and expanded as needed, as it is holding names that are of
increasing length as a hierarchy is descended and the instance
prefixes appended to the name.
2020-03-26 09:04:52 -04:00
Tim Edwards 03b241a5d4 Merge branch 'master' into netgen-1.5 2020-03-11 03:00:17 -04:00
Tim Edwards 0f5a618353 Corrected some problems with property matching in netcmp.c.
However, I have identified an issue that has not yet been resolved,
which is that there can be automorphisms that are potentially
broken by property matching.  Currently, the automorphisms are
arbitrarily resolved, then properties are matched---and may fail
accordingly.
2020-03-10 21:39:41 -04:00
Tim Edwards 43cebd1ef9 Merge branch 'master' into netgen-1.5 2020-03-06 03:00:39 -05:00
Tim Edwards 983c654086 Corrected error in property matching that can cause a segfault. 2020-03-05 15:20:46 -05:00
Tim Edwards 515fccc633 Corrected error in printing the name of a file when it is not found
in an "include" statement in either SPICE or verilog.  Modified pin
matching behavior to force cells in both netlists to be marked as
black-box entries if either one is marked as a black-box entry (this
may not be needed, but shouldn't do any harm, either).
2020-03-05 09:41:22 -05:00
Tim Edwards 0490959b07 Merge branch 'master' into netgen-1.5 2020-03-05 03:00:09 -05:00
Tim Edwards 7d94a7d5f6 Updated VERSION for new tarball. 2020-03-04 21:06:21 -05:00
Tim Edwards 39b3bb4d96 Changed behavior of MatchPins so that disconnected pins that are to
be removed because they do not match pins on the other cell being
compared, are marked with a different number (-2) than the usual
(-1).  CleanupPins then only removes those pins that are marked,
rather than all disconnected pins.
2020-03-04 21:01:43 -05:00
Tim Edwards 44673a04b6 Corrected the verilog parser to handle backslash-escape notation
in instance names, and to ignore bus delimiters inside backslash-
escaped names when determining if a net is a bus or not.
2020-03-04 16:55:53 -05:00
Tim Edwards a34f08b20a Corrected problem in flattening code that would attempt to flatten
a cell that mismatched by having zero instances.  Which fails and
repeats indefinitely.
2020-03-04 15:17:42 -05:00
Tim Edwards 240a276431 Changed behavior of "equate pins" to detect placeholder cells as
a different way of treating "black box" cells.  Even when the
"-blackbox" option is specified, any cell that has no definition
will be treated as a black box.  This allows comparison of a
black-box netlist against a non-black-box netlist, such as a
verilog netlist vs. a SPICE netlist, without forcing the black-box
attribute on the SPICE netlist.  Then, if the SPICE netlist
contains cells without elements such as fill/decap/tap cells,
they can be flattened and removed instead of forcing an error or
requiring the use of "ignore".
2020-03-03 10:50:45 -05:00
Tim Edwards dc841f3293 Merge branch 'master' into netgen-1.5 2020-02-24 17:35:04 -05:00
Tim Edwards f7037fc9e6 Updated VERSION manually; checking regeneration of tarball. 2020-02-24 17:34:38 -05:00
Tim Edwards 23fb9356f4 Corrected Makefile to use -include instead of include on defs.mak
so that "make distclean" works.
2020-02-24 17:31:06 -05:00
Tim Edwards 05bcfede69 Merge branch 'master' into netgen-1.5 2020-02-24 16:39:19 -05:00
Tim Edwards 027b4ae468 Test update of VERSION. 2020-02-24 16:38:56 -05:00
Tim Edwards 72ed78e55a Update for change in ocd git script 2020-02-24 15:04:59 -05:00
Tim Edwards 59bb8a89c0 "ocd_git_pure automatic update to repo" 2020-02-24 15:04:27 -05:00
Tim Edwards 08a442fda2 Removed VERSION from .gitignore, and updated VERSION. 2020-02-24 11:50:38 -05:00
Tim Edwards 9bdaee652e "ocd_git_pure automatic update to repo" 2020-02-18 03:00:14 -05:00
Tim Edwards 9879b58f83 Merge branch 'master' into netgen-1.5 2020-02-18 03:00:13 -05:00
Tim Edwards cc0cc512c0 Modified the Makefile per the patch from Charlene at OpenBSD to
add GR_LIBS to the list of options to CC, as this apparently
prevents problems with older binutils, and should not affect
builds otherwise.
2020-02-17 14:04:40 -05:00
Tim Edwards 9e3b705fcc "ocd_git_pure automatic update to repo" 2020-02-11 03:00:09 -05:00
Tim Edwards d2c9129242 Merge branch 'master' into netgen-1.5 2020-02-11 03:00:09 -05:00
Tim Edwards e9c0596dfe One additional change to allow a single value to the "format" command
to apply to both column widths.
2020-02-10 09:17:45 -05:00
Tim Edwards 9a1e295367 Based on code from John Wood, added command "netgen::format <col1_width>
<col2_width>" to set the output format width, to avoid the fixed column
widths of 41 characters which can truncate long strings in the output
such as deep cell hierarchies.  This command can be placed in the setup
script to widen the output columns to accomodate the result (to-do:
provide an "auto" mode to automatically determine the best width).
2020-02-10 09:11:34 -05:00
Tim Edwards 942f421fa3 "ocd_git_pure automatic update to repo" 2020-01-30 03:01:39 -05:00
Tim Edwards 6bc948d8ba Merge branch 'master' into netgen-1.5 2020-01-30 03:01:38 -05:00
Tim Edwards d7272e4ea1 One correction to a variable not pointing to the correct distributed
install location for --with-distdir.
2020-01-28 13:51:23 -05:00
Tim Edwards 7f4b5817e2 Corrected configure.in to correctly use withval for setting the
with-distdir option.
2020-01-28 13:48:24 -05:00
Tim Edwards b5ab38d5d7 Added a distributed install option "--with-distdir=" which replaces
"prefix" with the specified path during install, so that netgen can
be installed in a separate location to be migrated to the final
install location, without appending the entire install path to
DESTDIR.
2020-01-28 10:49:42 -05:00
Tim Edwards c1ad37f05a "ocd_git_pure automatic update to repo" 2020-01-14 03:00:47 -05:00
Tim Edwards 9edefe7d59 Merge branch 'master' into netgen-1.5 2020-01-14 03:00:47 -05:00
Tim Edwards bf671937b9 Changed the behavior with respect to backslashes in the JSON so that
they are converted to the double-backslash escape that is the proper
JSON syntax for backslashes, instead of being removed, which changes
the name and can be confusing.
2020-01-13 09:03:36 -05:00
Tim Edwards a16086d2e9 Added handling of backslash characters in instance names in the
JSON output.  Previously, only net names were checked for
backslash characters.
2020-01-13 09:00:48 -05:00
Tim Edwards f6b9629521 "ocd_git_pure automatic update to repo" 2019-11-20 03:00:33 -05:00
Tim Edwards 7b2e01f2af Merge branch 'master' into netgen-1.5 2019-11-20 03:00:33 -05:00
Tim Edwards 0e03f0bf97 Corrected an error that allows a variable to be used uninitialized
in parallel_sort, resulting in a (potentially intermittant)
segfault condition.
2019-11-19 11:45:49 -05:00
Tim Edwards 224050f153 "ocd_git_pure automatic update to repo" 2019-10-09 03:00:08 -04:00
Tim Edwards 74e8c3e168 Merge branch 'master' into netgen-1.5 2019-10-09 03:00:08 -04:00
Tim Edwards f12d03fcff Corrected the verilog parser for handling parameters and parameters
with increment/decrement syntax at the end.  Also the parser now
handles additional keywords associated with behavioral verilog
(initial, specify) and flags modules with them as black-box entries.
2019-10-08 12:18:13 -04:00
Tim Edwards 95a29fcd8c "ocd_git_pure automatic update to repo" 2019-09-11 03:00:07 -04:00
Tim Edwards 723a950fd3 Merge branch 'master' into netgen-1.5 2019-09-11 03:00:07 -04:00
Tim Edwards f04c72b984 Corrected missing case (greater-than or equal instead of greater than)
that affects vectors sliced across instance arrays.  Can cause vector
numbers to be out-of-bounds if an instance is arrayed but each
instance is listed separately.
2019-09-10 10:52:15 -04:00
Tim Edwards e3368cb22a "ocd_git_pure automatic update to repo" 2019-09-10 03:00:08 -04:00
Tim Edwards f06e6548bb Merge branch 'master' into netgen-1.5 2019-09-10 03:00:08 -04:00
Tim Edwards d38bd77825 Additional fixes to the verilog parser, including handling the
inline-I/O syntax with "wire" (e.g., "input wire [3:0] test")
and addressed the failure to add buses declared in inline I/O
to the list of known buses.
2019-09-09 13:42:21 -04:00
Tim Edwards ea4083893c A fairly large refactoring of the conditional handling code in the
verilog parser.  The parser should now be able to handle any
conditionals anywhere in the verilog code.  Also a bug was found
in the code that handles "a = b" assignments, and corrected.
2019-09-09 11:26:31 -04:00
Tim Edwards 72ed19ff36 "ocd_git_pure automatic update to repo" 2019-09-09 03:00:10 -04:00
Tim Edwards 39b8e3d14a Merge branch 'master' into netgen-1.5 2019-09-09 03:00:10 -04:00
Tim Edwards 3dc70148d1 Added support in the verilog parser for definitions anywhere in the
code using the backtick expression.  Also expanded the parsing of
"ifdef", "ifndef", and "endif" to include "elsif" and "else".  All
forms of "if" statements should now be handled, since verilog does
not define boolean expressions in ifdef operators like most languages
do.
2019-09-08 19:59:27 -04:00
Tim Edwards b63dfa8638 "ocd_git_pure automatic update to repo" 2019-08-20 03:00:20 -04:00
Tim Edwards f918f33c51 Merge branch 'master' into netgen-1.5 2019-08-20 03:00:20 -04:00
Tim Edwards a8576d26a9 Modified the netgen token parser, which (unwisely) is used both for
SPICE and verilog, in spite of the syntactical differences, to
account for the trick that qflow uses to replace the trailing space
in a verilog backslash-escaped name with a second backslash to get
a SPICE-compatible name that can be easily converted back to its
original verilog name without loss of information.  What this means
is that verilog can read SPICE files containing verilog names (which
is illegal SPICE) and verilog files containing hacked-backslash
names (which is illegal verilog).  This should be mostly harmless
although the wisdom of it is surely questionable.
2019-08-19 17:06:05 -04:00
Tim Edwards 63b2e48ea1 "ocd_git_pure automatic update to repo" 2019-08-13 03:00:08 -04:00
Tim Edwards 6e63f49d53 Merge branch 'master' into netgen-1.5 2019-08-13 03:00:07 -04:00
Tim Edwards a31390f152 Some corrections and updates to the commit of a few days ago to
handle wire bundles in wire assignments and pin connections.
Also corrected an error in which a comment after a wire statement
causes parsing issues.
2019-08-12 13:58:19 -04:00
Tim Edwards 419b6de29a "ocd_git_pure automatic update to repo" 2019-08-11 03:00:07 -04:00
Tim Edwards 205cf2aa58 Merge branch 'master' into netgen-1.5 2019-08-11 03:00:07 -04:00
Tim Edwards 44ec952872 Expanded the verilog parser to handle most forms of allowable wire and
assignment statements in verilog netlists, including assignment of
signal bundles.  Also corrected handling of signal bundles in pin
connections, which had been corrected in qflow's verilog parser but
not copied back to netgen.  Note that the syntax for signals multiplied
N times is still not handled.
2019-08-10 22:30:57 -04:00
Tim Edwards 52b6766fc8 "ocd_git_pure automatic update to repo" 2019-08-04 03:00:20 -04:00
Tim Edwards 7b0bdd29e8 Merge branch 'master' into netgen-1.5 2019-08-04 03:00:20 -04:00
Roman-Parise 3892529873 Removed generated files and edited .gitignore 2019-08-03 16:27:13 -04:00
Roman-Parise e3b51c6004 Fixed configure scripts for FreeBSD builds 2019-08-03 16:24:24 -04:00
Roman-Parise 3200b1bf95 Added FreeBSD installation comment to README. 2019-08-03 16:24:24 -04:00
Tim Edwards 814652e552 Updated tkcon.tcl, which was not corrected for a minor problem that
affects use with Tcl/Tk 8.6 (text option "-under" not recognized;
must be "-underline").
2019-08-03 16:22:26 -04:00
Tim Edwards 433cbd090a "ocd_git_pure automatic update to repo" 2019-07-25 03:00:16 -04:00
Tim Edwards 3087bd3337 Merge branch 'master' into netgen-1.5 2019-07-25 03:00:16 -04:00
Tim Edwards 4d138b64ca Corrected a missing "#ifdef TCL_NETGEN" around a Tcl subroutine
call, in objlist.c.
2019-07-24 11:13:25 -04:00
Tim Edwards b79a29d662 "ocd_git_pure automatic update to repo" 2019-07-15 03:00:27 -04:00
Tim Edwards bf9c61e412 Merge branch 'master' into netgen-1.5 2019-07-15 03:00:27 -04:00
Tim Edwards 9a2902abbb Removed "makedbh", which was copied from Magic (a long, long time
ago) when building out the netgen Makefile, and never removed.  The
script is very specific to Magic.
2019-07-14 09:39:39 -04:00
Tim Edwards 8d34bd372d "ocd_git_pure automatic update to repo" 2019-07-03 03:00:22 -04:00
Tim Edwards 229c2931a8 Merge branch 'master' into netgen-1.5 2019-07-03 03:00:22 -04:00
Tim Edwards 840f997133 Corrected a typo that somehow crept into the verilog delimiter set,
replacing the semicolon with a colon, which basically hoses the
verilog parser.
2019-07-02 10:45:10 -04:00
Tim Edwards b8da97deb1 "ocd_git_pure automatic update to repo" 2019-06-16 03:00:15 -04:00
Tim Edwards b7187d5899 Merge branch 'master' into netgen-1.5 2019-06-16 03:00:15 -04:00
Tim Edwards cb3cf592e8 Corrected the arguments to the configure script from the top-level
wrapper.
2019-06-15 12:43:13 -04:00
Tim Edwards b1d40e6d12 Corrected an error in the "permute forget" Tcl command option that
would attempt to access uninitialized variables, possibly causing
a crash.
2019-06-15 12:29:08 -04:00
Tim Edwards edbefbd1c4 Corrected an error in handling partial buses connected to a
full-bus pin in a module instance.
2019-06-15 03:05:50 -04:00
Tim Edwards d27d441c58 "ocd_git_pure automatic update to repo" 2019-06-13 03:00:05 -04:00
Tim Edwards 48c9e6b292 Merge branch 'master' into netgen-1.5 2019-06-13 03:00:05 -04:00
Tim Edwards 527cdb3dab Corrected error in detecting S and M. 2019-06-12 11:11:28 -04:00
Tim Edwards ced5846da3 "ocd_git_pure automatic update to repo" 2019-05-18 03:00:05 -04:00
Tim Edwards b99d33064f Merge branch 'master' into netgen-1.5 2019-05-18 03:00:04 -04:00
Tim Edwards ee66c00121 Further refined the last commit based on the change in definition of
a "critical property".  This lets a device define multiple critical
properties, all of which must match before additive properties can
be combined in the same device.
2019-05-17 14:33:26 -04:00
Tim Edwards f40a50d3b8 Corrected property value merging (again). By the rules of the
re-worked property command, "critical" properties must match
across devices so that all other properties can be combined as
specified (addition, parallel combination, or none).  The code was
still based on the older notion of the "critical" property being
the one to add (and thus preventing multiple properties from being
added in different ways).  This has now been fixed.
2019-05-17 11:25:34 -04:00
Tim Edwards 399472e940 "ocd_git_pure automatic update to repo" 2019-05-07 09:13:00 -04:00
Tim Edwards 8e0371e09b Corrected handling of verilog backslash-escaped names in the
verilog netlist parser.
2019-05-05 10:52:07 -04:00
Tim Edwards 395f857a82 Merge branch 'master' into work 2019-01-21 20:30:42 -05:00
Tim Edwards 9e59048731 Update at Mon Jan 21 20:30:40 EST 2019 by tim 2019-01-21 20:30:40 -05:00
Tim Edwards 7889e2ae73 Small typo, large effect; wrong reference to ob1 (instead of ob2) in
flatten.c can cause a segfault when analyzing whether flattening
cells generates a better circuit match.
2019-01-21 20:29:42 -05:00
Tim Edwards 8c7d2ae239 Merge branch 'master' into work 2019-01-09 20:31:57 -05:00
Tim Edwards e361640947 Update at Wed Jan 9 20:31:54 EST 2019 by tim 2019-01-09 20:31:54 -05:00
Tim Edwards 56b4174646 Fairly substantial overhaul of the tokenizing routine to better
handle verilog syntax.  Also:  Added SPICE voltage and current
sources as separate classes (as opposed to being converted to
subcircuits, which was how they were previously handled).  That
allowed voltage sources to be checked for zero value and removed
by shorting the ends together, as was being done for zero value
resistors (note that like zero-value resistors, removal is only
done if removing the component makes a better match than leaving
it in).  In particular, yosys has SPICE netlist output that
converts equality assignments ("assign a = b") into zero-value
voltage sources, so these components need to be treated as
non-physical elements.
2019-01-09 20:26:38 -05:00
Tim Edwards ccf2dc23c9 Merge branch 'master' into work 2018-11-19 08:12:59 -05:00
Tim Edwards f8ea27d8e8 Update at Mon Nov 19 08:12:57 EST 2018 by tim 2018-11-19 08:12:57 -05:00
Tim Edwards ef914e8d46 Corrected two instances of missing values on return from a function. 2018-11-19 08:12:12 -05:00
Tim Edwards f9cc4d3db6 Merge branch 'master' into work 2018-11-18 13:09:58 -05:00
Tim Edwards d8eefdad9a Update at Sun Nov 18 13:09:56 EST 2018 by tim 2018-11-18 13:09:56 -05:00
Tim Edwards 2cdf3c450f Extended the series/parallel merging setup commands to include
the possibility that a device (e.g., resistor or capacitor) may
not be a semiconductor device (in other words, a parasitic or
ideal device), and therefore uses "value" but not width and
length, and therefore "value" is a critical property to merge
both in series and parallel.  Corrected the series/parallel
network optimization to prevent it from setting both M and S
records > 1 on the same device (which is ambiguous).  To try
to get number of devices to match, where there are both series
and parallel devices, they will be merged across the critical
property early (before property matching).
2018-11-18 13:04:57 -05:00
Tim Edwards 079e0ab5d3 Corrected an error in the handling of node names in verilog that was
accidentally erasing array delimiters from node names, a move that
surprisingly has no effect at all on LVS until the cell containing
the truncated nodes is flattened, at which point it causes odd and
confusing behavior that seems to have nothing to do with node names
at all.
2018-11-14 19:53:19 -05:00
Tim Edwards f0cf6b52d3 Merge branch 'master' into work 2018-11-14 13:46:14 -05:00
Tim Edwards 9432bfc182 Update at Wed Nov 14 13:46:12 EST 2018 by tim 2018-11-14 13:46:12 -05:00
Tim Edwards 4fb892a64f Fixed configure script error that reports python3 as being
configured even when it is not found on the system.  This was only
a reporting error, and had no other repercussions.
2018-11-14 13:45:02 -05:00
38 changed files with 4556 additions and 6172 deletions
+40
View File
@@ -0,0 +1,40 @@
# This is a basic workflow to help you get started with Actions
name: CI
# Controls when the workflow will run
on:
# Triggers the workflow on push or pull request events but only for the master branch
push:
branches: [ master ]
pull_request:
branches: [ master ]
# Allows you to run this workflow manually from the Actions tab
workflow_dispatch:
# A workflow run is made up of one or more jobs that can run sequentially or in parallel
jobs:
# This workflow contains a single job called "build"
build:
# The type of runner that the job will run on
runs-on: ubuntu-latest
# Steps represent a sequence of tasks that will be executed as part of the job
steps:
# Runs a set of commands using the runners shell
#- name: Logging into Dockerhub
# run: docker login -u ${{ secrets.DOCKERHUB_USERNAME }} -p ${{ secrets.DOCKERHUB_PASSWORD }}
- name: Pulling the docker image
run: docker pull vezzal/vezzal:v1
- name: Start the container with the docker image
run: docker run -id --name test_netgen vezzal/vezzal:v1 bash | exit
- name: Run the testing on the container and send the mail
run: docker exec test_netgen /vezzal/test_netgen.sh "[email protected],[email protected]" ${{ secrets.MAILING_KEY }}
+5 -1
View File
@@ -1,12 +1,16 @@
netgen
netgenexec
defs.mak
scripts/defs.mak
config.cache
config.log
scripts/config.log
config.status
scripts/config.status
*.o
*.so
*~
*.log
UPDATE_ME
VERSION
tcltk/netgen.sh
tcltk/netgen.tcl
+8 -8
View File
@@ -9,7 +9,7 @@ MODULES = base
MAKEFLAGS =
INSTALL_CAD_DIRS = lib doc
include defs.mak
-include defs.mak
all: $(ALL_TARGET)
@@ -51,8 +51,8 @@ depend:
install: $(INSTALL_TARGET)
install-netgen:
@echo --- installing executable to $(DESTDIR)${BINDIR}
@echo --- installing run-time files to $(DESTDIR)${LIBDIR}
@echo --- installing executable to $(DESTDIR)${INSTALL_BINDIR}
@echo --- installing run-time files to $(DESTDIR)${INSTALL_LIBDIR}
@${MAKE} install-real >> install.log
install-real: install-dirs
@@ -60,15 +60,15 @@ install-real: install-dirs
(cd $$dir && ${MAKE} install); done
install-tcl-dirs:
${NETGENDIR}/scripts/mkdirs $(DESTDIR)${BINDIR} \
$(DESTDIR)${TCLDIR} $(DESTDIR)${PYDIR}
${NETGENDIR}/scripts/mkdirs $(DESTDIR)${INSTALL_BINDIR} \
$(DESTDIR)${INSTALL_TCLDIR} $(DESTDIR)${INSTALL_PYDIR}
install-dirs:
${NETGENDIR}/scripts/mkdirs $(DESTDIR)${BINDIR}
${NETGENDIR}/scripts/mkdirs $(DESTDIR)${INSTALL_BINDIR}
install-tcl: install-dirs
@echo --- installing executable to $(DESTDIR)${BINDIR}
@echo --- installing run-time files to $(DESTDIR)${LIBDIR}
@echo --- installing executable to $(DESTDIR)${INSTALL_BINDIR}
@echo --- installing run-time files to $(DESTDIR)${INSTALL_LIBDIR}
@${MAKE} install-tcl-real 2>&1 >> install.log
install-tcl-real: install-tcl-dirs
+7 -1
View File
@@ -1,4 +1,8 @@
NETGEN: VERSION 1.5
![Continuous Integration](https://github.com/RTimothyEdwards/netgen/actions/workflows/main.yml/badge.svg)
# NETGEN
### VERSION 1.5
NETGEN is a general-purpose netlist management system. It can read
and write several netlist formats, including NTK (Caltech, CMU),
@@ -85,6 +89,8 @@ and IRSIM version 9.7:
make
make install
Note: For FreeBSD, use 'gmake' instead.
IN CASE OF FAILURE
-------------------
Please contact me (tim@opencircuitdesign.com) to report compile-time and
+1 -1
View File
@@ -1 +1 @@
1.5.112
1.5.201
+342 -218
View File
@@ -193,17 +193,19 @@ void flattenCell(char *name, int file)
if (Debug) Printf("Renaming %s to %s\n", tmp->name, tmpstr);
FreeString(tmp->name);
tmp->name = strsave(tmpstr);
#if OLDPREFIX
sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
tmp->instance.name);
#else
strcpy(tmpstr+prefixlength,tmp->instance.name);
#endif
FreeString(tmp->instance.name);
tmp->instance.name = strsave(tmpstr);
HashPtrInstall(tmp->name, tmp, &(ThisCell->objdict));
if (tmp->type == FIRSTPIN)
HashPtrInstall(tmp->instance.name, tmp, &(ThisCell->instdict));
if ((tmp->type != NODE) && (tmp->instance.name != NULL)) {
#if OLDPREFIX
sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
tmp->instance.name);
#else
strcpy(tmpstr+prefixlength,tmp->instance.name);
#endif
FreeString(tmp->instance.name);
tmp->instance.name = strsave(tmpstr);
if (tmp->type == FIRSTPIN)
HashPtrInstall(tmp->instance.name, tmp, &(ThisCell->instdict));
}
}
/* splice instance out of parent */
@@ -252,14 +254,15 @@ void flattenCell(char *name, int file)
int flattenInstancesOf(char *name, int fnum, char *instance)
{
struct objlist *ParentParams;
struct objlist *ParentProps;
struct objlist *NextObj;
struct objlist *ChildObjList;
struct objlist *ParentProps, *CurrentProp;
struct objlist *NextObj, *LastObj, *prepp;
struct objlist *ChildObjList, *ChildListEnd;
struct objlist *ChildStart, *ChildEnd, *ParentEnd, *ParentNext;
struct nlist *ThisCell;
struct nlist *ChildCell;
struct objlist *tmp, *ob2, *ob3;
int notdone, rnodenum;
char tmpstr[200];
char tmpstr[1024];
int nextnode, oldmax, numflat = 0;
#if !OLDPREFIX
int prefixlength;
@@ -296,21 +299,35 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
while (notdone) {
notdone = 0;
ParentParams = ThisCell->cell;
LastObj = NULL;
for (ParentParams = ThisCell->cell; ParentParams != NULL;
ParentParams = NextObj) {
ParentParams = NextObj) {
if (Debug) Printf("Parent = %s, type = %d\n",
ParentParams->name, ParentParams->type);
NextObj = ParentParams->next;
if (ParentParams->type != FIRSTPIN) continue;
if (!(*matchfunc)(ParentParams->model.class, instance)) continue;
if (ParentParams->type != FIRSTPIN) {
LastObj = ParentParams;
continue;
}
if (!(*matchfunc)(ParentParams->model.class, instance)) {
LastObj = ParentParams;
continue;
}
ChildCell = LookupCellFile(ParentParams->model.class, ThisCell->file);
if (Debug)
Printf(" Flattening instance: %s, primitive = %s\n",
ParentParams->instance.name, (ChildCell->class ==
CLASS_SUBCKT) ? "no" : "yes");
if (ChildCell->class != CLASS_SUBCKT) continue;
if (ChildCell == ThisCell) continue; // Avoid infinite loop
if ((ChildCell->class != CLASS_SUBCKT) && (ChildCell->class != CLASS_MODULE)) {
LastObj = ParentParams;
continue;
}
if (ChildCell == ThisCell) {
LastObj = ParentParams;
continue; // Avoid infinite loop
}
/* Does the parent cell have properties? If so, save a pointer to them */
for (ParentProps = ParentParams->next; ParentProps &&
@@ -318,202 +335,264 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
ParentProps = ParentProps->next) {
if (ParentProps->type == PROPERTY) break;
}
if (ParentProps && (ParentProps->type != PROPERTY)) ParentProps = NULL;
/* not primitive, so need to flatten this instance */
notdone = 1;
/* if this is a new instance, flatten it */
/* if (ChildCell->dumped == 0) flattenCell(ParentParams->model.class, file); */
ChildObjList = CopyObjList(ChildCell->cell, 1);
numflat++;
/* update node numbers in child to unique numbers */
oldmax = 0;
for (tmp = ChildObjList; tmp != NULL; tmp = tmp->next)
if (tmp->node > oldmax) oldmax = tmp->node;
if (nextnode <= oldmax) nextnode = oldmax + 1;
for (tmp = ChildObjList; tmp != NULL; tmp = tmp->next)
if (tmp->node <= oldmax && tmp->node > 0) {
if (Debug) Printf("Update node %d --> %d\n", tmp->node, nextnode);
UpdateNodeNumbers(ChildObjList, tmp->node, nextnode);
nextnode++;
}
/* copy nodenumbers of ports from parent */
ob2 = ParentParams;
for (tmp = ChildObjList; tmp != NULL; tmp = tmp->next)
if (IsPort(tmp)) {
if (tmp->node > 0) {
if (ob2->node == -1) {
// Before commiting to attaching to a unconnected node, see
// if there is another node in ParentParams with the same
// name and a valid node number. If so, connect them. In
// the broader case, it may be necessary to consider all
// nodes, not just those with node == -1, and call join()
// here to update all node numbers in the parent cell.
// In that case, a more efficient method is needed for
// tracking same-name ports.
for (ob3 = ParentParams; ob3 && ob3->type >= FIRSTPIN; ob3 = ob3->next) {
if (ob3 == ob2) continue;
if ((*matchfunc)(ob3->name, ob2->name) && ob3->node != -1) {
ob2->node = ob3->node;
break;
}
}
}
if (Debug) {
// Printf(" Sealing port: %d to node %d\n", tmp->node, ob2->node);
Printf("Update node %d --> %d\n", tmp->node, ob2->node);
}
UpdateNodeNumbers(ChildObjList, tmp->node, ob2->node);
}
/* in pathological cases, the lengths of the port lists may
change. This is an error, but that is no reason to allow
the code to core dump. We avoid this by placing a
superfluous check on ob2->type
*/
if (ob2 != NULL)
ob2 = ob2->next;
if (ob2 == NULL) break;
}
/* Using name == NULL to indicate that a .ext file is being */
/* flattened on the fly. This is quick & dirty. */
if (name != NULL) {
/* delete all port elements from child */
while ((ChildObjList != NULL) && IsPort(ChildObjList)) {
/* delete all ports at beginning of list */
if (Debug) Printf("deleting leading port from child\n");
tmp = ChildObjList->next;
// FreeObjectAndHash(ChildObjList, ChildCell);
FreeObject(ChildObjList);
ChildObjList = tmp;
}
tmp = ChildObjList;
while (tmp && (tmp->next != NULL)) {
if (IsPort(tmp->next)) {
ob2 = (tmp->next)->next;
if (Debug) Printf("deleting a port from child\n");
// FreeObjectAndHash(tmp->next, ChildCell);
FreeObject(tmp->next);
tmp->next = ob2;
}
else tmp = tmp->next;
}
if (ParentProps && (ParentProps->type != PROPERTY)) {
ParentProps = NULL;
CurrentProp = NULL;
}
else
CurrentProp = ParentProps;
/* for each element in child, prepend 'prefix' */
/* Find the end record of the parent cell and save it */
for (ParentEnd = (ParentProps) ? ParentProps : ParentParams;
ParentEnd && ParentEnd->next &&
/* Stop on a node or the next instance */
((ParentEnd->next->type > FIRSTPIN) ||
(ParentEnd->next->type == PROPERTY));
ParentEnd = ParentEnd->next);
/* Not primitive, so need to flatten this instance */
notdone = 1;
/* Loop over property records. Need to flatten once per */
/* property record (or more, if property has M > 1) */
ob2 = NULL;
ChildObjList = NULL;
ChildListEnd = NULL;
while (1) {
ChildStart = CopyObjList(ChildCell->cell, 1);
numflat++;
/* Find the end record of the child cell and save it */
for (ChildEnd = ChildStart; ChildEnd && ChildEnd->next;
ChildEnd = ChildEnd->next);
if (ChildListEnd == NULL) ChildListEnd = ChildEnd;
/* update node numbers in child to unique numbers */
oldmax = 0;
for (tmp = ChildStart; tmp != NULL; tmp = tmp->next)
if (tmp->node > oldmax) oldmax = tmp->node;
if (nextnode <= oldmax) nextnode = oldmax + 1;
for (tmp = ChildStart; tmp != NULL; tmp = tmp->next)
if (tmp->node <= oldmax && tmp->node > 0) {
if (Debug) Printf("Update node %d --> %d\n", tmp->node, nextnode);
UpdateNodeNumbers(ChildStart, tmp->node, nextnode);
nextnode++;
}
/* copy nodenumbers of ports from parent */
ob2 = ParentParams;
for (tmp = ChildStart; tmp != NULL; tmp = tmp->next) {
if (IsPort(tmp)) {
if (tmp->node > 0) {
if (ob2->node == -1) {
// Before commiting to attaching to a unconnected node, see
// if there is another node in ParentParams with the same
// name and a valid node number. If so, connect them. In
// the broader case, it may be necessary to consider all
// nodes, not just those with node == -1, and call join()
// here to update all node numbers in the parent cell.
// In that case, a more efficient method is needed for
// tracking same-name ports.
for (ob3 = ParentParams; ob3 && ob3->type >= FIRSTPIN;
ob3 = ob3->next) {
if (ob3 == ob2) continue;
if ((*matchfunc)(ob3->name, ob2->name) && ob3->node != -1) {
ob2->node = ob3->node;
break;
}
}
}
if (Debug) {
// Printf(" Sealing port: %d to node %d\n", tmp->node, ob2->node);
Printf("Update node %d --> %d\n", tmp->node, ob2->node);
}
UpdateNodeNumbers(ChildStart, tmp->node, ob2->node);
}
/* in pathological cases, the lengths of the port lists may
* change. This is an error, but that is no reason to allow
* the code to core dump. We avoid this by placing a
* superfluous check on ob2->type
*/
if (ob2 != NULL) ob2 = ob2->next;
if (ob2 == NULL) break;
}
}
/* Using name == NULL to indicate that a .ext file is being */
/* flattened on the fly. This is quick & dirty. */
if (name != NULL) {
/* delete all port elements from child */
while ((ChildStart != NULL) && IsPort(ChildStart)) {
/* delete all ports at beginning of list */
if (Debug) Printf("deleting leading port from child\n");
tmp = ChildStart->next;
FreeObject(ChildStart);
ChildStart = tmp;
}
tmp = ChildStart;
while (tmp && (tmp->next != NULL)) {
if (IsPort(tmp->next)) {
ob2 = (tmp->next)->next;
if (Debug) Printf("deleting a port from child\n");
FreeObject(tmp->next);
tmp->next = ob2;
}
else tmp = tmp->next;
}
if (ChildStart == NULL) {
if (ChildListEnd == ChildEnd) ChildListEnd = NULL;
ChildEnd = NULL;
}
}
/* for each element in child, prepend 'prefix' */
#if !OLDPREFIX
/* replaces all the sprintf's below */
strcpy(tmpstr,ParentParams->instance.name);
strcat(tmpstr,SEPARATOR);
prefixlength = strlen(tmpstr);
/* replaces all the sprintf's below */
strcpy(tmpstr,ParentParams->instance.name);
strcat(tmpstr,SEPARATOR);
prefixlength = strlen(tmpstr);
#endif
for (tmp = ChildObjList; tmp != NULL; tmp = tmp->next) {
if (tmp->type == PROPERTY)
continue;
for (tmp = ChildStart; tmp != NULL; tmp = tmp->next) {
if (tmp->type == PROPERTY)
continue;
else if (IsGlobal(tmp)) {
/* Keep the name but search for node of same name in parent */
/* and replace the node number, if found. */
else if (IsGlobal(tmp)) {
/* Keep the name but search for node of same name in parent */
/* and replace the node number, if found. */
for (ob2 = ThisCell->cell; ob2 != NULL; ob2 = ob2->next) {
/* Type in parent may be a port, not a global */
if (ob2->type == tmp->type || ob2->type == PORT) {
if ((*matchfunc)(tmp->name, ob2->name)) {
if (ob2->node >= 0) {
// Replace all child objects with this node number
rnodenum = tmp->node;
for (ob3 = ChildObjList; ob3 != NULL; ob3 = ob3->next) {
if (ob3->node == rnodenum)
ob3->node = ob2->node;
}
break;
}
}
}
}
// Don't hash this if the parent had a port of this name
if (!ob2 || ob2->type != PORT)
HashPtrInstall(tmp->name, tmp, &(ThisCell->objdict));
continue;
}
for (ob2 = ThisCell->cell; ob2 != NULL; ob2 = ob2->next) {
/* Type in parent may be a port, not a global */
if (ob2->type == tmp->type || ob2->type == PORT) {
if ((*matchfunc)(tmp->name, ob2->name)) {
if (ob2->node >= 0) {
// Replace all child objects with this node number
rnodenum = tmp->node;
for (ob3 = ChildStart; ob3 != NULL; ob3 = ob3->next) {
if (ob3->node == rnodenum)
ob3->node = ob2->node;
}
break;
}
}
}
}
// Don't hash this if the parent had a port of this name
if (!ob2 || ob2->type != PORT)
HashPtrInstall(tmp->name, tmp, &(ThisCell->objdict));
continue;
}
#if OLDPREFIX
sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
tmp->name);
sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
tmp->name);
#else
strcpy(tmpstr+prefixlength,tmp->name);
strcpy(tmpstr+prefixlength,tmp->name);
#endif
if (Debug) Printf("Renaming %s to %s\n", tmp->name, tmpstr);
FreeString(tmp->name);
tmp->name = strsave(tmpstr);
if (Debug) Printf("Renaming %s to %s\n", tmp->name, tmpstr);
FreeString(tmp->name);
tmp->name = strsave(tmpstr);
HashPtrInstall(tmp->name, tmp, &(ThisCell->objdict));
if ((tmp->type != NODE) && (tmp->instance.name != NULL)) {
#if OLDPREFIX
sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
tmp->instance.name);
sprintf(tmpstr, "%s%s%s", ParentParams->instance.name, SEPARATOR,
tmp->instance.name);
#else
strcpy(tmpstr+prefixlength,tmp->instance.name);
strcpy(tmpstr+prefixlength,tmp->instance.name);
#endif
FreeString(tmp->instance.name);
tmp->instance.name = strsave(tmpstr);
HashPtrInstall(tmp->name, tmp, &(ThisCell->objdict));
if (tmp->type == FIRSTPIN)
HashPtrInstall(tmp->instance.name, tmp, &(ThisCell->instdict));
}
/* Do property inheritance */
if (ParentProps) {
for (ob2 = ChildObjList; ob2 != NULL; ob2=ob2->next) {
/* If the parent cell has properties to declare, then */
/* pass them on to children. Use globals only if the */
/* spiceparams dictionary is active (during file reading */
/* only). */
if (ob2->type == PROPERTY)
ReduceExpressions(ob2, ParentProps, ChildCell,
(spiceparams.hashtab == NULL) ? 0 : 1);
FreeString(tmp->instance.name);
tmp->instance.name = strsave(tmpstr);
if (tmp->type == FIRSTPIN)
HashPtrInstall(tmp->instance.name, tmp, &(ThisCell->instdict));
}
}
/* Do property inheritance */
/* NOTE: Need to do: Check properties for M > 1 and decrement
* and repeat without moving CurrentProp
*/
if (CurrentProp) {
for (ob2 = ChildStart; ob2 != NULL; ob2=ob2->next) {
/* If the parent cell has properties to declare, then */
/* pass them on to children. Use globals only if the */
/* spiceparams dictionary is active (during file */
/* reading only). */
if (ob2->type == PROPERTY)
ReduceExpressions(ob2, CurrentProp, ChildCell,
(spiceparams.hashtab == NULL) ? 0 : 1);
}
/* Repeat for each property record, as each property represents a
* unique instance that must be flattened individually.
*/
CurrentProp = CurrentProp->next;
if ((CurrentProp == NULL) || (CurrentProp->type != PROPERTY)) break;
}
else break;
/* Put the child cell at the start of ChildObjList */
ChildEnd->next = ChildObjList;
ChildObjList = ChildStart;
}
/* splice instance out of parent */
if ((ParentParams == ThisCell->cell) && (ChildObjList == NULL)) {
ThisCell->cell = ob2; /* Child cell was empty */
tmp = ob2;
/* Put the child cell at the start of ChildObjList */
if (ChildEnd) {
ChildEnd->next = ChildObjList;
ChildObjList = ChildStart;
}
else {
/* Pull the instance out of the parent */
if ((ParentParams != ThisCell->cell) || (ChildObjList != NULL)) {
if (ParentParams == ThisCell->cell) {
/* ParentParams are the very first thing in the list */
ThisCell->cell = ChildObjList;
for (ob2 = ChildObjList; ob2 && ob2->next != NULL; ob2 = ob2->next) ;
/* ParentParams are the very first thing in the list */
ThisCell->cell = ChildObjList;
}
else {
/* find ParentParams in ThisCell list */
for (ob2 = ThisCell->cell; ob2 && ob2->next != ParentParams; ob2=ob2->next);
if (ob2)
for (ob2->next = ChildObjList; ob2->next != NULL; ob2 = ob2->next) ;
else if (ChildObjList) {
/* find ParentParams in ThisCell list. In most cases, LastObj */
/* should be pointing to it. */
if (LastObj && (LastObj->next == ParentParams)) {
LastObj->next = ChildObjList;
}
else {
for (ob2 = LastObj; ob2 && ob2->next != ParentParams;
ob2 = ob2->next);
if (ob2 == NULL) {
/* It should not happen that LastObj is ahead of ParentParams */
/* but just in case, this long loop will find it. */
for (ob2 = ThisCell->cell; ob2 && ob2->next != ParentParams;
ob2 = ob2->next);
}
ob2->next = ChildObjList;
}
}
/* now, ob2 is last element in child list, so skip and reclaim parent */
else {
/* The child was completely optimized out, so close list around it */
LastObj->next = ParentEnd->next;
}
tmp = ParentParams;
do {
tmp = tmp->next;
} while ((tmp != NULL) && ((tmp->type > FIRSTPIN) || (tmp->type == PROPERTY)));
if (ob2) ob2->next = tmp;
/* Link end of child list into the parent */
if (ChildListEnd && ParentEnd)
ChildListEnd->next = ParentEnd->next;
}
while (ParentParams != tmp) {
ob2 = ParentParams->next;
FreeObjectAndHash(ParentParams, ThisCell);
ParentParams = ob2;
ParentNext = (ParentEnd) ? ParentEnd->next : NULL;
while (ParentParams != ParentNext) {
ob2 = ParentParams->next;
FreeObjectAndHash(ParentParams, ThisCell);
ParentParams = ob2;
}
NextObj = ParentParams;
} /* repeat until no more instances found */
@@ -1136,9 +1215,10 @@ int UniquePins(char *name, int filenum)
struct nlist *cleanuppins(struct hashlist *p, void *clientdata)
{
struct nlist *ptr;
struct objlist *ob, *obt, *lob, *nob, *firstpin;
struct objlist *ob, *obt, *lob, *nob, *firstpin, *pob;
struct nlist *tc = (struct nlist *)clientdata;
int pinnum;
char *saveinst = NULL;
ptr = (struct nlist *)(p->ptr);
if (tc->file != ptr->file) return NULL;
@@ -1166,7 +1246,7 @@ struct nlist *cleanuppins(struct hashlist *p, void *clientdata)
while (ob && obt && (ob->type > FIRSTPIN || ob == firstpin) &&
ob->model.class != NULL) {
nob = ob->next;
if ((obt->type == PORT) && (obt->node == -1)) {
if ((obt->type == PORT) && (obt->node == -2)) {
/* Remove this pin */
@@ -1186,13 +1266,44 @@ struct nlist *cleanuppins(struct hashlist *p, void *clientdata)
}
FREE(ob->name);
if (ob->instance.name != NULL) FREE(ob->instance.name);
if (ob->instance.name != NULL) {
/* Keep a copy of the instance name (see below) */
if (saveinst != NULL) FREE(saveinst);
saveinst = ob->instance.name;
}
if (ob->model.class != NULL) FREE(ob->model.class);
FREE(ob);
}
else {
lob = ob;
ob->type = pinnum++; // Renumber pins in order
if ((ob->type == PROPERTY) && (pinnum == 1))
{
/* If this happens, then all the pins got removed,
* and there is probably something very much wrong
* with the setup. However, to keep netgen from
* blowing up, add back a "proxy(no pins)" record
* in front; otherwise we'd have an orphaned
* property record.
*/
pob = GetObject();
pob->name = (char *)MALLOC(15);
sprintf(pob->name, "proxy(no pins)");
pob->model.class = strsave(ob->model.class);
if (saveinst != NULL)
pob->instance.name = strsave(saveinst);
else
/* This should never happen */
pob->instance.name = strsave("error");
pob->type = pinnum++;
pob->node = -1;
pob->next = ob;
lob->next = pob;
lob = ob;
}
else
{
lob = ob;
ob->type = pinnum++; // Renumber pins in order
}
}
ob = nob;
obt = obt->next;
@@ -1203,6 +1314,8 @@ struct nlist *cleanuppins(struct hashlist *p, void *clientdata)
HashPtrInstall(firstpin->instance.name, firstpin, &(ptr->instdict));
}
}
if (saveinst != NULL) FREE(saveinst);
return NULL; /* Keep the search going */
}
@@ -1238,7 +1351,7 @@ int CleanupPins(char *name, int filenum)
for (ob = ThisCell->cell; ob != NULL; ob = ob->next) {
if (ob->type != PORT) break;
if (ob->node == -1) {
if (ob->node == -2) {
needscleanup = 1;
break;
}
@@ -1265,7 +1378,7 @@ int CleanupPins(char *name, int filenum)
}
else if (ob->type != PORT) break;
nob = ob->next;
if (ob->node == -1) {
if (ob->node == -2) {
if (lob == NULL) {
ThisCell->cell = ob->next;
}
@@ -1391,7 +1504,7 @@ SurveyCell(struct nlist *tc, struct hashdict *compdict, int file1, int file2, in
/* */
/* If there is a mismatch between instances of low- */
/* level devices, determine if the mismatches can be */
/* resolved by parallel/serial combining, according to */
/* resolved by parallel/series combining, according to */
/* combination rules. */
/* */
/* Return the number of modifications made. */
@@ -1475,13 +1588,13 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
}
}
if (match) {
if (ecomp->cell1) {
if (ecomp->cell1 && (ecomp->num1 > 0)) {
Fprintf(stdout, "Flattening instances of %s in cell %s"
" makes a better match\n", ecomp->cell1->name,
name1);
flattenInstancesOf(name1, file1, ecomp->cell1->name);
}
if (ecomp->cell2) {
if (ecomp->cell2 && (ecomp->num2 > 0)) {
Fprintf(stdout, "Flattening instances of %s in cell %s"
" makes a better match\n", ecomp->cell2->name,
name2);
@@ -1539,7 +1652,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
/* (it without regard to cell1) improves the matching. */
else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell2 != NULL) &&
(ecomp->cell2->class == CLASS_SUBCKT)) {
(ecomp->num2 != 0) && (ecomp->cell2->class == CLASS_SUBCKT)) {
ecomp->add2 = -ecomp->num2;
match = 1;
for (ob2 = ecomp->cell2->cell; ob2; ob2 = ob2->next) {
@@ -1597,7 +1710,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
/* (it without regard to cell1) improves the matching. */
else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell1 != NULL) &&
(ecomp->cell1->class == CLASS_SUBCKT)) {
(ecomp->num1 != 0) && (ecomp->cell1->class == CLASS_SUBCKT)) {
ecomp->add1 = -ecomp->num1;
match = 1;
for (ob2 = ecomp->cell1->cell; ob2; ob2 = ob2->next) {
@@ -1659,7 +1772,9 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
ecomp = (ECompare *)HashFirst(&compdict);
while (ecomp != NULL) {
if ((ecomp->num1 != ecomp->num2) && (ecomp->cell1 != NULL) &&
(ecomp->cell1->class == CLASS_RES)) {
((ecomp->cell1->class == CLASS_RES) ||
(ecomp->cell1->class == CLASS_VSOURCE) ||
(ecomp->cell1->class == CLASS_ISOURCE))) {
int node1 = -1, node2 = -1;
lob = NULL;
for (ob1 = tc1->cell; ob1; ) {
@@ -1703,16 +1818,21 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
if (found) break;
}
if (found) {
Fprintf(stdout, "Removing zero-valued device"
Fprintf(stdout, "Removing zero-valued device "
"%s from cell %s makes a better match\n",
tsub1->name,
tc1->name);
/* merge node of endpoints */
for (ob2 = tc1->cell; ob2; ob2 = ob2->next) {
if (ob2->node == node2)
ob2->node = node1;
}
/* A current source is an open, while a */
/* resistor or voltage source is a short. */
if (ecomp->cell1->class != CLASS_ISOURCE) {
/* merge node of endpoints */
for (ob2 = tc1->cell; ob2; ob2 = ob2->next) {
if (ob2->node == node2)
ob2->node = node1;
}
}
/* snip, snip. Excise this device */
if (lob == NULL) {
@@ -1763,7 +1883,9 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
// Repeat the last section for the other circuit
if ((ecomp->num1 != ecomp->num2) && (ecomp->cell2 != NULL) &&
(ecomp->cell2->class == CLASS_RES)) {
((ecomp->cell2->class == CLASS_RES) ||
(ecomp->cell2->class == CLASS_VSOURCE) ||
(ecomp->cell2->class == CLASS_ISOURCE))) {
int node1 = -1, node2 = -1;
lob = NULL;
for (ob2 = tc2->cell; ob2; ) {
@@ -1807,15 +1929,17 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
if (found) break;
}
if (found) {
Fprintf(stdout, "Removing zero-valued device"
Fprintf(stdout, "Removing zero-valued device "
"%s from cell %s makes a better match\n",
tsub2->name,
tc2->name);
/* merge node of endpoints */
for (ob1 = tc2->cell; ob1; ob1 = ob1->next) {
if (ob1->node == node2)
ob1->node = node1;
if (ecomp->cell2->class != CLASS_ISOURCE) {
for (ob1 = tc2->cell; ob1; ob1 = ob1->next) {
if (ob1->node == node2)
ob1->node = node1;
}
}
/* snip, snip. Excise this device */
@@ -1917,7 +2041,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
char *dstr = NULL;
tc2 = LookupCellFile(ob2->model.class, ecomp0X->cell2->file);
if (tc2->flags & CELL_DUPLICATE) {
dstr = strstr(ob1->model.class, "[[");
dstr = strstr(ob2->model.class, "[[");
if (dstr) *dstr = '\0';
}
ncomp = (ECompare *)HashInt2Lookup(ob2->model.class,
+1321 -605
View File
File diff suppressed because it is too large Load Diff
+8 -1
View File
@@ -8,6 +8,9 @@ extern struct nlist *Circuit2;
extern int ExhaustiveSubdivision;
extern int left_col_end;
extern int right_col_end;
#ifdef TCL_NETGEN
#include <tcl.h>
extern int InterruptPending;
@@ -36,7 +39,8 @@ extern int EquivalenceNodes(char *name1, int file1, char *name2, int file2);
extern int EquivalenceClasses(char *name1, int file1, char *name2, int file2);
extern int IgnoreClass(char *name, int file, unsigned char type);
extern int MatchPins(struct nlist *tp1, struct nlist *tp2, int dolist);
extern int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int serial);
extern int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run,
int series, int comb);
extern int CreateCompareQueue(char *, int, char *, int);
extern int GetCompareQueueTop(char **, int *, char **, int *);
@@ -47,6 +51,9 @@ extern void PrintIllegalClasses();
extern void PrintIllegalNodeClasses();
extern void PrintIllegalElementClasses();
extern void DumpNetwork(struct objlist *ob, int cidx);
extern void DumpNetworkAll(char *name, int file);
#ifdef TCL_NETGEN
extern int EquivalentNode();
extern int EquivalentElement();
+291 -37
View File
@@ -47,6 +47,18 @@ static FILE *outfile;
static int Graph = 0;
int File;
/*------------------------------------------------------*/
/* Structure for stacking nested `if[n]def in verilog */
/*------------------------------------------------------*/
struct ifstack {
int invert;
struct property *kl;
struct ifstack *next;
};
struct ifstack *condstack = NULL;
extern char *SetExtension(char *buffer, char *path, char *extension)
/* add 'extension' to 'path' (overwriting previous extension, if any),
write it into buffer (if buffer is null, malloc a buffer).
@@ -191,11 +203,14 @@ struct filestack {
static struct filestack *OpenFiles = NULL;
struct hashdict *definitions = (struct hashdict *)NULL;
#define WHITESPACE_DELIMITER " \t\n\r"
/*----------------------------------------------------------------------*/
/* TrimQuoted() --- */
/* Remove spaces from inside single- or double-quoted strings. */
/* Ignore verilog constant bits (e.g., "1'b0") when parsing. */
/*----------------------------------------------------------------------*/
void TrimQuoted(char *line)
@@ -211,6 +226,13 @@ void TrimQuoted(char *line)
{
changed = FALSE;
qstart = strchr(lptr, '\'');
if (qstart && (qstart > lptr)) {
if (isdigit(*(qstart - 1))) {
lptr = qstart + 1;
changed = TRUE;
continue;
}
}
if (qstart)
{
qend = strchr(qstart + 1, '\'');
@@ -251,7 +273,6 @@ void TrimQuoted(char *line)
}
}
}
}
/*----------------------------------------------------------------------*/
@@ -265,39 +286,216 @@ void TrimQuoted(char *line)
int GetNextLineNoNewline(char *delimiter)
{
char *newbuf;
int testc;
char *newbuf;
int testc;
int nested = 0;
int llen;
if (feof(infile)) return -1;
if (feof(infile)) return -1;
// This is more reliable than feof() ...
testc = getc(infile);
if (testc == -1) return -1;
ungetc(testc, infile);
while (1) { /* May loop indefinitely in an `if[n]def conditional */
if (linesize == 0) {
/* Allocate memory for line */
linesize = 500;
line = (char *)MALLOC(linesize);
linetok = (char *)MALLOC(linesize);
}
fgets(line, linesize, infile);
while (strlen(line) == linesize - 1) {
newbuf = (char *)MALLOC(linesize + 500);
strcpy(newbuf, line);
FREE(line);
line = newbuf;
fgets(line + linesize - 1, 501, infile);
linesize += 500;
FREE(linetok);
linetok = (char *)MALLOC(linesize);
}
linenum++;
strcpy(linetok, line);
TrimQuoted(linetok);
// This is more reliable than feof() ...
testc = getc(infile);
if (testc == -1) return -1;
ungetc(testc, infile);
nexttok = strdtok(linetok, WHITESPACE_DELIMITER, delimiter);
return 0;
if (linesize == 0) {
/* Allocate memory for line */
linesize = 2000;
line = (char *)MALLOC(linesize + 1);
linetok = (char *)MALLOC(linesize + 1);
}
fgets(line, linesize, infile);
/* Immediately resolve backslash-EOL */
llen = strlen(line);
while ((llen > 1) && (llen < linesize - 1) && *(line + llen - 2) == '\\') {
*(line + llen - 2) = '\n';
fgets(line + llen - 1, linesize - llen + 1, infile);
llen = strlen(line);
}
while (llen == linesize - 1) {
newbuf = (char *)MALLOC(linesize + 501);
strcpy(newbuf, line);
FREE(line);
line = newbuf;
fgets(line + linesize - 1, 501, infile);
llen = strlen(line);
while ((llen > 1) && (llen < linesize - 1) && *(line + llen - 2) == '\\') {
*(line + llen - 2) = '\n';
fgets(line + llen - 1, linesize - llen + 1, infile);
llen = strlen(line);
}
linesize += 500;
FREE(linetok);
linetok = (char *)MALLOC(linesize + 1);
}
/* Check for substitutions (verilog only). Make sure linetok is */
/* large enough to hold the entire line after substitutions. */
if (definitions != NULL) {
char *s, *w, e;
struct property *kl;
int len, dlen, vlen, addin = 0;
unsigned char found = FALSE;
for (s = line; *s != '\0'; s++) {
if (*s == '`') {
w = s + 1;
while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
e = *w;
*w = '\0';
kl = (struct property *)HashLookup(s + 1, definitions);
if (kl != NULL) {
dlen = strlen(s);
if (kl->type == PROP_STRING) {
vlen = strlen(kl->pdefault.string);
}
else vlen = 12; /* Leave room for numeric conversion */
addin += vlen - dlen + 1;
found = TRUE;
}
*w = e;
}
}
if (found) {
len = strlen(line);
if (len + addin > linesize) {
while (len + addin > linesize) linesize += 500;
FREE(linetok);
linetok = (char *)MALLOC(linesize);
}
}
}
/* Make definition substitutions (verilog only) */
if (definitions != NULL) {
char *s, *t, *w, e;
struct property *kl;
t = linetok;
for (s = line; *s != '\0'; s++) {
if (*s == '`') {
w = s + 1;
while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
e = *w;
*w = '\0';
kl = (struct property *)HashLookup(s + 1, definitions);
if (kl != NULL) {
if (kl->type == PROP_STRING)
strcpy(t, kl->pdefault.string);
else if (kl->type == PROP_INTEGER)
sprintf(t, "%d", kl->pdefault.ival);
else if (kl->type == PROP_DOUBLE)
sprintf(t, "%g", kl->pdefault.dval);
t += strlen(t);
s = w - 1;
}
else *t++ = *s;
*w = e;
}
else *t++ = *s;
}
*t = '\0';
}
else
strcpy(linetok, line);
TrimQuoted(linetok);
linenum++;
nexttok = strdtok(linetok, WHITESPACE_DELIMITER, delimiter);
if (nexttok == NULL) return 0;
/* Handle `ifdef, `ifndef, `elsif, `else, and `endif (verilog */
/* only, where indicated by a non-NULL "definitions") */
if (definitions == NULL) return 0;
/* If currently skipping through a section, handle conditionals differently */
if (condstack) {
if (((condstack->invert == 0) && (condstack->kl == NULL))
|| ((condstack->invert == 1) && (condstack->kl != NULL))) {
if (match(nexttok, "`ifdef") || match(nexttok, "`ifndef")) {
nested++;
continue;
}
else if (nested > 0) {
if (match(nexttok, "`endif")) nested--;
continue;
}
else if (nexttok[0] != '`') continue;
}
}
/* Handle conditionals (that is not being skipped over) */
if (match(nexttok, "`endif")) {
if (condstack == NULL) {
fprintf(stderr, "Error: `endif without corresponding `if[n]def\n");
}
else {
struct ifstack *iftop = condstack;
condstack = condstack->next;
FREE(iftop);
}
}
/* Note that `if[n]def may be nested. */
else if (match(nexttok, "`ifdef") || match(nexttok, "`ifndef") ||
match(nexttok, "`elsif") || match(nexttok, "`else")) {
/* Every `ifdef or `ifndef increases condstack by 1 */
if (nexttok[1] == 'i') {
struct ifstack *newif = (struct ifstack *)MALLOC(sizeof(struct ifstack));
newif->next = condstack;
condstack = newif;
}
if (condstack == NULL) {
fprintf(stderr, "Error: %s without `if[n]def\n", nexttok);
break;
}
else {
if (match(nexttok, "`else")) {
/* Invert the sense of the if[n]def scope */
condstack->invert = (condstack->invert == 1) ? 0 : 1;
}
else if (match(nexttok, "`elsif")) {
nexttok = strdtok(NULL, WHITESPACE_DELIMITER, delimiter);
if (nexttok == NULL) {
fprintf(stderr, "Error: `elsif with no conditional.\n");
return 0;
}
/* Keep the same scope but redefine the parameter */
condstack->invert = 0;
condstack->kl = (struct property *)HashLookup(nexttok, definitions);
}
else {
condstack->invert = (nexttok[3] == 'n') ? 1 : 0;
nexttok = strdtok(NULL, WHITESPACE_DELIMITER, delimiter);
if (nexttok == NULL) {
fprintf(stderr, "Error: %s with no conditional.\n", nexttok);
return 0;
}
condstack->kl = (struct property *)HashLookup(nexttok, definitions);
}
}
}
else if (condstack) {
if (((condstack->invert == 0) && (condstack->kl == NULL))
|| ((condstack->invert == 1) && (condstack->kl != NULL)))
continue;
else
break;
}
else
break;
}
return 0;
}
/*----------------------------------------------------------------------*/
@@ -312,6 +510,24 @@ void GetNextLine(char *delimiter)
} while (nexttok == NULL);
}
/*----------------------------------------------------------------------*/
/* Return a pointer to the line at the position of nexttok */
/* This is used only when returning the entire line, untokenized, and */
/* is only called by the verilog read routine when reading the value of */
/* a `define statement. */
/*----------------------------------------------------------------------*/
char *GetLineAtTok()
{
char *lpos;
if (nexttok == NULL) return NULL;
if (line == NULL) return NULL;
lpos = strstr(line, nexttok);
return lpos;
}
/*----------------------------------------------------------------------*/
/* if nexttok is already NULL, force scanner to read new line */
/*----------------------------------------------------------------------*/
@@ -437,7 +653,10 @@ void SpiceSkipNewLine(void)
/* delimiters (this presumably could be further extended as needed). */
/* so ",;()" would be a valid delimiter set, but to include C-style */
/* comments and verilog-style parameter lists, one would need */
/* ",;()X/**///#(". */
/* "X/**///#(X,;()". Two-character delimiters should go first so that */
/* they have precedence over one-character delimiters. 'X' should be */
/* the first character of the delimiter string in addition to marking */
/* the boundary between two-character and one-character delimiters. */
/*----------------------------------------------------------------------*/
char *strdtok(char *pstring, char *delim1, char *delim2)
@@ -468,6 +687,34 @@ char *strdtok(char *pstring, char *delim1, char *delim2)
/* "stoken" is now set. Now find the end of the current token */
s = stoken;
/* Special verilog rule: If a name begins with '\', then all characters */
/* are a valid part of the name until a space character is reached. The */
/* space character becomes part of the verilog name. The remainder of the */
/* name is parsed according to the rules of "delim2". */
/* Special verilog rule exception: To handle the problems caused by */
/* translating verilog backslash-escaped names into other netlist formats */
/* like SPICE where the convention is strictly prohibited, I have used the */
/* convention in qflow scripts to replace the trailing space with another */
/* backslash, so the name is effectively delimited by a pair of back- */
/* slashes. Therefore check for a space or another backslash, whichever */
/* comes first. That will satisfy both methods. Technically this routine */
/* should know whether it is parsing SPICE or verilog and handle the syntax */
/* accordingly (needs to be done). */
if (*s == '\\') {
s++;
while (*s != '\0') {
if ((*s == ' ') || (*s == '\\')) {
s++;
break;
}
s++;
}
}
/* Check string from position stoken. If a character in "delim2" is found, */
/* save the character in "lastdelim", null the byte at that position, and */
/* return the token. If a character in "delim1" is found, do the same but */
@@ -476,11 +723,11 @@ char *strdtok(char *pstring, char *delim1, char *delim2)
/* as for "delim2" above. If not, then set "lastdelim" to a null byte and */
/* return the token. */
for (s = stoken; *s; s++) {
twofer = FALSE;
for (s2 = delim2; s2 && *s2; s2++) {
for (; *s; s++) {
twofer = (delim2 && (*delim2 == 'X')) ? TRUE : FALSE;
for (s2 = ((twofer == TRUE) ? delim2 + 1 : delim2); s2 && *s2; s2++) {
if (*s2 == 'X') {
twofer = TRUE;
twofer = FALSE;
continue;
}
if (twofer) {
@@ -551,7 +798,7 @@ int OpenParseFile(char *name, int fnum)
FILE *locfile;
struct filestack *newfile;
locfile = fopen(name,"r");
locfile = fopen(name, "r");
linenum = 0;
/* reset the token scanner */
nexttok = NULL;
@@ -636,7 +883,12 @@ char *ReadNetlist(char *fname, int *fnum)
{SPICE_EXTENSION, ReadSpice},
{SPICE_EXT2, ReadSpice},
{SPICE_EXT3, ReadSpice},
{SPICE_EXT4, ReadSpice},
{SPICE_EXT5, ReadSpice},
{SPICE_EXT6, ReadSpice},
{SPICE_EXT7, ReadSpice},
{VERILOG_EXTENSION, ReadVerilog},
{SYS_VERILOG_EXTENSION, ReadVerilog},
{NETGEN_EXTENSION, ReadNetgenFile},
{NULL, NULL}
};
@@ -644,7 +896,9 @@ char *ReadNetlist(char *fname, int *fnum)
/* make first pass looking for extension */
for (index = 0; formats[index].extension != NULL; index++) {
if (strstr(fname, formats[index].extension) != NULL) {
int extlen = strlen(formats[index].extension);
int flen = strlen(fname);
if (!strcmp(fname + flen - extlen, formats[index].extension)) {
return (*(formats[index].proc))(fname, fnum);
}
}
+9 -1
View File
@@ -9,11 +9,16 @@
#define SIM_EXTENSION ".sim"
#define SPICE_EXTENSION ".spice"
#define SPICE_EXT2 ".spc"
#define SPICE_EXT3 ".fspc"
#define SPICE_EXT3 ".sp"
#define SPICE_EXT4 ".spi"
#define SPICE_EXT5 ".fspc"
#define SPICE_EXT6 ".cir"
#define SPICE_EXT7 ".ckt"
#define NETGEN_EXTENSION ".ntg"
#define CCODE_EXTENSION ".c.code"
#define ESACAP_EXTENSION ".esa"
#define VERILOG_EXTENSION ".v"
#define SYS_VERILOG_EXTENSION ".sv"
#define LINELENGTH 80
@@ -24,14 +29,17 @@ extern void FlushString (char *format, ...);
extern char *SetExtension(char *buffer, char *path, char *extension);
extern int File;
extern struct hashdict *definitions;
/* input routines */
extern char *nexttok;
#define SKIPTO(a) do {SkipTok(NULL);} while (!match(nexttok,a))
extern char *strdtok(char *pstring, char *delim1, char *delim2);
extern char *GetLineAtTok();
extern void SkipTok(char *delimiter);
extern void SkipTokNoNewline(char *delimiter);
extern void SkipTokComments(char *delimiter);
extern void SkipNewLine(char *delimiter);
extern void SpiceTokNoNewline(void); /* handles SPICE "+" continuation line */
extern void SpiceSkipNewLine(void); /* handles SPICE "+" continuation line */
+766 -571
View File
File diff suppressed because it is too large Load Diff
+20 -5
View File
@@ -36,12 +36,15 @@ extern struct property *PropertyString(char *name, int fnum, char *key,
double slop, char *pdefault);
extern int PropertyDelete(char *name, int fnum, char *key);
extern void SetParallelCombine(int value);
extern void SetSeriesCombine(int value);
extern int PropertyTolerance(char *name, int fnum, char *key, int ival,
double dval);
extern int PropertyMerge(char *name, int fnum, char *key, int merge_type);
extern int PropertyMerge(char *name, int fnum, char *key, int merge_type,
int merge_mask);
extern void ResolveProperties(char *name1, int file1, char *name2, int file2);
extern void CopyProperties(struct objlist *obj_to, struct objlist *obj_from);
extern int PromoteProperty(struct property *, struct valuelist *);
extern int PromoteProperty(struct property *, struct valuelist *,
struct objlist *, struct nlist *);
extern int SetPropertyDefault(struct property *, struct valuelist *);
extern struct objlist *LinkProperties(char *model, struct keyvalue *topptr);
extern int ReduceExpressions(struct objlist *instprop, struct objlist *parprops,
@@ -63,6 +66,15 @@ extern void AssignCircuits(char *name1, int file1, char *name2, int file2);
/* flatten.c */
extern int PrematchLists(char *, int, char *, int);
/* verilog.c */
struct cellstack {
char *cellname;
struct cellstack *next;
};
void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
int blackbox);
/* Define (enumerate) various device classes, largely based on SPICE */
/* model types, mixed with some ext/sim types. */
@@ -85,8 +97,10 @@ extern int PrematchLists(char *, int, char *, int);
#define CLASS_DIODE 16 /* standard SPICE diode */
#define CLASS_INDUCTOR 17 /* standard SPICE inductor */
#define CLASS_XLINE 18 /* transmission line model */
#define CLASS_MODULE 19 /* sim "x"; black-box subcircuit */
#define CLASS_UNDEF 20 /* not defined; error */
#define CLASS_VSOURCE 19 /* independent voltage source */
#define CLASS_ISOURCE 20 /* independent current source */
#define CLASS_MODULE 21 /* sim "x"; black-box subcircuit */
#define CLASS_UNDEF 22 /* not defined; error */
extern char *P(char *fname, char *inststr, char *drain, char *gate, char *source);
extern char *P4(char *fname, char *inststr, char *drain, char *gate, char *source,
@@ -120,7 +134,7 @@ extern void ConvertGlobals(char *name, int fnum);
extern int CleanupPins(char *name, int fnum);
extern void ConnectAllNodes(char *model, int fnum);
extern int CombineParallel(char *model, int fnum);
extern int CombineSerial(char *model, int fnum);
extern int CombineSeries(char *model, int fnum);
extern int NoDisconnectedNodes;
extern int PropertyKeyMatch(char *, char *);
extern int PropertyValueMatch(char *, char *);
@@ -136,6 +150,7 @@ extern int NoOutput; /* set this to 1 to disable stdout output */
extern int Composition; /* direction of composition */
extern int UnixWildcards; /* TRUE if *,?,{},[] only; false if full REGEXP */
extern int GlobalParallelNone; /* If TRUE, don't parallel combine any cells */
extern int GlobalParallelOpen; /* If TRUE, parallel combine cells w/no-connects */
/* magic internal flag to restrict searches to recently placed cells */
extern int QuickSearch;
/* does re"CellDef"ing a cell add to it or overwrite it??? */
+12 -3
View File
@@ -289,7 +289,7 @@ static struct hashdict cell_dict;
void InitCellHashTable(void)
{
hashfunc = hash;
matchfunc = match;
matchfunc = NULL;
matchintfunc = matchfile;
InitializeHashTable(&cell_dict, CELLHASHSIZE);
}
@@ -598,7 +598,11 @@ static int PrintCellHashTableElement(struct hashlist *p)
if (Debug == 1) Printf("Cell: %s (instanced %d times); Primitive\n",
ptr->name, ptr->number);
else if (Debug == 3) { /* list */
#ifdef TCL_NETGEN
Tcl_AppendElement(netgeninterp, ptr->name);
#else
Printf("%s ", ptr->name);
#endif
}
}
else if ((Debug == 2) || (Debug == 3)) { /* list only */
@@ -971,6 +975,7 @@ struct objlist *CopyObjList(struct objlist *oldlist, unsigned char doforall)
newob->model.class = NULL;
else
newob->model.class = strsave(tmp->model.class);
newob->flags = tmp->flags;
newob->instance.name = (tmp->instance.name) ?
strsave(tmp->instance.name) : NULL;
}
@@ -1108,13 +1113,17 @@ void FreeObjectAndHash(struct objlist *ob, struct nlist *ptr)
/*************** GENERAL UTILITIES ****************************/
int NumberOfPorts(char *cellname)
int NumberOfPorts(char *cellname, int file)
{
struct nlist *tp;
struct objlist *ob;
int ports;
tp = LookupCell(cellname);
if (file == -1)
tp = LookupCell(cellname);
else
tp = LookupCellFile(cellname, file);
if (tp == NULL) return(0);
ports = 0;
for (ob = tp->cell; ob != NULL; ob = ob->next)
+25 -11
View File
@@ -28,6 +28,8 @@
#define PROXY (0) /* Used in model.port record of ports */
#define NO_CONNECT 1 /* Use in object list to flag an isolated net */
/* Lists of device properties. Order is defined at the time of */
/* the cell definition; values are sorted at the time instances */
/* are read. */
@@ -103,18 +105,30 @@ struct valuelist {
/* Part 3: Keys & Defaults (kept in the cell record as a hash table) */
#define MERGE_NONE 0 /* Property does not change when devices merge */
#define MERGE_ADD 1 /* Properties sum with device parallel merge */
#define MERGE_ADD_CRIT 2 /* Properties sum with device parallel merge */
#define MERGE_PAR 3 /* Properties add in parallel with device merge */
#define MERGE_PAR_CRIT 4 /* Properties add in parallel with device merge */
#define MERGE_SER 5 /* Properties sum with device parallel merge */
#define MERGE_SER_CRIT 6 /* Properties sum with device parallel merge */
#define MERGE_NONE 0x00 /* Property does not change when devices merge */
#define MERGE_P_ADD 0x01 /* Properties sum with device parallel merge */
#define MERGE_P_PAR 0x02 /* Properties add in parallel with parallel merge */
#define MERGE_P_CRIT 0x04 /* This property enables parallel merging */
#define MERGE_P_XCRIT 0x08 /* Old "critical" behavior (deprecated) */
#define MERGE_S_ADD 0x10 /* Properties sum with device series merge */
#define MERGE_S_PAR 0x20 /* Properties add in parallel with series merge */
#define MERGE_S_CRIT 0x40 /* This property enables series merging */
#define MERGE_S_XCRIT 0x80 /* Old "critical" behavior (deprecated) */
#define MERGE_P_MASK (MERGE_P_ADD | MERGE_P_PAR | MERGE_P_CRIT | MERGE_P_XCRIT)
#define MERGE_S_MASK (MERGE_S_ADD | MERGE_S_PAR | MERGE_S_CRIT | MERGE_S_XCRIT)
#define MERGE_ALL_MASK (MERGE_P_MASK | MERGE_S_MASK)
/* Although the above are flags, "ADD" and "PAR" are mutually exclusive. */
/* Note: A "critical" merge means that the property causes the number of */
/* devices to change. e.g., transistor width is critical; transistor drain */
/* area sums when devices are merged, but does not change the number of devices.*/
/* More than one property can be critical. e.g., width and number of fingers. */
/* Also it is possible for a property (e.g., "value") to be critical for both */
/* series and parallel merging. */
struct property {
char *key; /* name of the property */
@@ -150,6 +164,7 @@ struct objlist {
/* (string) value of property for properties */
struct valuelist *props; /* Property record */
} instance;
unsigned char flags; /* Used by NODE type to flag isolated net */
int node; /* the electrical node number of the port/node/pin */
struct objlist *next;
};
@@ -180,9 +195,8 @@ struct Permutation {
struct Permutation *next;
};
#define OBJHASHSIZE 997 /* the size of the object and instance hash lists */
#define OBJHASHSIZE 42073 /* the size of the object and instance hash lists */
/* prime numbers are good choices as hash sizes */
/* 101 is a good number for IBMPC */
/* cell definition for hash table */
/* NOTE: "file" must come first for the hash matching by name and file */
@@ -217,7 +231,7 @@ struct nlist {
/* Flags for combination allowances and prohibitions */
#define COMB_SERIAL 0x40
#define COMB_SERIES 0x40
#define COMB_NO_PARALLEL 0x80
extern struct nlist *CurrentCell;
@@ -230,7 +244,7 @@ extern void FreeObjectAndHash(struct objlist *ob, struct nlist *ptr);
extern void FreePorts(char *cellname);
extern struct IgnoreList *ClassIgnore;
extern int NumberOfPorts(char *cellname);
extern int NumberOfPorts(char *cellname, int file);
extern struct objlist *InstanceNumber(struct nlist *tp, int inst);
extern struct objlist *List(char *list_template);
+1 -1
View File
@@ -929,7 +929,7 @@ void ToggleDebug(void)
void DescribeCell(char *name, int detail)
{
Printf("Cell: %s contains %d instances, %d nodes and %d ports\n", name,
NumberOfInstances(name), RenumberNodes(name), NumberOfPorts(name));
NumberOfInstances(name), RenumberNodes(name), NumberOfPorts(name, -1));
PrintEmbeddingTree(stdout,name,detail);
}
+13 -6
View File
@@ -801,9 +801,16 @@ void DescribeInstance(char *name, int file)
{
if (ob->node > nodemax) nodemax = ob->node;
else if ((ob->node == -1) && (ob->model.port != PROXY)) {
if (disconnectednodes == 0) Fprintf(stderr, "\n");
disconnectednodes++;
Fprintf(stderr, "Cell %s disconnected node: %s\n", tp->name, ob->name);
/* All black-box modules and placeholders by definition have all */
/* disconnected pins, so don't report those. */
if (!(tp->flags & CELL_PLACEHOLDER) && (tp->class != CLASS_MODULE))
{
if (disconnectednodes == 0) Fprintf(stderr, "\n");
disconnectednodes++;
Fprintf(stderr, "Cell %s disconnected node: %s\n", tp->name, ob->name);
}
}
}
instlist = (unsigned char *) CALLOC((nodemax + 1), sizeof(unsigned char));
@@ -900,7 +907,7 @@ void PrintLeavesInCell(char *cellname, int filenum)
np->dumped = 1;
if (np->class != CLASS_SUBCKT) {
Printf("%s; %d ports; Primitive.\n", cellname, NumberOfPorts(cellname));
Printf("%s; %d ports; Primitive.\n", cellname, NumberOfPorts(cellname, filenum));
return;
}
@@ -913,7 +920,7 @@ void PrintLeavesInCell(char *cellname, int filenum)
am_a_leaf = 0;
}
if (am_a_leaf) Printf("%s; %d ports\n", cellname, NumberOfPorts(cellname));
if (am_a_leaf) Printf("%s; %d ports\n", cellname, NumberOfPorts(cellname, filenum));
return;
}
@@ -1063,7 +1070,7 @@ void Query(void)
ActelLib();
break;
case 'S':
promptstring("Read SPICE (.ckt) file? ", repstr);
promptstring("Read SPICE (.spice) file? ", repstr);
ReadSpice(repstr, &filenum);
break;
case 'V':
+78 -27
View File
@@ -117,6 +117,12 @@ void SpiceSubCell(struct nlist *tp, int IsSubCell)
case CLASS_NPN: case CLASS_PNP: case CLASS_BJT:
spice_class = 'Q';
break;
case CLASS_VSOURCE:
spice_class = 'V';
break;
case CLASS_ISOURCE:
spice_class = 'I';
break;
case CLASS_RES: case CLASS_RES3:
spice_class = 'R';
break;
@@ -172,7 +178,7 @@ void SpiceSubCell(struct nlist *tp, int IsSubCell)
break;
}
/* caps and resistors, print out device value */
/* caps, resistors, voltage and current sources, print out device value */
/* print out device type (model/subcircuit name) */
@@ -217,6 +223,23 @@ void SpiceSubCell(struct nlist *tp, int IsSubCell)
FlushString(" %s", model); /* semiconductor resistor */
break;
case CLASS_VSOURCE:
case CLASS_ISOURCE:
ob = ob->next;
if (ob->type == PROPERTY) {
struct valuelist *vl;
int i;
for (i == 0;; i++) {
vl = &(ob->instance.props[i]);
if (vl->type == PROP_ENDLIST) break;
else if (vl->type == PROP_VALUE) {
FlushString(" %g", vl->value.dval);
break;
}
}
}
break;
default:
FlushString(" %s", model); /* everything else */
}
@@ -450,15 +473,6 @@ void CleanupSubcell() {
SetClass(CLASS_MODULE);
}
/*------------------------------------------------------*/
/* Structure for stacking nested subcircuit definitions */
/*------------------------------------------------------*/
struct cellstack {
char *cellname;
struct cellstack *next;
};
/*------------------------------------------------------*/
/* Push a subcircuit name onto the stack */
/*------------------------------------------------------*/
@@ -711,6 +725,12 @@ skip_ends:
else if (!strcasecmp(nexttok, "R")) {
class = CLASS_RES;
}
else if (!strcasecmp(nexttok, "V")) {
class = CLASS_VSOURCE;
}
else if (!strcasecmp(nexttok, "I")) {
class = CLASS_ISOURCE;
}
else if (!strcasecmp(nexttok, "C")) {
class = CLASS_CAP;
}
@@ -845,6 +865,17 @@ skip_ends:
}
}
/* Ignore anything in a .CONTROL ... .ENDC block */
else if (matchnocase(nexttok, ".CONTROL")) {
while (1) {
SpiceSkipNewLine();
SkipTok(NULL);
if (EndParseFile()) break;
if (matchnocase(nexttok, ".ENDC"))
break;
}
}
// Blackbox (library) mode---parse only subcircuits and models;
// ignore all components.
@@ -1155,7 +1186,7 @@ skip_ends:
else if (CountPorts(model, filenum) != 2) {
/* Modeled device: Make sure it has the right number of ports */
Fprintf(stderr, "Device \"%s\" has wrong number of ports for a "
"resistor.\n");
"resistor.\n", model);
goto baddevice;
}
usemodel = 1;
@@ -1436,7 +1467,7 @@ skip_ends:
Port("pos");
Port("neg");
PropertyInteger(model, filenum, "M", 0, 1);
SetClass(CLASS_MODULE);
SetClass(CLASS_VSOURCE);
EndCell();
ReopenCellDef((*CellStackPtr)->cellname, filenum); /* Reopen */
}
@@ -1490,7 +1521,7 @@ skip_ends:
Port("pos");
Port("neg");
PropertyInteger(model, filenum, "M", 0, 1);
SetClass(CLASS_MODULE);
SetClass(CLASS_ISOURCE);
EndCell();
ReopenCellDef((*CellStackPtr)->cellname, filenum); /* Reopen */
}
@@ -1854,20 +1885,36 @@ char *ReadSpiceTop(char *fname, int *fnum, int blackbox)
CurrentCell = NULL;
if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
char name[100];
SetExtension(name, fname, SPICE_EXTENSION);
if ((filenum = OpenParseFile(name, *fnum)) < 0) {
Fprintf(stderr,"Error in SPICE file read: No file %s\n",name);
if (strrchr(fname, '.') == NULL) {
char name[1024];
SetExtension(name, fname, SPICE_EXTENSION);
if ((filenum = OpenParseFile(name, *fnum)) < 0) {
Fprintf(stderr, "Error in SPICE file read: No file %s\n", name);
*fnum = filenum;
return NULL;
}
}
else {
Fprintf(stderr, "Error in SPICE file read: No file %s\n", fname);
*fnum = filenum;
return NULL;
}
}
}
/* Make sure all SPICE file reading is case insensitive */
matchfunc = matchnocase;
matchintfunc = matchfilenocase;
hashfunc = hashnocase;
/* Make sure all SPICE file reading is case insensitive */
/* BUT if a verilog file was read before it, then it will */
/* be forced to be case sensitive, caveat end-user. */
if (matchfunc == match) {
Printf("Warning: A case-sensitive file has been read and so the "
"SPICE netlist must be treated case-sensitive to match.\n");
}
else {
matchfunc = matchnocase;
matchintfunc = matchfilenocase;
hashfunc = hashnocase;
}
InitializeHashTable(&spiceparams, OBJHASHSIZE);
@@ -1951,14 +1998,18 @@ void IncludeSpice(char *fname, int parent, struct cellstack **CellStackPtr,
/* helps, if the file didn't have an extension. But */
/* really, we're getting desperate at this point. */
if (strchr(fname, '.') == NULL) {
if (strrchr(fname, '.') == NULL) {
SetExtension(name, fname, SPICE_EXTENSION);
filenum = OpenParseFile(name, parent);
}
if (filenum < 0) {
Fprintf(stderr,"Error in SPICE file include: No file %s\n",name);
return;
if (filenum < 0) {
Fprintf(stderr, "Error in SPICE file include: No file %s\n", name);
return;
}
}
else {
Fprintf(stderr, "Error in SPICE file include: No file %s\n", fname);
return;
}
}
}
ReadSpiceFile(fname, parent, CellStackPtr, blackbox);
+907 -277
View File
File diff suppressed because it is too large Load Diff
Vendored
+3 -1
View File
@@ -4,4 +4,6 @@
# all of its config scripts in a different directory than the configure
# script itself.
( CFLAGS="-g" ; export CFLAGS ; cd scripts ; ./configure $* )
export CFLAGS="$CFLAGS -g"
cd scripts
exec ./configure "$@"
-85
View File
@@ -1,85 +0,0 @@
# defs.mak.in --
# source file for autoconf-generated "defs.mak" for netgen
# defs.mak. Generated from defs.mak.in by configure.
# Feel free to change the values in here to suit your needs.
# Be aware that running scripts/configure again will overwrite
# any changes!
SHELL = /bin/sh
prefix = ${BUILDROOT}/usr/local
exec_prefix = ${prefix}
bindir = ${exec_prefix}/bin
libdir = ${exec_prefix}/lib
mandir = ${prefix}/share/man
VERSION =
SCRIPTS = ${NETGENDIR}/scripts
INSTALL = /bin/install -c
INSTALL_PROGRAM = ${INSTALL}
INSTALL_DATA = ${INSTALL} -m 644
INSTALL_SCRIPT = ${INSTALL}
# Override standard "make" target when compiling under TCL
ALL_TARGET = tcl
INSTALL_TARGET = install-tcl
# Change CADDIR to install in a different place
BINDIR = ${bindir}
MANDIR = ${mandir}
LIBDIR = ${libdir}
DOCDIR = ${libdir}/netgen/doc
TCLDIR = ${libdir}/netgen/tcl
PYDIR = ${libdir}/netgen/python
MAIN_EXTRA_LIBS = ${NETGENDIR}/tcltk/libtcltk.o
LD_EXTRA_LIBS =
LD_SHARED =
TOP_EXTRA_LIBS =
SUB_EXTRA_LIBS =
MODULES += tcltk
UNUSED_MODULES +=
PROGRAMS += tcltk
INSTALL_CAD_DIRS += tcltk
RM = rm -f
CP = cp
AR = @AR@
ARFLAGS = crv
LINK = /bin/ld -r
LD = /bin/ld
M4 = /bin/m4
RANLIB = ranlib
SHDLIB_EXT = .so
LDDL_FLAGS = -shared -Wl,-soname,$@ -Wl,--version-script=${NETGENDIR}/netgen/symbol.map
LD_RUN_PATH =
LIB_SPECS = -L/usr/lib64 -ltkstub8.6 -L/usr/lib64 -ltclstub8.6
LIB_SPECS_NOSTUB = -L/usr/lib64 -ltk8.6 -L/usr/lib64 -ltcl8.6
WISH_EXE = /usr/bin/wish
TCL_LIB_DIR = /usr/lib
CC = gcc
CPP = gcc -E -x c
CXX = @CXX@
CPPFLAGS = -I. -I${NETGENDIR}
DFLAGS = -DCAD_DIR=\"${LIBDIR}\" -DTCL_DIR=\"${TCLDIR}\" -DUSE_TCL_STUBS -DUSE_TK_STUBS -DPACKAGE_NAME=\"netgen\" -DPACKAGE_TARNAME=\"netgen\" -DPACKAGE_VERSION=\"1.3\" -DPACKAGE_STRING=\"netgen\ 1.3\" -DPACKAGE_BUGREPORT=\"[email protected]\" -DPACKAGE_URL=\"\" -DNETGEN_VERSION=\"1.5\" -DNETGEN_REVISION=\"102\" -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DSIZEOF_VOID_P=8 -DSIZEOF_UNSIGNED_INT=4 -DSIZEOF_UNSIGNED_LONG=8 -DSIZEOF_UNSIGNED_LONG_LONG=8 -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DHAVE_DIRENT_H=1 -DHAVE_LIMITS_H=1 -DHAVE_VA_COPY=1 -DHAVE___VA_COPY=1 -DDBUG_OFF=1 -DTCL_NETGEN=1 -Dlinux=1 -DSYSV=1 -DISC=1 -DSHDLIB_EXT=\".so\" -DNDEBUG
DFLAGS_NOSTUB = -DCAD_DIR=\"${LIBDIR}\" -DTCL_DIR=\"${TCLDIR}\" -DPACKAGE_NAME=\"netgen\" -DPACKAGE_TARNAME=\"netgen\" -DPACKAGE_VERSION=\"1.3\" -DPACKAGE_STRING=\"netgen\ 1.3\" -DPACKAGE_BUGREPORT=\"[email protected]\" -DPACKAGE_URL=\"\" -DNETGEN_VERSION=\"1.5\" -DNETGEN_REVISION=\"102\" -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DSIZEOF_VOID_P=8 -DSIZEOF_UNSIGNED_INT=4 -DSIZEOF_UNSIGNED_LONG=8 -DSIZEOF_UNSIGNED_LONG_LONG=8 -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DHAVE_DIRENT_H=1 -DHAVE_LIMITS_H=1 -DHAVE_VA_COPY=1 -DHAVE___VA_COPY=1 -DDBUG_OFF=1 -DTCL_NETGEN=1 -Dlinux=1 -DSYSV=1 -DISC=1 -DSHDLIB_EXT=\".so\" -DNDEBUG
CFLAGS = -g -m64 -fPIC -fPIC
DEPEND_FILE = Depend
DEPEND_FLAG = -MM
EXEEXT =
GR_CFLAGS =
GR_DFLAGS = -DX11 -DXLIB -DNDEBUG
GR_LIBS = -lX11
GR_SRCS = ${TK_SRCS}
OBJS = ${SRCS:.c=.o}
LIB_OBJS = ${LIB_SRCS:.c=.o}
CLEANS = ${OBJS} ${LIB_OBJS} lib${MODULE}.a lib${MODULE}.o ${MODULE}
+7 -7
View File
@@ -2,11 +2,11 @@ NETGENDIR = ..
include ${NETGENDIR}/defs.mak
MANDIRS = $(DESTDIR)${MANDIR} $(DESTDIR)${MANDIR}/man1
DOCDIRS = $(DESTDIR)${DOCDIR}
MANDIRS = $(DESTDIR)${INSTALL_MANDIR} $(DESTDIR)${INSTALL_MANDIR}/man1
DOCDIRS = $(DESTDIR)${INSTALL_DOCDIR}
MANFILES =
DOCFILES = $(DESTDIR)${DOCDIR}/netgen.doc
DOCFILES = $(DESTDIR)${INSTALL_DOCDIR}/netgen.doc
install-tcl: ${DOCDIRS} ${DOCFILES}
@@ -23,8 +23,8 @@ make-doc-dirs:
${SCRIPTS}/mkdirs ${DOCDIRS}
# This file does not actually exist. . .
$(DESTDIR)${MANDIR}/man1/netgen.1: netgen.1 ${MANDIRS}
${CP} netgen.1 $(DESTDIR)${MANDIR}/man1/netgen.1
$(DESTDIR)${INSTALL_MANDIR}/man1/netgen.1: netgen.1 ${MANDIRS}
${CP} netgen.1 $(DESTDIR)${INSTALL_MANDIR}/man1/netgen.1
$(DESTDIR)${DOCDIR}/netgen.doc: netgen.doc ${DOCDIRS}
${CP} netgen.doc $(DESTDIR)${DOCDIR}/netgen.doc
$(DESTDIR)${INSTALL_DOCDIR}/netgen.doc: netgen.doc ${DOCDIRS}
${CP} netgen.doc $(DESTDIR)${INSTALL_DOCDIR}/netgen.doc
+6 -6
View File
@@ -4,14 +4,14 @@ include ${NETGENDIR}/defs.mak
LIB_FILES = ntk2adl.sh spice spice.bot spice.top
LIB_INST_FILES= $(LIB_FILES:%=$(DESTDIR)${LIBDIR}/netgen/%)
BIN_INST_FILES= $(BIN_FILES:%=$(DESTDIR)${BINDIR}/%)
LIB_INST_FILES= $(LIB_FILES:%=$(DESTDIR)${INSTALL_LIBDIR}/netgen/%)
BIN_INST_FILES= $(BIN_FILES:%=$(DESTDIR)${INSTALL_BINDIR}/%)
install-tcl: ${LIB_INST_FILES}
install: ${LIB_INST_FILES}
$(DESTDIR)${LIBDIR}/netgen/%: %
../scripts/mkdirs $(DESTDIR)${LIBDIR}/netgen
${RM} $(DESTDIR)${LIBDIR}/netgen/$*
${CP} $* $(DESTDIR)${LIBDIR}/netgen/$*
$(DESTDIR)${INSTALL_LIBDIR}/netgen/%: %
../scripts/mkdirs $(DESTDIR)${INSTALL_LIBDIR}/netgen
${RM} $(DESTDIR)${INSTALL_LIBDIR}/netgen/$*
${CP} $* $(DESTDIR)${INSTALL_LIBDIR}/netgen/$*
+12 -12
View File
@@ -25,23 +25,23 @@ tclnetgen${SHDLIB_EXT}: ${EXTRA_LIBS}
${LD_RUN_PATH} ${EXTRA_LIBS} ${LD_EXTRA_LIBS} \
-lc ${LIBS} ${LIB_SPECS} ${LDFLAGS}
$(DESTDIR)${BINDIR}/netgen:
$(DESTDIR)${INSTALL_BINDIR}/netgen:
${RM} $@
${CP} netgen $@
$(DESTDIR)${BINDIR}/ntk2adl:
$(DESTDIR)${INSTALL_BINDIR}/ntk2adl:
${RM} $@
${CP} ntk2adl $@
$(DESTDIR)${BINDIR}/ntk2xnf:
$(DESTDIR)${INSTALL_BINDIR}/ntk2xnf:
${RM} $@
${CP} ntk2xnf $@
$(DESTDIR)${BINDIR}/netcomp:
$(DESTDIR)${INSTALL_BINDIR}/netcomp:
${RM} $@
${CP} netcomp $@
$(DESTDIR)${BINDIR}/inetcomp:
$(DESTDIR)${INSTALL_BINDIR}/inetcomp:
${RM} $@
${CP} inetcomp $@
@@ -61,14 +61,14 @@ ntk2xnf: ntk2xnf.c
${CC} ${CFLAGS} ${CPPFLAGS} ${DFLAGS} ntk2xnf.c -o $@ ${EXTRA_LIBS} \
${LIBS} ${LDFLAGS}
install: $(DESTDIR)${BINDIR}/netgen $(DESTDIR)${BINDIR}/netcomp \
$(DESTDIR)${BINDIR}/inetcomp $(DESTDIR)${BINDIR}/ntk2adl \
$(DESTDIR)${BINDIR}/ntk2xnf
install: $(DESTDIR)${INSTALL_BINDIR}/netgen $(DESTDIR)${INSTALL_BINDIR}/netcomp \
$(DESTDIR)${INSTALL_BINDIR}/inetcomp $(DESTDIR)${INSTALL_BINDIR}/ntk2adl \
$(DESTDIR)${INSTALL_BINDIR}/ntk2xnf
install-tcl: $(DESTDIR)${TCLDIR} $(DESTDIR)${TCLDIR}/tclnetgen${SHDLIB_EXT}
install-tcl: $(DESTDIR)${INSTALL_TCLDIR} $(DESTDIR)${INSTALL_TCLDIR}/tclnetgen${SHDLIB_EXT}
$(DESTDIR)${TCLDIR}/tclnetgen${SHDLIB_EXT}: tclnetgen${SHDLIB_EXT}
${RM} $(DESTDIR)${TCLDIR}/tclnetgen${SHDLIB_EXT}
${CP} tclnetgen${SHDLIB_EXT} $(DESTDIR)${TCLDIR}/tclnetgen${SHDLIB_EXT}
$(DESTDIR)${INSTALL_TCLDIR}/tclnetgen${SHDLIB_EXT}: tclnetgen${SHDLIB_EXT}
${RM} $(DESTDIR)${INSTALL_TCLDIR}/tclnetgen${SHDLIB_EXT}
${CP} tclnetgen${SHDLIB_EXT} $(DESTDIR)${INSTALL_TCLDIR}/tclnetgen${SHDLIB_EXT}
include ${NETGENDIR}/rules.mak
+15 -12
View File
@@ -4,19 +4,21 @@ SRCS =
SCRIPTS = consoletext.py helpwindow.py lvs_manager.py treeviewsplit.py
SCRIPTS += tksimpledialog.py tooltip.py lvs_help.txt
SCRIPTINSTALL = $(DESTDIR)${PYDIR}
SCRIPTINSTALL = $(DESTDIR)${INSTALL_PYDIR}
include ${NETGENDIR}/defs.mak
CLEANS += lvs_manager.py
main: lvs_manager.py
tcl-main: lvs_manager.py
$(DESTDIR)${PYDIR}/consoletext.py:
$(DESTDIR)${INSTALL_PYDIR}/consoletext.py:
${RM} $@
${CP} consoletext.py $@
$(DESTDIR)${PYDIR}/helpwindow.py:
$(DESTDIR)${INSTALL_PYDIR}/helpwindow.py:
${RM} $@
${CP} helpwindow.py $@
@@ -24,31 +26,32 @@ lvs_manager.py: lvs_manager.py.in
sed -e '/SUBST_SCRIPT_DIR/s#SUBST_SCRIPT_DIR#$(SCRIPTINSTALL)#' \
lvs_manager.py.in > lvs_manager.py
$(DESTDIR)${PYDIR}/lvs_manager.py: lvs_manager.py
$(DESTDIR)${INSTALL_PYDIR}/lvs_manager.py: lvs_manager.py
${RM} $@
${CP} lvs_manager.py $@
chmod a+x $@
$(DESTDIR)${PYDIR}/treeviewsplit.py: treeviewsplit.py
$(DESTDIR)${INSTALL_PYDIR}/treeviewsplit.py: treeviewsplit.py
${RM} $@
${CP} treeviewsplit.py $@
$(DESTDIR)${PYDIR}/tksimpledialog.py: tksimpledialog.py
$(DESTDIR)${INSTALL_PYDIR}/tksimpledialog.py: tksimpledialog.py
${RM} $@
${CP} tksimpledialog.py $@
$(DESTDIR)${PYDIR}/tooltip.py: tooltip.py
$(DESTDIR)${INSTALL_PYDIR}/tooltip.py: tooltip.py
${RM} $@
${CP} tooltip.py $@
$(DESTDIR)${PYDIR}/lvs_help.txt: lvs_help.txt
$(DESTDIR)${INSTALL_PYDIR}/lvs_help.txt: lvs_help.txt
${RM} $@
${CP} lvs_help.txt $@
install: install-tcl
install-tcl: $(DESTDIR)${PYDIR} $(DESTDIR)${PYDIR}/consoletext.py \
$(DESTDIR)${PYDIR}/helpwindow.py $(DESTDIR)${PYDIR}/lvs_manager.py \
$(DESTDIR)${PYDIR}/treeviewsplit.py $(DESTDIR)${PYDIR}/tksimpledialog.py \
$(DESTDIR)${PYDIR}/tooltip.py $(DESTDIR)${PYDIR}/lvs_help.txt
install-tcl: $(DESTDIR)${INSTALL_PYDIR} $(DESTDIR)${INSTALL_PYDIR}/consoletext.py \
$(DESTDIR)${INSTALL_PYDIR}/helpwindow.py $(DESTDIR)${INSTALL_PYDIR}/lvs_manager.py \
$(DESTDIR)${INSTALL_PYDIR}/treeviewsplit.py $(DESTDIR)${INSTALL_PYDIR}/tksimpledialog.py \
$(DESTDIR)${INSTALL_PYDIR}/tooltip.py $(DESTDIR)${INSTALL_PYDIR}/lvs_help.txt
include ${NETGENDIR}/rules.mak
-819
View File
@@ -1,819 +0,0 @@
#!/bin/env python3
#
#--------------------------------------------------------
# LVS Manager GUI.
#
# This is a Python tkinter script that handles the
# process of running LVS and interpreting results.
#
#--------------------------------------------------------
# Written by Tim Edwards
# efabless, inc.
# Version 1. November 30, 2016
# Version 2. March 6, 2017. Reads JSON format output
# Version 3. April 25, 2018. Handles layout vs. verilog
#--------------------------------------------------------
import io
import os
import re
import sys
import json
import shutil
import signal
import socket
import select
import datetime
import contextlib
import subprocess
import tkinter
from tkinter import ttk
from tkinter import filedialog
import tksimpledialog
import tooltip
from consoletext import ConsoleText
from helpwindow import HelpWindow
from treeviewsplit import TreeViewSplit
# User preferences file (if it exists)
prefsfile = '~/.profile/prefs.json'
netgen_script_dir = '/usr/local/lib/netgen/python'
#------------------------------------------------------
# Simple dialog for confirming quit
#------------------------------------------------------
class ConfirmDialog(tksimpledialog.Dialog):
def body(self, master, warning, seed):
if warning:
ttk.Label(master, text=warning, wraplength=500).grid(row = 0, columnspan = 2, sticky = 'wns')
return self
def apply(self):
return 'okay'
#------------------------------------------------------
# Main class for this application
#------------------------------------------------------
class LVSManager(ttk.Frame):
"""LVS Manager GUI."""
def __init__(self, parent, *args, **kwargs):
ttk.Frame.__init__(self, parent, *args, **kwargs)
self.root = parent
self.init_gui()
parent.protocol("WM_DELETE_WINDOW", self.on_quit)
def on_quit(self):
"""Exits program."""
if self.msock:
self.msock.close()
quit()
def init_gui(self):
"""Builds GUI."""
global prefsfile
message = []
fontsize = 11
# Read user preferences file, get default font size from it.
prefspath = os.path.expanduser(prefsfile)
if os.path.exists(prefspath):
with open(prefspath, 'r') as f:
self.prefs = json.load(f)
if 'fontsize' in self.prefs:
fontsize = self.prefs['fontsize']
else:
self.prefs = {}
s = ttk.Style()
available_themes = s.theme_names()
s.theme_use(available_themes[0])
s.configure('bg.TFrame', background='gray40')
s.configure('italic.TLabel', font=('Helvetica', fontsize, 'italic'))
s.configure('title.TLabel', font=('Helvetica', fontsize, 'bold italic'),
foreground = 'brown', anchor = 'center')
s.configure('normal.TLabel', font=('Helvetica', fontsize))
s.configure('red.TLabel', font=('Helvetica', fontsize), foreground = 'red')
s.configure('green.TLabel', font=('Helvetica', fontsize), foreground = 'green3')
s.configure('blue.TLabel', font=('Helvetica', fontsize), foreground = 'blue')
s.configure('normal.TButton', font=('Helvetica', fontsize),
border = 3, relief = 'raised')
s.configure('red.TButton', font=('Helvetica', fontsize), foreground = 'red',
border = 3, relief = 'raised')
s.configure('green.TButton', font=('Helvetica', fontsize), foreground = 'green3',
border = 3, relief = 'raised')
s.configure('blue.TButton', font=('Helvetica', fontsize), foreground = 'blue',
border = 3, relief = 'raised')
s.configure('redtitle.TButton', font=('Helvetica', fontsize, 'bold italic'),
foreground = 'red', border = 3, relief = 'raised')
s.configure('bluetitle.TButton', font=('Helvetica', fontsize, 'bold italic'),
foreground = 'blue', border = 3, relief = 'raised')
# These values to be overridden from arguments
self.rootpath = None
self.project = None
self.logfile = None
self.msock = None
self.help = None
# Create the help window
if os.path.exists(netgen_script_dir + '/netgen_help.txt'):
self.help = HelpWindow(self, fontsize = fontsize)
with io.StringIO() as buf, contextlib.redirect_stdout(buf):
self.help.add_pages_from_file('lvs_help.txt')
message = buf.getvalue()
# Set the help display to the first page
self.help.page(0)
# Variables used by option menus and other stuff
self.project = "(no selection)"
self.layout = "(default)"
self.schematic = "(default)"
self.tech = "(none)"
self.lvs_setup = ''
self.lvsdata = {}
# Root window title
self.root.title('LVS Manager')
self.root.option_add('*tearOff', 'FALSE')
self.pack(side = 'top', fill = 'both', expand = 'true')
pane = tkinter.PanedWindow(self, orient = 'vertical', sashrelief='groove', sashwidth=6)
pane.pack(side = 'top', fill = 'both', expand = 'true')
self.toppane = ttk.Frame(pane)
self.botpane = ttk.Frame(pane)
# Get username
if 'username' in self.prefs:
username = self.prefs['username']
else:
username = os.environ['USER']
# Label with the user
self.toppane.title_frame = ttk.Frame(self.toppane)
self.toppane.title_frame.pack(side = 'top', fill = 'x')
self.toppane.title_frame.title = ttk.Label(self.toppane.title_frame, text='User:', style = 'red.TLabel')
self.toppane.title_frame.user = ttk.Label(self.toppane.title_frame, text=username, style = 'blue.TLabel')
self.toppane.title_frame.title.grid(column=0, row=0, ipadx = 5)
self.toppane.title_frame.user.grid(column=1, row=0, ipadx = 5)
self.toppane.title2_frame = ttk.Frame(self.toppane)
self.toppane.title2_frame.pack(side = 'top', fill = 'x')
self.toppane.title2_frame.project_label = ttk.Label(self.toppane.title2_frame, text="Project:",
style = 'title.TLabel')
self.toppane.title2_frame.project_label.grid(column=0, row=0, ipadx = 5)
# New project select button
self.toppane.title2_frame.project_select = ttk.Button(self.toppane.title2_frame,
text=self.project, style='normal.TButton', command=self.choose_project)
self.toppane.title2_frame.project_select.grid(column=1, row=0, ipadx = 5)
tooltip.ToolTip(self.toppane.title2_frame.project_select,
text = "Select new project")
# Show path to project
self.toppane.title2_frame.path_label = ttk.Label(self.toppane.title2_frame, text=self.project,
style = 'normal.TLabel')
self.toppane.title2_frame.path_label.grid(column=2, row=0, ipadx = 5, padx = 10)
# Show top-level layout cellname with select button. Initial cell name is the top-level cell.
self.toppane.title2_frame.tech_label = ttk.Label(self.toppane.title2_frame, text="Technology setup:",
style = 'title.TLabel')
self.toppane.title2_frame.tech_label.grid(column=3, row=0, ipadx = 5)
self.toppane.title2_frame.tech_select = ttk.Button(self.toppane.title2_frame,
text=self.tech, style='normal.TButton', command=self.choose_tech)
self.toppane.title2_frame.tech_select.grid(column=4, row=0, ipadx = 3, padx = 3)
self.toppane.title2_frame.layout_label = ttk.Label(self.toppane.title2_frame, text="Layout:",
style = 'title.TLabel')
self.toppane.title2_frame.layout_label.grid(column=0, row=1, ipadx = 5)
self.toppane.title2_frame.layout_select = ttk.Button(self.toppane.title2_frame,
text=self.layout, style='normal.TButton', command=self.choose_layout)
self.toppane.title2_frame.layout_select.grid(column=1, row=1, ipadx = 3, padx = 3)
# Show top-level schematic cellname with select button. Initial cell name is the top-level cell.
self.toppane.title2_frame.schem_label = ttk.Label(self.toppane.title2_frame, text="Schematic:",
style = 'title.TLabel')
self.toppane.title2_frame.schem_label.grid(column=3, row=1, ipadx = 5)
self.toppane.title2_frame.schem_select = ttk.Button(self.toppane.title2_frame,
text=self.schematic, style='normal.TButton', command=self.choose_netlist)
self.toppane.title2_frame.schem_select.grid(column=4, row=1, ipadx = 3, padx = 3)
tooltip.ToolTip(self.toppane.title2_frame.project_select,
text = "Select new project")
tooltip.ToolTip(self.toppane.title2_frame.layout_select,
text = "Select a layout subcirucit to compare")
tooltip.ToolTip(self.toppane.title2_frame.schem_select,
text = "Select a schematic subcirucit to compare")
#---------------------------------------------
ttk.Separator(self.toppane, orient='horizontal').pack(side = 'top', fill = 'x')
#---------------------------------------------
# Create listbox of Circuit1 vs. Circuit2 results
height = 10
self.toppane.lvsreport = TreeViewSplit(self.toppane, fontsize = fontsize)
self.toppane.lvsreport.populate("Layout:", [], "Schematic:", [],
[["Run", True, self.run_lvs],
# ["Find", True, self.findrecord]
], height = height)
self.toppane.lvsreport.set_title("Line")
self.toppane.lvsreport.pack(side = 'top', fill = 'both', expand = 'true')
tooltip.ToolTip(self.toppane.lvsreport.get_button(0), text="Run LVS")
#---------------------------------------------
# ttk.Separator(self, orient='horizontal').grid(column=0, row=3, sticky='ew')
#---------------------------------------------
# Add a text window below the project name to capture output. Redirect
# print statements to it.
self.botpane.console = ttk.Frame(self.botpane)
self.botpane.console.pack(side = 'top', fill = 'both', expand = 'true')
self.text_box = ConsoleText(self.botpane.console, wrap='word', height = 4)
self.text_box.pack(side='left', fill='both', expand='true')
console_scrollbar = ttk.Scrollbar(self.botpane.console)
console_scrollbar.pack(side='right', fill='y')
# attach console to scrollbar
self.text_box.config(yscrollcommand = console_scrollbar.set)
console_scrollbar.config(command = self.text_box.yview)
# Add button bar at the bottom of the window
self.botpane.bbar = ttk.Frame(self.botpane)
self.botpane.bbar.pack(side = 'top', fill = 'x')
# Define the "quit" button and action
self.botpane.bbar.quit_button = ttk.Button(self.botpane.bbar, text='Quit', command=self.on_quit,
style = 'normal.TButton')
self.botpane.bbar.quit_button.grid(column=0, row=0, padx = 5)
# Define help button
if self.help:
self.botpane.bbar.help_button = ttk.Button(self.botpane.bbar, text='Help',
command=self.help.open, style = 'normal.TButton')
self.botpane.bbar.help_button.grid(column = 2, row = 0, padx = 5)
tooltip.ToolTip(self.botpane.bbar.help_button, text = "Show help window")
# Add the panes once the internal geometry is known.
pane.add(self.toppane)
pane.add(self.botpane)
pane.paneconfig(self.toppane, stretch='first')
# Redirect stdout and stderr to the console as the last thing to do. . .
# Otherwise errors in the GUI get sucked into the void.
self.stdout = sys.stdout
self.stderr = sys.stderr
sys.stdout = ConsoleText.StdoutRedirector(self.text_box)
sys.stderr = ConsoleText.StderrRedirector(self.text_box)
if message:
print(message)
def logprint(self, message, doflush=False):
if self.logfile:
self.logfile.buffer.write(message.encode('utf-8'))
self.logfile.buffer.write('\n'.encode('utf-8'))
if doflush:
self.logfile.flush()
def printout(self, output):
# Generate output
if not output:
return
outlines = output.splitlines()
for line in outlines:
try:
print(line)
except TypeError:
line = line.decode('utf-8')
pritn(line)
def printwarn(self, output):
# Check output for warning or error
if not output:
return 0
warnrex = re.compile('.*warning', re.IGNORECASE)
errrex = re.compile('.*error', re.IGNORECASE)
errors = 0
outlines = output.splitlines()
for line in outlines:
try:
wmatch = warnrex.match(line)
except TypeError:
line = line.decode('utf-8')
wmatch = warnrex.match(line)
ematch = errrex.match(line)
if ematch:
errors += 1
if ematch or wmatch:
print(line)
return errors
def choose_tech(self):
try:
project_path = self.rootpath
initdirname = self.rootpath + '/tech',
except:
print('Must choose a project first.')
return
techname = filedialog.askopenfilename(multiple=False,
initialdir = initdirname,
filetypes = (("Tcl script", "*.tcl"),("All Files","*.*")),
title = "Choose a netgen technology setup script.")
if techname != '':
print("Selected technology setup script " + techname)
techbase = os.path.split(techname)[1]
self.tech = os.path.splitext(techbase)[0]
self.lvs_setup = techname
self.toppane.title2_frame.layout_select.config(text = self.tech)
def choose_layout(self):
try:
project_path = self.rootpath
initdirname = self.rootpath + '/layout',
except:
print('Must choose a project first.')
return
cellname = filedialog.askopenfilename(multiple=False,
initialdir = initdirname,
filetypes = (("Magic layout", "*.mag"),("All Files","*.*")),
title = "Choose a layout cell to compare.")
if cellname != '':
print("Selected compare cell " + cellname)
cellbase = os.path.split(cellname)[1]
self.layout = os.path.splitext(cellbase)[0]
self.toppane.title2_frame.layout_select.config(text = self.layout)
def choose_netlist(self):
try:
project_path = self.rootpath
initdirname = self.rootpath + '/netlist/' + self.project + '.spi'
except:
print('Must choose a project first.')
return
cellname = filedialog.askopenfilename(multiple=False,
initialdir = initdirname,
filetypes = (("Spice netlist", "*.spi"),("Verilog netlist", "*.v")),
title = "Choose a netlist to compare.")
if cellname != '':
print("Selected compare cell " + cellname)
cellbase = os.path.split(cellname)[1]
self.schematic = os.path.splitext(cellbase)[0]
self.toppane.title2_frame.schem_select.config(text = self.schematic)
fileext = os.path.splitext(cellbase)[1]
if fileext == '.v':
self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
elif fileext == '.sp' or fileext == '.spi' or fileext == '.spice' or fileext == '.spc' or fileext == '.ckt':
self.toppane.title2_frame.schem_label.config(text = 'SPICE netlist:')
elif fileext == '.cdl':
self.toppane.title2_frame.schem_label.config(text = 'CDL netlist:')
else:
self.toppane.title2_frame.schem_label.config(text = 'Unknown netlist:')
def choose_project(self):
project = filedialog.askdirectory(initialdir = os.getcwd(),
title = "Find a project.")
if project != '':
print("Selected project " + str(project))
result = self.set_project(project)
def set_project(self, rootpath, project_name=None):
# Check if rootpath is valid. For LVS, there should be subdirectories
# "layout/" and "netlist/" or "verilog/".
haslay = os.path.isdir(rootpath + '/layout')
hasvlog = os.path.isdir(rootpath + '/verilog')
hasnet = os.path.isdir(rootpath + '/netlist')
if not haslay or not (hasvlog or hasnet):
if not haslay:
print("Project path has no layout (/layout) subdirectory.")
if not (hasvlog or hasnet):
print("Project path has no verilog (/verilog), or netlist (/netlist) subdirectory.")
# Continue anyway; assume that netlists will be selected manually
if self.logfile:
self.logfile.close()
self.logfile = None
if not project_name:
project = os.path.split(rootpath)[1]
else:
project = project_name
if self.project != project:
self.rootpath = rootpath
self.project = project
# Clear out old project data
self.toppane.lvsreport.repopulate([], [])
# Close any open logfile.
if self.logfile:
self.logfile.close()
self.logfile = None
# Put new log file called 'lvs.log' in the mag/ subdirectory
self.logfile = open(rootpath + '/layout/lvs.log', 'w')
# Print some initial information to the logfile.
self.logprint('Starting new log file ' + datetime.datetime.now().strftime('%c'),
doflush=True)
# Update project button
self.toppane.title2_frame.project_select.config(text = self.project)
self.toppane.title2_frame.path_label.config(text = self.rootpath)
# Cell name is the same as project name initially
self.layout = self.project
self.schematic = self.project
self.toppane.title2_frame.layout_select.config(text = self.layout)
self.toppane.title2_frame.schem_select.config(text = self.schematic)
# Update schematic button
if os.path.isfile(rootpath + '/verilog/' + self.schematic + '.v'):
self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
else:
self.toppane.title2_frame.schem_label.config(text = 'Schematic netlist:')
# If there is a comparison file that post-dates both netlists, load it.
self.check_lvs()
return True
def check_layout_out_of_date(self, spipath, layoutpath):
# Check if a netlist (spipath) is out-of-date relative to the layouts
# (layoutpath). Need to read the netlist and check all of the subcells.
need_capture = False
if not os.path.isfile(spipath):
return True
if os.path.isfile(layoutpath):
spi_statbuf = os.stat(spipath)
lay_statbuf = os.stat(layoutpath)
if spi_statbuf.st_mtime < lay_statbuf.st_mtime:
# netlist exists but is out-of-date
need_capture = True
else:
# only found that the top-level-layout is older than the
# netlist. Now need to read the netlist, find all subcircuits,
# and check those dates, too.
layoutdir = os.path.split(layoutpath)[0]
subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
with open(spipath, 'r') as ifile:
duttext = ifile.read()
dutlines = duttext.replace('\n+', ' ').splitlines()
for line in dutlines:
lmatch = subrex.match(line)
if lmatch:
subname = lmatch.group(1)
sublayout = layoutdir + '/' + subname + '.mag'
# subcircuits that cannot be found in the current directory are
# assumed to be library components and therefore never out-of-date.
if os.path.exists(sublayout):
sub_statbuf = os.stat(sublayout)
if spi_statbuf.st_mtime < lay_statbuf.st_mtime:
# netlist exists but is out-of-date
need_capture = True
break
return need_capture
def check_schematic_out_of_date(self, spipath, schempath):
# Check if a netlist (spipath) is out-of-date relative to the schematics
# (schempath). Need to read the netlist and check all of the subcells.
need_capture = False
if not os.path.isfile(spipath):
return True
if os.path.isfile(schempath):
spi_statbuf = os.stat(spipath)
sch_statbuf = os.stat(schempath)
if spi_statbuf.st_mtime < sch_statbuf.st_mtime:
# netlist exists but is out-of-date
need_capture = True
else:
# only found that the top-level-schematic is older than the
# netlist. Now need to read the netlist, find all subcircuits,
# and check those dates, too.
schemdir = os.path.split(schempath)[0]
subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
with open(spipath, 'r') as ifile:
duttext = ifile.read()
dutlines = duttext.replace('\n+', ' ').splitlines()
for line in dutlines:
lmatch = subrex.match(line)
if lmatch:
subname = lmatch.group(1)
# NOTE: Electric uses library:cell internally to track libraries,
# and maps the ":" to "__" in the netlist. Not entirely certain that
# the double-underscore uniquely identifies the library:cell. . .
librex = re.compile('(.*)__(.*)', re.IGNORECASE)
lmatch = librex.match(subname)
if lmatch:
elecpath = os.path.split(os.path.split(schempath)[0])[0]
libname = lmatch.group(1)
subschem = elecpath + '/' + libname + '.delib/' + lmatch.group(2) + '.sch'
else:
libname = {}
subschem = schemdir + '/' + subname + '.sch'
# subcircuits that cannot be found in the current directory are
# assumed to be library components and therefore never out-of-date.
if os.path.exists(subschem):
sub_statbuf = os.stat(subschem)
if spi_statbuf.st_mtime < sub_statbuf.st_mtime:
# netlist exists but is out-of-date
need_capture = True
break
# mapping of characters to what's allowed in SPICE makes finding
# the associated schematic file a bit difficult. Requires wild-card
# searching.
elif libname:
restr = lmatch.group(2) + '.sch'
restr = restr.replace('.', '\.')
restr = restr.replace('_', '.')
schrex = re.compile(restr, re.IGNORECASE)
libpath = elecpath + '/' + libname + '.delib'
if os.path.exists(libpath):
liblist = os.listdir(libpath)
for file in liblist:
lmatch = schrex.match(file)
if lmatch:
subschem = libpath + '/' + file
sub_statbuf = os.stat(subschem)
if spi_statbuf.st_mtime < sch_statbuf.st_mtime:
# netlist exists but is out-of-date
need_capture = True
break
return need_capture
def check_lvs(self):
# If both netlists exist, and comp.json is more recent than both, then
# load LVS results from comp.json
project_path = self.rootpath
project_name = self.project
layout_path = project_path + '/layout/' + project_name + '.spc'
net_path = project_path + '/netlist/' + project_name + '.spi'
comp_path = project_path + '/layout/comp.json'
if os.path.exists(layout_path) and os.path.exists(net_path) and os.path.exists(comp_path):
magtime = os.stat(layout_path).st_mtime
schemtime = os.stat(net_path).st_mtime
comptime = os.stat(comp_path).st_mtime
if comptime > magtime and comptime > schemtime:
print("Loading LVS results from file.")
self.generate(comp_path)
def generate_layout_netlist(self, layout_path, layout_src, project_path):
# Does layout netlist exist and is it current?
if self.check_layout_out_of_date(layout_path, layout_src):
print('Generating layout netlist.')
self.update_idletasks()
mproc = subprocess.Popen(['magic', '-dnull', '-noconsole',
self.layout], stdin = subprocess.PIPE, stdout = subprocess.PIPE,
stderr = subprocess.PIPE, cwd = project_path + '/layout',
universal_newlines = True)
mproc.stdin.write("select top cell\n")
mproc.stdin.write("expand\n")
mproc.stdin.write("extract all\n")
mproc.stdin.write("ext2spice hierarchy on\n")
mproc.stdin.write("ext2spice format ngspice\n")
mproc.stdin.write("ext2spice scale off\n")
mproc.stdin.write("ext2spice renumber off\n")
mproc.stdin.write("ext2spice subcircuit top auto\n")
mproc.stdin.write("ext2spice cthresh infinite\n")
mproc.stdin.write("ext2spice rthresh infinite\n")
mproc.stdin.write("ext2spice blackbox on\n")
mproc.stdin.write("ext2spice -o " + self.layout + ".spi\n")
mproc.stdin.write("quit -noprompt\n")
magicout = mproc.communicate()[0]
self.printwarn(magicout)
if mproc.returncode != 0:
print('Failure to generate new layout netlist.')
return False
# Move .spi netlist to project_dir/netlist/lvs/
shutil.move(project_path + '/layout/' + self.layout + '.spi', layout_path)
# Remove extraction files
for file in os.listdir(project_path + '/layout'):
if os.path.splitext(file)[1] == '.ext':
os.remove(project_path + '/layout/' + file)
else:
print('Layout netlist is up-to-date, not regenerating.')
return True
def run_lvs(self, value):
# "value" is ignored (?)
# Check if netlists exist and are current; otherwise create them.
# Then run LVS.
project_path = self.rootpath
project_name = self.project
comp_path = project_path + '/layout/comp.json'
has_vlog = False
vlog_path = project_path + '/verilog/' + project_name + '.v'
layout_path = project_path + '/netlist/lvs/' + self.layout + '.spi'
net_path = project_path + '/netlist/schem/' + self.schematic + '.spi'
layout_src = project_path + '/layout/' + self.layout + '.mag'
# Does the setup file exist (this is optional)?
if self.lvs_setup != '' and not os.path.isfile('setup.tcl'):
print('No technology setup file selected.')
# Does schematic netlist exist?
if not os.path.isfile(vlog_path) and not os.path.isfile(net_path):
print('Error: No schematic netlist or verilog netlist.')
return
# Does LVS netlist subdirectory exist?
if not os.path.exists(project_path + '/netlist/lvs'):
os.makedirs(project_path + '/netlist/lvs')
# Does layout netlist exist and is it current?
if not self.generate_layout_netlist(layout_path, layout_src, project_path):
return False
# Final check
if not os.path.isfile(layout_path):
print('Error: No netlist generated from magic.')
return
else:
# Read in netlist and convert commas from [X,Y] arrays to vertical bars
# as something that can be converted back as necessary. ngspice treats
# commas as special characters for some reason.
with open(layout_path) as ifile:
spitext = ifile.read()
# spilines = spitext.replace(',', '|')
# with open(layout_path, 'w') as ofile:
# ofile.write(spilines)
# Check the netlist to see if the cell to match is a subcircuit. If
# not, then assume it is the top level.
is_subckt = False
subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
dutlines = spitext.replace('\n+', ' ').splitlines()
for line in dutlines:
lmatch = subrex.match(line)
if lmatch:
subname = lmatch.group(1)
if subname == self.layout:
is_subckt = True
break
if is_subckt:
layout_arg = layout_path + ' ' + self.layout
layout_text = '"' + layout_arg + '"'
else:
layout_arg = layout_path
layout_text = layout_arg
if has_vlog:
schem_arg = vlog_path + ' ' + self.schematic
else:
schem_arg = net_path + ' ' + self.schematic
schem_text = '"' + schem_arg + '"'
# Remove any previous comparison output file
comp_out_path = os.path.splitext(comp_path)[0] + '.out'
if os.path.exists(comp_out_path):
os.remove(comp_out_path)
# Run netgen as subprocess
print('Running: netgen -batch lvs ' + layout_text +
' ' + schem_text + ' ' + self.lvs_setup + ' ' + comp_out_path +
' -json -blackbox')
# Note: Because arguments to subprocess are list items, the {filename cell}
# pair does *not* have to be quoted or braced. Doing so causes a parse
# error.
self.lvsproc = subprocess.Popen(['netgen', '-batch', 'lvs',
layout_arg, schem_arg,
self.lvs_setup, comp_out_path, '-json', '-blackbox'],
cwd=project_path + '/layout',
stdout=subprocess.PIPE, stderr=subprocess.PIPE, bufsize=0)
# This is largely unnecessary as netgen usually runs to completion very quickly.
self.watchclock(comp_path)
def watchclock(self, filename):
if self.lvsproc == None:
return
lvs_status = self.lvsproc.poll()
sresult = select.select([self.lvsproc.stdout, self.lvsproc.stderr], [], [], 0)[0]
if self.lvsproc.stdout in sresult:
outstring = self.lvsproc.stdout.readline().decode().strip()
self.logprint(outstring, doflush=True)
print(outstring)
elif self.lvsproc.stderr in sresult:
errstring = self.lvsproc.stderr.readline().decode().strip()
self.logprint(errstring, doflush = True)
print(errstring, file=sys.stderr)
if lvs_status != None:
print("netgen LVS exited with status " + str(lvs_status))
self.lvsproc = None
if lvs_status != 0:
print('Errors encountered in LVS.')
self.logprint('Errors in LVS, lvs status = ' + str(lvs_status), doflush=True)
# Done; now read comp.json and fill the treeview listbox.
self.generate(filename)
else:
self.after(500, lambda: self.watchclock(filename))
# Generate display from "comp.out" file (json file now preferred)
def generate_orig(self, lvspath):
lefttext = []
righttext = []
print("Reading LVS output file " + lvspath)
if os.path.exists(lvspath):
with open(lvspath, 'r') as ifile:
lvslines = ifile.read().splitlines()
for line in lvslines:
if '|' in line:
# parts = line.split('|')
# lefttext.append(parts[0])
# righttext.append(parts[1])
lefttext.append(line[0:42].strip())
righttext.append(line[44:].strip())
else:
lefttext.append(line)
righttext.append('')
# Populate treeview with text
self.toppane.lvsreport.repopulate(lefttext, righttext)
else:
print("Error: No output file generated from LVS.")
# Generate output from LVS report JSON file comp.json
def generate(self, lvspath):
lefttext = []
righttext = []
print("Reading LVS output file " + lvspath)
if os.path.exists(lvspath):
with open(lvspath, 'r') as ifile:
self.lvsdata = json.load(ifile)
# Populate treeview with text
self.toppane.lvsreport.json_repopulate(self.lvsdata)
else:
print("Error: No output file generated from LVS.")
def findrecord(self, value):
print("Unimplemented function")
def findrecord_test(self, value):
# Check if socket is defined; if not, attempt to open one
if not self.msock:
try:
self.msock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
except:
print("No response from layout tool.")
if self.msock:
self.msock.connect(("0.0.0.0", 12946))
self.msock.setblocking(False)
if self.msock:
# Pull name of net or device from 'value'
# This is a test:
self.msock.sendall(b'box 0 0 100 100\r\n')
if __name__ == '__main__':
options = []
arguments = []
for item in sys.argv[1:]:
if item.find('-', 0) == 0:
options.append(item)
else:
arguments.append(item)
root = tkinter.Tk()
app = LVSManager(root)
if arguments:
if len(arguments) >= 2:
app.set_project(arguments[0], project_name=arguments[1])
else:
app.set_project(arguments[0])
root.mainloop()
+108 -36
View File
@@ -343,7 +343,7 @@ class LVSManager(ttk.Frame):
techbase = os.path.split(techname)[1]
self.tech = os.path.splitext(techbase)[0]
self.lvs_setup = techname
self.toppane.title2_frame.layout_select.config(text = self.tech)
self.toppane.title2_frame.tech_select.config(text = self.tech)
def choose_layout(self):
try:
@@ -358,30 +358,37 @@ class LVSManager(ttk.Frame):
title = "Choose a layout cell to compare.")
if cellname != '':
print("Selected compare cell " + cellname)
self.layout = cellname
cellbase = os.path.split(cellname)[1]
self.layout = os.path.splitext(cellbase)[0]
self.toppane.title2_frame.layout_select.config(text = self.layout)
layoutname = os.path.splitext(cellbase)[0]
self.toppane.title2_frame.layout_select.config(text = layoutname)
fileext = os.path.splitext(cellbase)[1]
if fileext == '.mag':
self.toppane.title2_frame.layout_label.config(text = 'Layout:')
else:
self.toppane.title2_frame.layout_label.config(text = 'Layout netlist:')
def choose_netlist(self):
try:
project_path = self.rootpath
initdirname = self.rootpath + '/netlist/' + self.project + '.spi'
initdirname = self.rootpath + '/netlist/' + self.project + '.spice'
except:
print('Must choose a project first.')
return
cellname = filedialog.askopenfilename(multiple=False,
initialdir = initdirname,
filetypes = (("Spice netlist", "*.spi"),("Verilog netlist", "*.v")),
filetypes = (("Spice netlist", "*.spice"),("Verilog netlist", "*.v"),("All Files","*.*")),
title = "Choose a netlist to compare.")
if cellname != '':
print("Selected compare cell " + cellname)
self.schematic = cellname
cellbase = os.path.split(cellname)[1]
self.schematic = os.path.splitext(cellbase)[0]
self.toppane.title2_frame.schem_select.config(text = self.schematic)
schematic_name = os.path.splitext(cellbase)[0]
self.toppane.title2_frame.schem_select.config(text = schematic_name)
fileext = os.path.splitext(cellbase)[1]
if fileext == '.v':
self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
elif fileext == '.sp' or fileext == '.spi' or fileext == '.spice' or fileext == '.spc' or fileext == '.ckt':
elif fileext == '.sp' or fileext == '.spice' or fileext == '.spi' or fileext == '.spc' or fileext == '.ckt':
self.toppane.title2_frame.schem_label.config(text = 'SPICE netlist:')
elif fileext == '.cdl':
self.toppane.title2_frame.schem_label.config(text = 'CDL netlist:')
@@ -433,7 +440,10 @@ class LVSManager(ttk.Frame):
self.logfile = None
# Put new log file called 'lvs.log' in the mag/ subdirectory
self.logfile = open(rootpath + '/layout/lvs.log', 'w')
if os.path.exists(rootpath + '/layout'):
self.logfile = open(rootpath + '/layout/lvs.log', 'w')
else:
self.logfile = open(rootpath + '/lvs.log', 'w')
# Print some initial information to the logfile.
self.logprint('Starting new log file ' + datetime.datetime.now().strftime('%c'),
doflush=True)
@@ -444,15 +454,23 @@ class LVSManager(ttk.Frame):
# Cell name is the same as project name initially
self.layout = self.project
self.schematic = self.project
self.toppane.title2_frame.layout_select.config(text = self.layout)
self.toppane.title2_frame.schem_select.config(text = self.schematic)
layname = os.path.splitext(os.path.split(self.layout)[1])[0]
self.toppane.title2_frame.layout_select.config(text = layname)
schemname = os.path.splitext(os.path.split(self.schematic)[1])[0]
self.toppane.title2_frame.schem_select.config(text = schemname)
# Update schematic button
if os.path.isfile(rootpath + '/verilog/' + self.schematic + '.v'):
if os.path.splitext(self.schematic)[1] == '.v':
self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
else:
self.toppane.title2_frame.schem_label.config(text = 'Schematic netlist:')
# Update layout button
if os.path.splitext(self.layout)[1] == '.mag':
self.toppane.title2_frame.schem_label.config(text = 'Layout:')
else:
self.toppane.title2_frame.schem_label.config(text = 'Layout netlist:')
# If there is a comparison file that post-dates both netlists, load it.
self.check_lvs()
return True
@@ -567,8 +585,8 @@ class LVSManager(ttk.Frame):
# load LVS results from comp.json
project_path = self.rootpath
project_name = self.project
layout_path = project_path + '/layout/' + project_name + '.spc'
net_path = project_path + '/netlist/' + project_name + '.spi'
layout_path = project_path + '/layout/' + project_name + '.spice'
net_path = project_path + '/netlist/' + project_name + '.spice'
comp_path = project_path + '/layout/comp.json'
if os.path.exists(layout_path) and os.path.exists(net_path) and os.path.exists(comp_path):
@@ -599,7 +617,7 @@ class LVSManager(ttk.Frame):
mproc.stdin.write("ext2spice cthresh infinite\n")
mproc.stdin.write("ext2spice rthresh infinite\n")
mproc.stdin.write("ext2spice blackbox on\n")
mproc.stdin.write("ext2spice -o " + self.layout + ".spi\n")
mproc.stdin.write("ext2spice -o " + self.layout + ".spice\n")
mproc.stdin.write("quit -noprompt\n")
magicout = mproc.communicate()[0]
self.printwarn(magicout)
@@ -607,8 +625,8 @@ class LVSManager(ttk.Frame):
print('Failure to generate new layout netlist.')
return False
# Move .spi netlist to project_dir/netlist/lvs/
shutil.move(project_path + '/layout/' + self.layout + '.spi', layout_path)
# Move .spice netlist to project_dir/netlist/lvs/
shutil.move(project_path + '/layout/' + self.layout + '.spice', layout_path)
# Remove extraction files
for file in os.listdir(project_path + '/layout'):
if os.path.splitext(file)[1] == '.ext':
@@ -625,17 +643,37 @@ class LVSManager(ttk.Frame):
project_path = self.rootpath
project_name = self.project
comp_path = project_path + '/layout/comp.json'
# Diagnostic:
print('project_name is ' + project_name)
print('project_path is ' + project_path)
print('self.layout is ' + self.layout)
print('self.schematic is ' + self.schematic)
print('self.lvs_setup is ' + self.lvs_setup)
has_vlog = False
vlog_path = project_path + '/verilog/' + project_name + '.v'
layout_path = project_path + '/netlist/lvs/' + self.layout + '.spi'
net_path = project_path + '/netlist/schem/' + self.schematic + '.spi'
layout_src = project_path + '/layout/' + self.layout + '.mag'
if os.path.isfile(self.layout):
layout_path = self.layout
layout_src = None
else:
layout_path = project_path + '/netlist/lvs/' + self.layout + '.spice'
layout_src = project_path + '/layout/' + self.layout + '.mag'
comp_dir = os.path.split(layout_path)[0]
comp_path = comp_dir + '/comp.json'
if os.path.isfile(self.schematic):
net_path = self.schematic
else:
net_path = project_path + '/netlist/schem/' + self.schematic + '.spice'
# Does the setup file exist (this is optional)?
if self.lvs_setup != '' and not os.path.isfile('setup.tcl'):
if self.lvs_setup == '' and not os.path.isfile('setup.tcl'):
print('No technology setup file selected.')
elif not os.path.isfile(self.lvs_setup):
print("Can't find technology setup file " + self.lvs_setup)
# Does schematic netlist exist?
if not os.path.isfile(vlog_path) and not os.path.isfile(net_path):
@@ -643,14 +681,16 @@ class LVSManager(ttk.Frame):
return
# Does LVS netlist subdirectory exist?
if not os.path.exists(project_path + '/netlist/lvs'):
os.makedirs(project_path + '/netlist/lvs')
if os.path.exists(project_path + '/netlist'):
if not os.path.exists(project_path + '/netlist/lvs'):
os.makedirs(project_path + '/netlist/lvs')
# Does layout netlist exist and is it current?
if not self.generate_layout_netlist(layout_path, layout_src, project_path):
return False
if layout_src:
if not self.generate_layout_netlist(layout_path, layout_src, project_path):
return False
# Final check
# Final checks
if not os.path.isfile(layout_path):
print('Error: No netlist generated from magic.')
return
@@ -662,26 +702,27 @@ class LVSManager(ttk.Frame):
with open(layout_path) as ifile:
spitext = ifile.read()
# spilines = spitext.replace(',', '|')
# with open(layout_path, 'w') as ofile:
# ofile.write(spilines)
# Check the netlist to see if the cell to match is a subcircuit. If
# not, then assume it is the top level.
layoutcell = os.path.splitext(os.path.split(self.layout)[1])[0]
is_subckt = False
subname = None
subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
dutlines = spitext.replace('\n+', ' ').splitlines()
for line in dutlines:
lmatch = subrex.match(line)
if lmatch:
subname = lmatch.group(1)
if subname == self.layout:
if subname == layoutcell:
is_subckt = True
break
if is_subckt:
layout_arg = layout_path + ' ' + self.layout
layout_arg = self.layout + ' ' + layoutcell
layout_text = '"' + layout_arg + '"'
elif subname:
layout_arg = self.layout + ' ' + subname
layout_text = '"' + layout_arg + '"'
else:
layout_arg = layout_path
@@ -690,8 +731,39 @@ class LVSManager(ttk.Frame):
if has_vlog:
schem_arg = vlog_path + ' ' + self.schematic
else:
schem_arg = net_path + ' ' + self.schematic
schem_text = '"' + schem_arg + '"'
# Final checks
if not os.path.isfile(net_path):
print('Error: No netlist from schematic.')
return
with open(net_path) as ifile:
spitext = ifile.read()
# Check the netlist to see if the cell to match is a subcircuit. If
# not, then assume it is the top level.
schemcell = os.path.splitext(os.path.split(self.schematic)[1])[0]
subname = None
is_subckt = False
subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
dutlines = spitext.replace('\n+', ' ').splitlines()
for line in dutlines:
lmatch = subrex.match(line)
if lmatch:
subname = lmatch.group(1)
if subname == schemcell:
is_subckt = True
break
if is_subckt:
schem_arg = self.schematic + ' ' + schemcell
schem_text = '"' + schem_arg + '"'
elif subname:
schem_arg = self.schematic + ' ' + subname
schem_text = '"' + schem_arg + '"'
else:
schem_arg = net_path
schem_text = schem_arg
# Remove any previous comparison output file
comp_out_path = os.path.splitext(comp_path)[0] + '.out'
@@ -708,7 +780,7 @@ class LVSManager(ttk.Frame):
self.lvsproc = subprocess.Popen(['netgen', '-batch', 'lvs',
layout_arg, schem_arg,
self.lvs_setup, comp_out_path, '-json', '-blackbox'],
cwd=project_path + '/layout',
cwd=comp_dir,
stdout=subprocess.PIPE, stderr=subprocess.PIPE, bufsize=0)
# This is largely unnecessary as netgen usually runs to completion very quickly.
self.watchclock(comp_path)
-772
View File
@@ -1,772 +0,0 @@
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
It was created by netgen configure 1.3, which was
generated by GNU Autoconf 2.69. Invocation command line was
$ ./configure
## --------- ##
## Platform. ##
## --------- ##
hostname = stravinsky
uname -m = x86_64
uname -r = 4.1.13-100.fc21.x86_64
uname -s = Linux
uname -v = #1 SMP Tue Nov 10 13:13:20 UTC 2015
/usr/bin/uname -p = x86_64
/bin/uname -X = unknown
/bin/arch = x86_64
/usr/bin/arch -k = unknown
/usr/convex/getsysinfo = unknown
/usr/bin/hostinfo = unknown
/bin/machine = unknown
/usr/bin/oslevel = unknown
/bin/universe = unknown
PATH: .
PATH: /bin
PATH: /sbin
PATH: /usr/bin
PATH: /usr/sbin
PATH: /usr/local/bin
## ----------- ##
## Core tests. ##
## ----------- ##
configure:2398: checking build system type
configure:2412: result: x86_64-unknown-linux-gnu
configure:2432: checking host system type
configure:2445: result: x86_64-unknown-linux-gnu
configure:2465: checking target system type
configure:2478: result: x86_64-unknown-linux-gnu
configure:2569: checking for gcc
configure:2585: found /bin/gcc
configure:2596: result: gcc
configure:2825: checking for C compiler version
configure:2834: gcc --version >&5
gcc (GCC) 4.9.2 20150212 (Red Hat 4.9.2-6)
Copyright (C) 2014 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
configure:2845: $? = 0
configure:2834: gcc -v >&5
Using built-in specs.
COLLECT_GCC=gcc
COLLECT_LTO_WRAPPER=/usr/libexec/gcc/x86_64-redhat-linux/4.9.2/lto-wrapper
Target: x86_64-redhat-linux
Configured with: ../configure --prefix=/usr --mandir=/usr/share/man --infodir=/usr/share/info --with-bugurl=http://bugzilla.redhat.com/bugzilla --enable-bootstrap --enable-shared --enable-threads=posix --enable-checking=release --enable-multilib --with-system-zlib --enable-__cxa_atexit --disable-libunwind-exceptions --enable-gnu-unique-object --enable-linker-build-id --with-linker-hash-style=gnu --enable-languages=c,c++,objc,obj-c++,fortran,ada,go,lto --enable-plugin --enable-initfini-array --disable-libgcj --with-isl=/builddir/build/BUILD/gcc-4.9.2-20150212/obj-x86_64-redhat-linux/isl-install --with-cloog=/builddir/build/BUILD/gcc-4.9.2-20150212/obj-x86_64-redhat-linux/cloog-install --enable-gnu-indirect-function --with-tune=generic --with-arch_32=i686 --build=x86_64-redhat-linux
Thread model: posix
gcc version 4.9.2 20150212 (Red Hat 4.9.2-6) (GCC)
configure:2845: $? = 0
configure:2834: gcc -V >&5
gcc: error: unrecognized command line option '-V'
gcc: fatal error: no input files
compilation terminated.
configure:2845: $? = 4
configure:2834: gcc -qversion >&5
gcc: error: unrecognized command line option '-qversion'
gcc: fatal error: no input files
compilation terminated.
configure:2845: $? = 4
configure:2865: checking whether the C compiler works
configure:2887: gcc -g conftest.c >&5
configure:2891: $? = 0
configure:2939: result: yes
configure:2942: checking for C compiler default output file name
configure:2944: result: a.out
configure:2950: checking for suffix of executables
configure:2957: gcc -o conftest -g conftest.c >&5
configure:2961: $? = 0
configure:2983: result:
configure:3005: checking whether we are cross compiling
configure:3013: gcc -o conftest -g conftest.c >&5
configure:3017: $? = 0
configure:3024: ./conftest
configure:3028: $? = 0
configure:3043: result: no
configure:3048: checking for suffix of object files
configure:3070: gcc -c -g conftest.c >&5
configure:3074: $? = 0
configure:3095: result: o
configure:3099: checking whether we are using the GNU C compiler
configure:3118: gcc -c -g conftest.c >&5
configure:3118: $? = 0
configure:3127: result: yes
configure:3136: checking whether gcc accepts -g
configure:3156: gcc -c -g conftest.c >&5
configure:3156: $? = 0
configure:3197: result: yes
configure:3214: checking for gcc option to accept ISO C89
configure:3277: gcc -c -g conftest.c >&5
configure:3277: $? = 0
configure:3290: result: none needed
configure:3315: checking how to run the C preprocessor
configure:3346: gcc -E conftest.c
configure:3346: $? = 0
configure:3360: gcc -E conftest.c
conftest.c:11:28: fatal error: ac_nonexistent.h: No such file or directory
#include <ac_nonexistent.h>
^
compilation terminated.
configure:3360: $? = 1
configure: failed program was:
| /* confdefs.h */
| #define PACKAGE_NAME "netgen"
| #define PACKAGE_TARNAME "netgen"
| #define PACKAGE_VERSION "1.3"
| #define PACKAGE_STRING "netgen 1.3"
| #define PACKAGE_BUGREPORT "[email protected]"
| #define PACKAGE_URL ""
| #define NETGEN_VERSION "1.5"
| #define NETGEN_REVISION "102"
| /* end confdefs.h. */
| #include <ac_nonexistent.h>
configure:3385: result: gcc -E
configure:3405: gcc -E conftest.c
configure:3405: $? = 0
configure:3419: gcc -E conftest.c
conftest.c:11:28: fatal error: ac_nonexistent.h: No such file or directory
#include <ac_nonexistent.h>
^
compilation terminated.
configure:3419: $? = 1
configure: failed program was:
| /* confdefs.h */
| #define PACKAGE_NAME "netgen"
| #define PACKAGE_TARNAME "netgen"
| #define PACKAGE_VERSION "1.3"
| #define PACKAGE_STRING "netgen 1.3"
| #define PACKAGE_BUGREPORT "[email protected]"
| #define PACKAGE_URL ""
| #define NETGEN_VERSION "1.5"
| #define NETGEN_REVISION "102"
| /* end confdefs.h. */
| #include <ac_nonexistent.h>
configure:3448: checking for library containing strerror
configure:3479: gcc -o conftest -g conftest.c >&5
configure:3479: $? = 0
configure:3496: result: none required
configure:3518: checking for a BSD-compatible install
configure:3586: result: /bin/install -c
configure:3640: checking for ranlib
configure:3656: found /bin/ranlib
configure:3667: result: ranlib
configure:3694: checking for gm4
configure:3727: result: no
configure:3694: checking for gnum4
configure:3727: result: no
configure:3694: checking for m4
configure:3712: found /bin/m4
configure:3724: result: /bin/m4
configure:3765: checking for ld used by GCC
configure:3828: result: /bin/ld
configure:3835: checking if the linker (/bin/ld) is GNU ld
GNU ld version 2.24
configure:3847: result: yes
configure:3854: checking for grep that handles long lines and -e
configure:3912: result: /bin/grep
configure:3917: checking for egrep
configure:3979: result: /bin/grep -E
configure:3984: checking for ANSI C header files
configure:4004: gcc -c -g conftest.c >&5
configure:4004: $? = 0
configure:4077: gcc -o conftest -g conftest.c >&5
configure:4077: $? = 0
configure:4077: ./conftest
configure:4077: $? = 0
configure:4088: result: yes
configure:4101: checking for sys/types.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for sys/stat.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for stdlib.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for string.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for memory.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for strings.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for inttypes.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for stdint.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for unistd.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4117: checking size of void *
configure:4122: gcc -o conftest -g conftest.c >&5
configure:4122: $? = 0
configure:4122: ./conftest
configure:4122: $? = 0
configure:4136: result: 8
configure:4150: checking size of unsigned int
configure:4155: gcc -o conftest -g conftest.c >&5
configure:4155: $? = 0
configure:4155: ./conftest
configure:4155: $? = 0
configure:4169: result: 4
configure:4183: checking size of unsigned long
configure:4188: gcc -o conftest -g conftest.c >&5
configure:4188: $? = 0
configure:4188: ./conftest
configure:4188: $? = 0
configure:4202: result: 8
configure:4216: checking size of unsigned long long
configure:4221: gcc -o conftest -g conftest.c >&5
configure:4221: $? = 0
configure:4221: ./conftest
configure:4221: $? = 0
configure:4235: result: 8
configure:4246: checking whether byte ordering is bigendian
configure:4261: gcc -c -g conftest.c >&5
conftest.c:26:9: error: unknown type name 'not'
not a universal capable compiler
^
conftest.c:26:15: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'universal'
not a universal capable compiler
^
conftest.c:26:15: error: unknown type name 'universal'
configure:4261: $? = 1
configure: failed program was:
| /* confdefs.h */
| #define PACKAGE_NAME "netgen"
| #define PACKAGE_TARNAME "netgen"
| #define PACKAGE_VERSION "1.3"
| #define PACKAGE_STRING "netgen 1.3"
| #define PACKAGE_BUGREPORT "[email protected]"
| #define PACKAGE_URL ""
| #define NETGEN_VERSION "1.5"
| #define NETGEN_REVISION "102"
| #define STDC_HEADERS 1
| #define HAVE_SYS_TYPES_H 1
| #define HAVE_SYS_STAT_H 1
| #define HAVE_STDLIB_H 1
| #define HAVE_STRING_H 1
| #define HAVE_MEMORY_H 1
| #define HAVE_STRINGS_H 1
| #define HAVE_INTTYPES_H 1
| #define HAVE_STDINT_H 1
| #define HAVE_UNISTD_H 1
| #define SIZEOF_VOID_P 8
| #define SIZEOF_UNSIGNED_INT 4
| #define SIZEOF_UNSIGNED_LONG 8
| #define SIZEOF_UNSIGNED_LONG_LONG 8
| /* end confdefs.h. */
| #ifndef __APPLE_CC__
| not a universal capable compiler
| #endif
| typedef int dummy;
|
configure:4306: gcc -c -g conftest.c >&5
configure:4306: $? = 0
configure:4324: gcc -c -g conftest.c >&5
conftest.c: In function 'main':
conftest.c:32:4: error: unknown type name 'not'
not big endian
^
conftest.c:32:12: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'endian'
not big endian
^
configure:4324: $? = 1
configure: failed program was:
| /* confdefs.h */
| #define PACKAGE_NAME "netgen"
| #define PACKAGE_TARNAME "netgen"
| #define PACKAGE_VERSION "1.3"
| #define PACKAGE_STRING "netgen 1.3"
| #define PACKAGE_BUGREPORT "[email protected]"
| #define PACKAGE_URL ""
| #define NETGEN_VERSION "1.5"
| #define NETGEN_REVISION "102"
| #define STDC_HEADERS 1
| #define HAVE_SYS_TYPES_H 1
| #define HAVE_SYS_STAT_H 1
| #define HAVE_STDLIB_H 1
| #define HAVE_STRING_H 1
| #define HAVE_MEMORY_H 1
| #define HAVE_STRINGS_H 1
| #define HAVE_INTTYPES_H 1
| #define HAVE_STDINT_H 1
| #define HAVE_UNISTD_H 1
| #define SIZEOF_VOID_P 8
| #define SIZEOF_UNSIGNED_INT 4
| #define SIZEOF_UNSIGNED_LONG 8
| #define SIZEOF_UNSIGNED_LONG_LONG 8
| /* end confdefs.h. */
| #include <sys/types.h>
| #include <sys/param.h>
|
| int
| main ()
| {
| #if BYTE_ORDER != BIG_ENDIAN
| not big endian
| #endif
|
| ;
| return 0;
| }
configure:4452: result: no
configure:4471: checking for ANSI C header files
configure:4575: result: yes
configure:4587: checking for setenv
configure:4587: gcc -o conftest -g conftest.c >&5
configure:4587: $? = 0
configure:4587: result: yes
configure:4587: checking for putenv
configure:4587: gcc -o conftest -g conftest.c >&5
configure:4587: $? = 0
configure:4587: result: yes
configure:4597: checking for vfork
configure:4597: gcc -o conftest -g conftest.c >&5
configure:4597: $? = 0
configure:4597: result: yes
configure:4605: checking dirent.h usability
configure:4605: gcc -c -g conftest.c >&5
configure:4605: $? = 0
configure:4605: result: yes
configure:4605: checking dirent.h presence
configure:4605: gcc -E -x c conftest.c
configure:4605: $? = 0
configure:4605: result: yes
configure:4605: checking for dirent.h
configure:4605: result: yes
configure:4618: checking limits.h usability
configure:4618: gcc -c -g conftest.c >&5
configure:4618: $? = 0
configure:4618: result: yes
configure:4618: checking limits.h presence
configure:4618: gcc -E -x c conftest.c
configure:4618: $? = 0
configure:4618: result: yes
configure:4618: checking for limits.h
configure:4618: result: yes
configure:4631: checking param.h usability
configure:4631: gcc -c -g conftest.c >&5
conftest.c:63:19: fatal error: param.h: No such file or directory
#include <param.h>
^
compilation terminated.
configure:4631: $? = 1
configure: failed program was:
| /* confdefs.h */
| #define PACKAGE_NAME "netgen"
| #define PACKAGE_TARNAME "netgen"
| #define PACKAGE_VERSION "1.3"
| #define PACKAGE_STRING "netgen 1.3"
| #define PACKAGE_BUGREPORT "[email protected]"
| #define PACKAGE_URL ""
| #define NETGEN_VERSION "1.5"
| #define NETGEN_REVISION "102"
| #define STDC_HEADERS 1
| #define HAVE_SYS_TYPES_H 1
| #define HAVE_SYS_STAT_H 1
| #define HAVE_STDLIB_H 1
| #define HAVE_STRING_H 1
| #define HAVE_MEMORY_H 1
| #define HAVE_STRINGS_H 1
| #define HAVE_INTTYPES_H 1
| #define HAVE_STDINT_H 1
| #define HAVE_UNISTD_H 1
| #define SIZEOF_VOID_P 8
| #define SIZEOF_UNSIGNED_INT 4
| #define SIZEOF_UNSIGNED_LONG 8
| #define SIZEOF_UNSIGNED_LONG_LONG 8
| #define STDC_HEADERS 1
| #define HAVE_SETENV 1
| #define HAVE_PUTENV 1
| #define HAVE_DIRENT_H 1
| #define HAVE_LIMITS_H 1
| /* end confdefs.h. */
| #include <stdio.h>
| #ifdef HAVE_SYS_TYPES_H
| # include <sys/types.h>
| #endif
| #ifdef HAVE_SYS_STAT_H
| # include <sys/stat.h>
| #endif
| #ifdef STDC_HEADERS
| # include <stdlib.h>
| # include <stddef.h>
| #else
| # ifdef HAVE_STDLIB_H
| # include <stdlib.h>
| # endif
| #endif
| #ifdef HAVE_STRING_H
| # if !defined STDC_HEADERS && defined HAVE_MEMORY_H
| # include <memory.h>
| # endif
| # include <string.h>
| #endif
| #ifdef HAVE_STRINGS_H
| # include <strings.h>
| #endif
| #ifdef HAVE_INTTYPES_H
| # include <inttypes.h>
| #endif
| #ifdef HAVE_STDINT_H
| # include <stdint.h>
| #endif
| #ifdef HAVE_UNISTD_H
| # include <unistd.h>
| #endif
| #include <param.h>
configure:4631: result: no
configure:4631: checking param.h presence
configure:4631: gcc -E -x c conftest.c
conftest.c:30:19: fatal error: param.h: No such file or directory
#include <param.h>
^
compilation terminated.
configure:4631: $? = 1
configure: failed program was:
| /* confdefs.h */
| #define PACKAGE_NAME "netgen"
| #define PACKAGE_TARNAME "netgen"
| #define PACKAGE_VERSION "1.3"
| #define PACKAGE_STRING "netgen 1.3"
| #define PACKAGE_BUGREPORT "[email protected]"
| #define PACKAGE_URL ""
| #define NETGEN_VERSION "1.5"
| #define NETGEN_REVISION "102"
| #define STDC_HEADERS 1
| #define HAVE_SYS_TYPES_H 1
| #define HAVE_SYS_STAT_H 1
| #define HAVE_STDLIB_H 1
| #define HAVE_STRING_H 1
| #define HAVE_MEMORY_H 1
| #define HAVE_STRINGS_H 1
| #define HAVE_INTTYPES_H 1
| #define HAVE_STDINT_H 1
| #define HAVE_UNISTD_H 1
| #define SIZEOF_VOID_P 8
| #define SIZEOF_UNSIGNED_INT 4
| #define SIZEOF_UNSIGNED_LONG 8
| #define SIZEOF_UNSIGNED_LONG_LONG 8
| #define STDC_HEADERS 1
| #define HAVE_SETENV 1
| #define HAVE_PUTENV 1
| #define HAVE_DIRENT_H 1
| #define HAVE_LIMITS_H 1
| /* end confdefs.h. */
| #include <param.h>
configure:4631: result: no
configure:4631: checking for param.h
configure:4631: result: no
configure:4644: checking for python3
configure:4660: found /bin/python3
configure:4672: result: yes
configure:4681: checking for va_copy
configure:4699: gcc -o conftest -g conftest.c >&5
configure:4699: $? = 0
configure:4708: result: yes
configure:4716: checking for __va_copy
configure:4734: gcc -o conftest -g conftest.c >&5
configure:4734: $? = 0
configure:4743: result: yes
configure:4874: checking for tclConfig.sh
configure:4946: result: /usr/lib64/tclConfig.sh
configure:4962: checking for tkConfig.sh
configure:5035: result: /usr/lib64/tkConfig.sh
configure:5168: checking for wish executable
configure:5195: result: /usr/bin/wish
configure:5201: checking for tclsh executable
configure:5227: result: /usr/bin/tclsh
configure:5350: checking for X
configure:5489: gcc -o conftest -g conftest.c -lX11 >&5
configure:5489: $? = 0
configure:5539: result: libraries , headers
configure:5638: gcc -o conftest -g conftest.c -lX11 >&5
configure:5638: $? = 0
configure:5736: checking for gethostbyname
configure:5736: gcc -o conftest -g conftest.c >&5
configure:5736: $? = 0
configure:5736: result: yes
configure:5833: checking for connect
configure:5833: gcc -o conftest -g conftest.c >&5
configure:5833: $? = 0
configure:5833: result: yes
configure:5882: checking for remove
configure:5882: gcc -o conftest -g conftest.c >&5
configure:5882: $? = 0
configure:5882: result: yes
configure:5931: checking for shmat
configure:5931: gcc -o conftest -g conftest.c >&5
configure:5931: $? = 0
configure:5931: result: yes
configure:5989: checking for IceConnectionNumber in -lICE
configure:6014: gcc -o conftest -g conftest.c -lICE >&5
configure:6014: $? = 0
configure:6023: result: yes
configure:6745: creating ./config.status
## ---------------------- ##
## Running config.status. ##
## ---------------------- ##
This file was extended by netgen config.status 1.3, which was
generated by GNU Autoconf 2.69. Invocation command line was
CONFIG_FILES =
CONFIG_HEADERS =
CONFIG_LINKS =
CONFIG_COMMANDS =
$ ./config.status
on stravinsky
config.status:784: creating defs.mak
config.status:887: WARNING: 'defs.mak.in' seems to ignore the --datarootdir setting
## ---------------- ##
## Cache variables. ##
## ---------------- ##
ac_cv_build=x86_64-unknown-linux-gnu
ac_cv_c___va_copy=yes
ac_cv_c_bigendian=no
ac_cv_c_compiler_gnu=yes
ac_cv_c_va_copy=yes
ac_cv_env_CC_set=
ac_cv_env_CC_value=
ac_cv_env_CFLAGS_set=set
ac_cv_env_CFLAGS_value=-g
ac_cv_env_CPPFLAGS_set=
ac_cv_env_CPPFLAGS_value=
ac_cv_env_CPP_set=
ac_cv_env_CPP_value=
ac_cv_env_LDFLAGS_set=
ac_cv_env_LDFLAGS_value=
ac_cv_env_LIBS_set=
ac_cv_env_LIBS_value=
ac_cv_env_XMKMF_set=
ac_cv_env_XMKMF_value=
ac_cv_env_build_alias_set=
ac_cv_env_build_alias_value=
ac_cv_env_host_alias_set=
ac_cv_env_host_alias_value=
ac_cv_env_target_alias_set=
ac_cv_env_target_alias_value=
ac_cv_func_connect=yes
ac_cv_func_gethostbyname=yes
ac_cv_func_putenv=yes
ac_cv_func_remove=yes
ac_cv_func_setenv=yes
ac_cv_func_shmat=yes
ac_cv_func_vfork=yes
ac_cv_have_x='have_x=yes ac_x_includes='\'''\'' ac_x_libraries='\'''\'''
ac_cv_header_dirent_h=yes
ac_cv_header_inttypes_h=yes
ac_cv_header_limits_h=yes
ac_cv_header_memory_h=yes
ac_cv_header_param_h=no
ac_cv_header_stdc=yes
ac_cv_header_stdint_h=yes
ac_cv_header_stdlib_h=yes
ac_cv_header_string_h=yes
ac_cv_header_strings_h=yes
ac_cv_header_sys_stat_h=yes
ac_cv_header_sys_types_h=yes
ac_cv_header_unistd_h=yes
ac_cv_host=x86_64-unknown-linux-gnu
ac_cv_lib_ICE_IceConnectionNumber=yes
ac_cv_objext=o
ac_cv_path_EGREP='/bin/grep -E'
ac_cv_path_GREP=/bin/grep
ac_cv_path_LD=/bin/ld
ac_cv_path_M4=/bin/m4
ac_cv_path_install='/bin/install -c'
ac_cv_prog_CPP='gcc -E'
ac_cv_prog_HAVE_PYTHON3=yes
ac_cv_prog_ac_ct_CC=gcc
ac_cv_prog_ac_ct_RANLIB=ranlib
ac_cv_prog_cc_c89=
ac_cv_prog_cc_g=yes
ac_cv_prog_gnu_ld=yes
ac_cv_search_strerror='none required'
ac_cv_sizeof_unsigned_int=4
ac_cv_sizeof_unsigned_long=8
ac_cv_sizeof_unsigned_long_long=8
ac_cv_sizeof_void_p=8
ac_cv_target=x86_64-unknown-linux-gnu
## ----------------- ##
## Output variables. ##
## ----------------- ##
ALL_TARGET='tcl'
CC='gcc'
CFLAGS='-g -m64 -fPIC'
CPP='gcc -E -x c'
CPPFLAGS=''
DEFS='-DPACKAGE_NAME=\"netgen\" -DPACKAGE_TARNAME=\"netgen\" -DPACKAGE_VERSION=\"1.3\" -DPACKAGE_STRING=\"netgen\ 1.3\" -DPACKAGE_BUGREPORT=\"[email protected]\" -DPACKAGE_URL=\"\" -DNETGEN_VERSION=\"1.5\" -DNETGEN_REVISION=\"102\" -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DSIZEOF_VOID_P=8 -DSIZEOF_UNSIGNED_INT=4 -DSIZEOF_UNSIGNED_LONG=8 -DSIZEOF_UNSIGNED_LONG_LONG=8 -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DHAVE_DIRENT_H=1 -DHAVE_LIMITS_H=1 -DHAVE_VA_COPY=1 -DHAVE___VA_COPY=1 -DDBUG_OFF=1 -DTCL_NETGEN=1 -Dlinux=1 -DSYSV=1 -DISC=1'
DEPEND_FLAG='-MM'
ECHO_C=''
ECHO_N='printf'
ECHO_T=''
EGREP='/bin/grep -E'
EXEEXT=''
EXTRA_LIB_SPECS='-ldl'
GREP='/bin/grep'
HAVE_PYTHON3='yes'
INC_SPECS=''
INSTALL_DATA='${INSTALL} -m 644'
INSTALL_PROGRAM='${INSTALL}'
INSTALL_SCRIPT='${INSTALL}'
INSTALL_TARGET='install-tcl'
LD='/bin/ld'
LDDL_FLAGS=' -shared -Wl,-soname,$@ -Wl,--version-script=${NETGENDIR}/netgen/symbol.map'
LDFLAGS=''
LD_RUN_PATH=''
LIBOBJS=''
LIBS=''
LIB_SPECS=' -L/usr/lib64 -ltkstub8.6 -L/usr/lib64 -ltclstub8.6'
LIB_SPECS_NOSTUB=' -L/usr/lib64 -ltk8.6 -L/usr/lib64 -ltcl8.6'
LTLIBOBJS=''
M4='/bin/m4'
OBJEXT='o'
PACKAGE='netgen'
PACKAGE_BUGREPORT='[email protected]'
PACKAGE_NAME='netgen'
PACKAGE_STRING='netgen 1.3'
PACKAGE_TARNAME='netgen'
PACKAGE_URL=''
PACKAGE_VERSION='1.3'
PATH_SEPARATOR=':'
RANLIB='ranlib'
SCRIPTS=''
SHDLIB_EXT='.so'
SHELL='/bin/sh'
SHLIB_CFLAGS='-fPIC'
SHLIB_LD=''
SHLIB_LIB_SPECS=''
TCLSH_EXE='/usr/bin/tclsh'
TCL_LIB_DIR='/usr/lib'
VERSION=''
WISH_EXE='/usr/bin/wish'
XMKMF=''
X_CFLAGS=''
X_EXTRA_LIBS=''
X_LIBS=''
X_PRE_LIBS=' -lSM -lICE'
ac_ct_CC='gcc'
bindir='${exec_prefix}/bin'
build='x86_64-unknown-linux-gnu'
build_alias=''
build_cpu='x86_64'
build_os='linux-gnu'
build_vendor='unknown'
cadinstall=' tcltk'
datadir='${datarootdir}'
datarootdir='${prefix}/share'
docdir='${datarootdir}/doc/${PACKAGE_TARNAME}'
dvidir='${docdir}'
exec_prefix='${prefix}'
extra_defs=' -DCAD_DIR=\"${LIBDIR}\" -DTCL_DIR=\"${TCLDIR}\"'
extra_libs=' ${NETGENDIR}/tcltk/libtcltk.o'
gr_cflags=''
gr_dflags=' -DX11 -DXLIB'
gr_libs=' -lX11'
gr_srcs=' ${TK_SRCS}'
host='x86_64-unknown-linux-gnu'
host_alias=''
host_cpu='x86_64'
host_os='linux-gnu'
host_vendor='unknown'
htmldir='${docdir}'
includedir='${prefix}/include'
infodir='${datarootdir}/info'
ld_extra_libs=''
ld_extra_objs=''
libdir='${exec_prefix}/lib'
libexecdir='${exec_prefix}/libexec'
localedir='${datarootdir}/locale'
localstatedir='${prefix}/var'
mandir='${datarootdir}/man'
modules=' tcltk'
oldincludedir='/usr/include'
pdfdir='${docdir}'
prefix='/usr/local'
program_transform_name='s,x,x,'
programs=' tcltk'
psdir='${docdir}'
sbindir='${exec_prefix}/sbin'
sharedstatedir='${prefix}/com'
stub_defs=' -DUSE_TCL_STUBS -DUSE_TK_STUBS'
sub_extra_libs=''
sysconfdir='${prefix}/etc'
target='x86_64-unknown-linux-gnu'
target_alias=''
target_cpu='x86_64'
target_os='linux-gnu'
target_vendor='unknown'
top_extra_libs=''
unused=''
## ----------- ##
## confdefs.h. ##
## ----------- ##
/* confdefs.h */
#define PACKAGE_NAME "netgen"
#define PACKAGE_TARNAME "netgen"
#define PACKAGE_VERSION "1.3"
#define PACKAGE_STRING "netgen 1.3"
#define PACKAGE_BUGREPORT "[email protected]"
#define PACKAGE_URL ""
#define NETGEN_VERSION "1.5"
#define NETGEN_REVISION "102"
#define STDC_HEADERS 1
#define HAVE_SYS_TYPES_H 1
#define HAVE_SYS_STAT_H 1
#define HAVE_STDLIB_H 1
#define HAVE_STRING_H 1
#define HAVE_MEMORY_H 1
#define HAVE_STRINGS_H 1
#define HAVE_INTTYPES_H 1
#define HAVE_STDINT_H 1
#define HAVE_UNISTD_H 1
#define SIZEOF_VOID_P 8
#define SIZEOF_UNSIGNED_INT 4
#define SIZEOF_UNSIGNED_LONG 8
#define SIZEOF_UNSIGNED_LONG_LONG 8
#define STDC_HEADERS 1
#define HAVE_SETENV 1
#define HAVE_PUTENV 1
#define HAVE_DIRENT_H 1
#define HAVE_LIMITS_H 1
#define HAVE_VA_COPY 1
#define HAVE___VA_COPY 1
#define DBUG_OFF 1
#define TCL_NETGEN 1
#define linux 1
#define SYSV 1
#define ISC 1
configure: exit 0
-941
View File
@@ -1,941 +0,0 @@
#! /bin/sh
# Generated by configure.
# Run this file to recreate the current configuration.
# Compiler output produced by configure, useful for debugging
# configure, is in config.log if it exists.
debug=false
ac_cs_recheck=false
ac_cs_silent=false
SHELL=${CONFIG_SHELL-/bin/sh}
export SHELL
## -------------------- ##
## M4sh Initialization. ##
## -------------------- ##
# Be more Bourne compatible
DUALCASE=1; export DUALCASE # for MKS sh
if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then :
emulate sh
NULLCMD=:
# Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
# is contrary to our usage. Disable this feature.
alias -g '${1+"$@"}'='"$@"'
setopt NO_GLOB_SUBST
else
case `(set -o) 2>/dev/null` in #(
*posix*) :
set -o posix ;; #(
*) :
;;
esac
fi
as_nl='
'
export as_nl
# Printing a long string crashes Solaris 7 /usr/bin/printf.
as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
# Prefer a ksh shell builtin over an external printf program on Solaris,
# but without wasting forks for bash or zsh.
if test -z "$BASH_VERSION$ZSH_VERSION" \
&& (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then
as_echo='print -r --'
as_echo_n='print -rn --'
elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
as_echo='printf %s\n'
as_echo_n='printf %s'
else
if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
as_echo_n='/usr/ucb/echo -n'
else
as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
as_echo_n_body='eval
arg=$1;
case $arg in #(
*"$as_nl"*)
expr "X$arg" : "X\\(.*\\)$as_nl";
arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
esac;
expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
'
export as_echo_n_body
as_echo_n='sh -c $as_echo_n_body as_echo'
fi
export as_echo_body
as_echo='sh -c $as_echo_body as_echo'
fi
# The user is always right.
if test "${PATH_SEPARATOR+set}" != set; then
PATH_SEPARATOR=:
(PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
(PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
PATH_SEPARATOR=';'
}
fi
# IFS
# We need space, tab and new line, in precisely that order. Quoting is
# there to prevent editors from complaining about space-tab.
# (If _AS_PATH_WALK were called with IFS unset, it would disable word
# splitting by setting IFS to empty value.)
IFS=" "" $as_nl"
# Find who we are. Look in the path if we contain no directory separator.
as_myself=
case $0 in #((
*[\\/]* ) as_myself=$0 ;;
*) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
for as_dir in $PATH
do
IFS=$as_save_IFS
test -z "$as_dir" && as_dir=.
test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
done
IFS=$as_save_IFS
;;
esac
# We did not find ourselves, most probably we were run as `sh COMMAND'
# in which case we are not to be found in the path.
if test "x$as_myself" = x; then
as_myself=$0
fi
if test ! -f "$as_myself"; then
$as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
exit 1
fi
# Unset variables that we do not need and which cause bugs (e.g. in
# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1"
# suppresses any "Segmentation fault" message there. '((' could
# trigger a bug in pdksh 5.2.14.
for as_var in BASH_ENV ENV MAIL MAILPATH
do eval test x\${$as_var+set} = xset \
&& ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || :
done
PS1='$ '
PS2='> '
PS4='+ '
# NLS nuisances.
LC_ALL=C
export LC_ALL
LANGUAGE=C
export LANGUAGE
# CDPATH.
(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
# as_fn_error STATUS ERROR [LINENO LOG_FD]
# ----------------------------------------
# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
# provided, also output the error to LOG_FD, referencing LINENO. Then exit the
# script with STATUS, using 1 if that was 0.
as_fn_error ()
{
as_status=$1; test $as_status -eq 0 && as_status=1
if test "$4"; then
as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
$as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4
fi
$as_echo "$as_me: error: $2" >&2
as_fn_exit $as_status
} # as_fn_error
# as_fn_set_status STATUS
# -----------------------
# Set $? to STATUS, without forking.
as_fn_set_status ()
{
return $1
} # as_fn_set_status
# as_fn_exit STATUS
# -----------------
# Exit the shell with STATUS, even in a "trap 0" or "set -e" context.
as_fn_exit ()
{
set +e
as_fn_set_status $1
exit $1
} # as_fn_exit
# as_fn_unset VAR
# ---------------
# Portably unset VAR.
as_fn_unset ()
{
{ eval $1=; unset $1;}
}
as_unset=as_fn_unset
# as_fn_append VAR VALUE
# ----------------------
# Append the text in VALUE to the end of the definition contained in VAR. Take
# advantage of any shell optimizations that allow amortized linear growth over
# repeated appends, instead of the typical quadratic growth present in naive
# implementations.
if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then :
eval 'as_fn_append ()
{
eval $1+=\$2
}'
else
as_fn_append ()
{
eval $1=\$$1\$2
}
fi # as_fn_append
# as_fn_arith ARG...
# ------------------
# Perform arithmetic evaluation on the ARGs, and store the result in the
# global $as_val. Take advantage of shells that can avoid forks. The arguments
# must be portable across $(()) and expr.
if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then :
eval 'as_fn_arith ()
{
as_val=$(( $* ))
}'
else
as_fn_arith ()
{
as_val=`expr "$@" || test $? -eq 1`
}
fi # as_fn_arith
if expr a : '\(a\)' >/dev/null 2>&1 &&
test "X`expr 00001 : '.*\(...\)'`" = X001; then
as_expr=expr
else
as_expr=false
fi
if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
as_basename=basename
else
as_basename=false
fi
if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
as_dirname=dirname
else
as_dirname=false
fi
as_me=`$as_basename -- "$0" ||
$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
X"$0" : 'X\(//\)$' \| \
X"$0" : 'X\(/\)' \| . 2>/dev/null ||
$as_echo X/"$0" |
sed '/^.*\/\([^/][^/]*\)\/*$/{
s//\1/
q
}
/^X\/\(\/\/\)$/{
s//\1/
q
}
/^X\/\(\/\).*/{
s//\1/
q
}
s/.*/./; q'`
# Avoid depending upon Character Ranges.
as_cr_letters='abcdefghijklmnopqrstuvwxyz'
as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
as_cr_Letters=$as_cr_letters$as_cr_LETTERS
as_cr_digits='0123456789'
as_cr_alnum=$as_cr_Letters$as_cr_digits
ECHO_C= ECHO_N= ECHO_T=
case `echo -n x` in #(((((
-n*)
case `echo 'xy\c'` in
*c*) ECHO_T=' ';; # ECHO_T is single tab character.
xy) ECHO_C='\c';;
*) echo `echo ksh88 bug on AIX 6.1` > /dev/null
ECHO_T=' ';;
esac;;
*)
ECHO_N='-n';;
esac
rm -f conf$$ conf$$.exe conf$$.file
if test -d conf$$.dir; then
rm -f conf$$.dir/conf$$.file
else
rm -f conf$$.dir
mkdir conf$$.dir 2>/dev/null
fi
if (echo >conf$$.file) 2>/dev/null; then
if ln -s conf$$.file conf$$ 2>/dev/null; then
as_ln_s='ln -s'
# ... but there are two gotchas:
# 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
# 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
# In both cases, we have to default to `cp -pR'.
ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
as_ln_s='cp -pR'
elif ln conf$$.file conf$$ 2>/dev/null; then
as_ln_s=ln
else
as_ln_s='cp -pR'
fi
else
as_ln_s='cp -pR'
fi
rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
rmdir conf$$.dir 2>/dev/null
# as_fn_mkdir_p
# -------------
# Create "$as_dir" as a directory, including parents if necessary.
as_fn_mkdir_p ()
{
case $as_dir in #(
-*) as_dir=./$as_dir;;
esac
test -d "$as_dir" || eval $as_mkdir_p || {
as_dirs=
while :; do
case $as_dir in #(
*\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'(
*) as_qdir=$as_dir;;
esac
as_dirs="'$as_qdir' $as_dirs"
as_dir=`$as_dirname -- "$as_dir" ||
$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
X"$as_dir" : 'X\(//\)[^/]' \| \
X"$as_dir" : 'X\(//\)$' \| \
X"$as_dir" : 'X\(/\)' \| . 2>/dev/null ||
$as_echo X"$as_dir" |
sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
s//\1/
q
}
/^X\(\/\/\)[^/].*/{
s//\1/
q
}
/^X\(\/\/\)$/{
s//\1/
q
}
/^X\(\/\).*/{
s//\1/
q
}
s/.*/./; q'`
test -d "$as_dir" && break
done
test -z "$as_dirs" || eval "mkdir $as_dirs"
} || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir"
} # as_fn_mkdir_p
if mkdir -p . 2>/dev/null; then
as_mkdir_p='mkdir -p "$as_dir"'
else
test -d ./-p && rmdir ./-p
as_mkdir_p=false
fi
# as_fn_executable_p FILE
# -----------------------
# Test if FILE is an executable regular file.
as_fn_executable_p ()
{
test -f "$1" && test -x "$1"
} # as_fn_executable_p
as_test_x='test -x'
as_executable_p=as_fn_executable_p
# Sed expression to map a string onto a valid CPP name.
as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
# Sed expression to map a string onto a valid variable name.
as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
exec 6>&1
## ----------------------------------- ##
## Main body of $CONFIG_STATUS script. ##
## ----------------------------------- ##
# Save the log message, to keep $0 and so on meaningful, and to
# report actual input values of CONFIG_FILES etc. instead of their
# values after options handling.
ac_log="
This file was extended by netgen $as_me 1.3, which was
generated by GNU Autoconf 2.69. Invocation command line was
CONFIG_FILES = $CONFIG_FILES
CONFIG_HEADERS = $CONFIG_HEADERS
CONFIG_LINKS = $CONFIG_LINKS
CONFIG_COMMANDS = $CONFIG_COMMANDS
$ $0 $@
on `(hostname || uname -n) 2>/dev/null | sed 1q`
"
# Files that config.status was made for.
config_files=" defs.mak"
ac_cs_usage="\
\`$as_me' instantiates files and other configuration actions
from templates according to the current configuration. Unless the files
and actions are specified as TAGs, all are instantiated by default.
Usage: $0 [OPTION]... [TAG]...
-h, --help print this help, then exit
-V, --version print version number and configuration settings, then exit
--config print configuration, then exit
-q, --quiet, --silent
do not print progress messages
-d, --debug don't remove temporary files
--recheck update $as_me by reconfiguring in the same conditions
--file=FILE[:TEMPLATE]
instantiate the configuration file FILE
Configuration files:
$config_files
Report bugs to <[email protected]>."
ac_cs_config="'CFLAGS=-g'"
ac_cs_version="\
netgen config.status 1.3
configured by ./configure, generated by GNU Autoconf 2.69,
with options \"$ac_cs_config\"
Copyright (C) 2012 Free Software Foundation, Inc.
This config.status script is free software; the Free Software Foundation
gives unlimited permission to copy, distribute and modify it."
ac_pwd='/home/tim/gitsrc/netgen-1.5/scripts'
srcdir='..'
INSTALL='/bin/install -c'
test -n "$AWK" || AWK=awk
# The default lists apply if the user does not specify any file.
ac_need_defaults=:
while test $# != 0
do
case $1 in
--*=?*)
ac_option=`expr "X$1" : 'X\([^=]*\)='`
ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'`
ac_shift=:
;;
--*=)
ac_option=`expr "X$1" : 'X\([^=]*\)='`
ac_optarg=
ac_shift=:
;;
*)
ac_option=$1
ac_optarg=$2
ac_shift=shift
;;
esac
case $ac_option in
# Handling of the options.
-recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
ac_cs_recheck=: ;;
--version | --versio | --versi | --vers | --ver | --ve | --v | -V )
$as_echo "$ac_cs_version"; exit ;;
--config | --confi | --conf | --con | --co | --c )
$as_echo "$ac_cs_config"; exit ;;
--debug | --debu | --deb | --de | --d | -d )
debug=: ;;
--file | --fil | --fi | --f )
$ac_shift
case $ac_optarg in
*\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;
'') as_fn_error $? "missing file argument" ;;
esac
as_fn_append CONFIG_FILES " '$ac_optarg'"
ac_need_defaults=false;;
--he | --h | --help | --hel | -h )
$as_echo "$ac_cs_usage"; exit ;;
-q | -quiet | --quiet | --quie | --qui | --qu | --q \
| -silent | --silent | --silen | --sile | --sil | --si | --s)
ac_cs_silent=: ;;
# This is an error.
-*) as_fn_error $? "unrecognized option: \`$1'
Try \`$0 --help' for more information." ;;
*) as_fn_append ac_config_targets " $1"
ac_need_defaults=false ;;
esac
shift
done
ac_configure_extra_args=
if $ac_cs_silent; then
exec 6>/dev/null
ac_configure_extra_args="$ac_configure_extra_args --silent"
fi
if $ac_cs_recheck; then
set X /bin/sh './configure' 'CFLAGS=-g' $ac_configure_extra_args --no-create --no-recursion
shift
$as_echo "running CONFIG_SHELL=/bin/sh $*" >&6
CONFIG_SHELL='/bin/sh'
export CONFIG_SHELL
exec "$@"
fi
exec 5>>config.log
{
echo
sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX
## Running $as_me. ##
_ASBOX
$as_echo "$ac_log"
} >&5
# Handling of arguments.
for ac_config_target in $ac_config_targets
do
case $ac_config_target in
"defs.mak") CONFIG_FILES="$CONFIG_FILES defs.mak" ;;
*) as_fn_error $? "invalid argument: \`$ac_config_target'" "$LINENO" 5;;
esac
done
# If the user did not use the arguments to specify the items to instantiate,
# then the envvar interface is used. Set only those that are not.
# We use the long form for the default assignment because of an extremely
# bizarre bug on SunOS 4.1.3.
if $ac_need_defaults; then
test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files
fi
# Have a temporary directory for convenience. Make it in the build tree
# simply because there is no reason against having it here, and in addition,
# creating and moving files from /tmp can sometimes cause problems.
# Hook for its removal unless debugging.
# Note that there is a small window in which the directory will not be cleaned:
# after its creation but before its name has been assigned to `$tmp'.
$debug ||
{
tmp= ac_tmp=
trap 'exit_status=$?
: "${ac_tmp:=$tmp}"
{ test ! -d "$ac_tmp" || rm -fr "$ac_tmp"; } && exit $exit_status
' 0
trap 'as_fn_exit 1' 1 2 13 15
}
# Create a (secure) tmp directory for tmp files.
{
tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` &&
test -d "$tmp"
} ||
{
tmp=./conf$$-$RANDOM
(umask 077 && mkdir "$tmp")
} || as_fn_error $? "cannot create a temporary directory in ." "$LINENO" 5
ac_tmp=$tmp
# Set up the scripts for CONFIG_FILES section.
# No need to generate them if there are no CONFIG_FILES.
# This happens for instance with `./config.status config.h'.
if test -n "$CONFIG_FILES"; then
ac_cr=`echo X | tr X '\015'`
# On cygwin, bash can eat \r inside `` if the user requested igncr.
# But we know of no other shell where ac_cr would be empty at this
# point, so we can use a bashism as a fallback.
if test "x$ac_cr" = x; then
eval ac_cr=\$\'\\r\'
fi
ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' </dev/null 2>/dev/null`
if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then
ac_cs_awk_cr='\\r'
else
ac_cs_awk_cr=$ac_cr
fi
echo 'BEGIN {' >"$ac_tmp/subs1.awk" &&
cat >>"$ac_tmp/subs1.awk" <<\_ACAWK &&
S["LTLIBOBJS"]=""
S["LIBOBJS"]=""
S["INSTALL_TARGET"]="install-tcl"
S["ALL_TARGET"]="tcl"
S["LD_RUN_PATH"]=""
S["SHLIB_CFLAGS"]="-fPIC"
S["DEPEND_FLAG"]="-MM"
S["gr_srcs"]=" ${TK_SRCS}"
S["gr_libs"]=" -lX11"
S["gr_dflags"]=" -DX11 -DXLIB"
S["gr_cflags"]=""
S["cadinstall"]=" tcltk"
S["programs"]=" tcltk"
S["unused"]=""
S["modules"]=" tcltk"
S["sub_extra_libs"]=""
S["top_extra_libs"]=""
S["ld_extra_objs"]=""
S["ld_extra_libs"]=""
S["stub_defs"]=" -DUSE_TCL_STUBS -DUSE_TK_STUBS"
S["extra_defs"]=" -DCAD_DIR=\\\"${LIBDIR}\\\" -DTCL_DIR=\\\"${TCLDIR}\\\""
S["extra_libs"]=" ${NETGENDIR}/tcltk/libtcltk.o"
S["SCRIPTS"]=""
S["PACKAGE"]="netgen"
S["VERSION"]=""
S["TCL_LIB_DIR"]="/usr/lib"
S["TCLSH_EXE"]="/usr/bin/tclsh"
S["WISH_EXE"]="/usr/bin/wish"
S["LIB_SPECS_NOSTUB"]=" -L/usr/lib64 -ltk8.6 -L/usr/lib64 -ltcl8.6"
S["LIB_SPECS"]=" -L/usr/lib64 -ltkstub8.6 -L/usr/lib64 -ltclstub8.6"
S["INC_SPECS"]=""
S["EXTRA_LIB_SPECS"]="-ldl"
S["SHLIB_LIB_SPECS"]=""
S["LDDL_FLAGS"]=" -shared -Wl,-soname,$@ -Wl,--version-script=${NETGENDIR}/netgen/symbol.map"
S["LD"]="/bin/ld"
S["SHLIB_LD"]=""
S["SHDLIB_EXT"]=".so"
S["X_EXTRA_LIBS"]=""
S["X_LIBS"]=""
S["X_PRE_LIBS"]=" -lSM -lICE"
S["X_CFLAGS"]=""
S["XMKMF"]=""
S["HAVE_PYTHON3"]="yes"
S["EGREP"]="/bin/grep -E"
S["GREP"]="/bin/grep"
S["M4"]="/bin/m4"
S["RANLIB"]="ranlib"
S["INSTALL_DATA"]="${INSTALL} -m 644"
S["INSTALL_SCRIPT"]="${INSTALL}"
S["INSTALL_PROGRAM"]="${INSTALL}"
S["CPP"]="gcc -E -x c"
S["OBJEXT"]="o"
S["EXEEXT"]=""
S["ac_ct_CC"]="gcc"
S["CPPFLAGS"]=""
S["LDFLAGS"]=""
S["CFLAGS"]="-g -m64 -fPIC"
S["CC"]="gcc"
S["target_os"]="linux-gnu"
S["target_vendor"]="unknown"
S["target_cpu"]="x86_64"
S["target"]="x86_64-unknown-linux-gnu"
S["host_os"]="linux-gnu"
S["host_vendor"]="unknown"
S["host_cpu"]="x86_64"
S["host"]="x86_64-unknown-linux-gnu"
S["build_os"]="linux-gnu"
S["build_vendor"]="unknown"
S["build_cpu"]="x86_64"
S["build"]="x86_64-unknown-linux-gnu"
S["target_alias"]=""
S["host_alias"]=""
S["build_alias"]=""
S["LIBS"]=""
S["ECHO_T"]=""
S["ECHO_N"]="-n"
S["ECHO_C"]=""
S["DEFS"]="-DPACKAGE_NAME=\\\"netgen\\\" -DPACKAGE_TARNAME=\\\"netgen\\\" -DPACKAGE_VERSION=\\\"1.3\\\" -DPACKAGE_STRING=\\\"netgen\\ 1.3\\\" -DPACKAGE_BUGREPORT=\\\"eda-dev@open"\
"circuitdesign.com\\\" -DPACKAGE_URL=\\\"\\\" -DNETGEN_VERSION=\\\"1.5\\\" -DNETGEN_REVISION=\\\"102\\\" -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 "\
"-DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DSIZEOF_VOID_P=8 -"\
"DSIZEOF_UNSIGNED_INT=4 -DSIZEOF_UNSIGNED_LONG=8 -DSIZEOF_UNSIGNED_LONG_LONG=8 -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DHAVE_DIRENT_H=1 -DH"\
"AVE_LIMITS_H=1 -DHAVE_VA_COPY=1 -DHAVE___VA_COPY=1 -DDBUG_OFF=1 -DTCL_NETGEN=1 -Dlinux=1 -DSYSV=1 -DISC=1"
S["mandir"]="${datarootdir}/man"
S["localedir"]="${datarootdir}/locale"
S["libdir"]="${exec_prefix}/lib"
S["psdir"]="${docdir}"
S["pdfdir"]="${docdir}"
S["dvidir"]="${docdir}"
S["htmldir"]="${docdir}"
S["infodir"]="${datarootdir}/info"
S["docdir"]="${datarootdir}/doc/${PACKAGE_TARNAME}"
S["oldincludedir"]="/usr/include"
S["includedir"]="${prefix}/include"
S["localstatedir"]="${prefix}/var"
S["sharedstatedir"]="${prefix}/com"
S["sysconfdir"]="${prefix}/etc"
S["datadir"]="${datarootdir}"
S["datarootdir"]="${prefix}/share"
S["libexecdir"]="${exec_prefix}/libexec"
S["sbindir"]="${exec_prefix}/sbin"
S["bindir"]="${exec_prefix}/bin"
S["program_transform_name"]="s,x,x,"
S["prefix"]="/usr/local"
S["exec_prefix"]="${prefix}"
S["PACKAGE_URL"]=""
S["PACKAGE_BUGREPORT"]="[email protected]"
S["PACKAGE_STRING"]="netgen 1.3"
S["PACKAGE_VERSION"]="1.3"
S["PACKAGE_TARNAME"]="netgen"
S["PACKAGE_NAME"]="netgen"
S["PATH_SEPARATOR"]=":"
S["SHELL"]="/bin/sh"
_ACAWK
cat >>"$ac_tmp/subs1.awk" <<_ACAWK &&
for (key in S) S_is_set[key] = 1
FS = ""
}
{
line = $ 0
nfields = split(line, field, "@")
substed = 0
len = length(field[1])
for (i = 2; i < nfields; i++) {
key = field[i]
keylen = length(key)
if (S_is_set[key]) {
value = S[key]
line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3)
len += length(value) + length(field[++i])
substed = 1
} else
len += 1 + keylen
}
print line
}
_ACAWK
if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then
sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g"
else
cat
fi < "$ac_tmp/subs1.awk" > "$ac_tmp/subs.awk" \
|| as_fn_error $? "could not setup config files machinery" "$LINENO" 5
fi # test -n "$CONFIG_FILES"
eval set X " :F $CONFIG_FILES "
shift
for ac_tag
do
case $ac_tag in
:[FHLC]) ac_mode=$ac_tag; continue;;
esac
case $ac_mode$ac_tag in
:[FHL]*:*);;
:L* | :C*:*) as_fn_error $? "invalid tag \`$ac_tag'" "$LINENO" 5;;
:[FH]-) ac_tag=-:-;;
:[FH]*) ac_tag=$ac_tag:$ac_tag.in;;
esac
ac_save_IFS=$IFS
IFS=:
set x $ac_tag
IFS=$ac_save_IFS
shift
ac_file=$1
shift
case $ac_mode in
:L) ac_source=$1;;
:[FH])
ac_file_inputs=
for ac_f
do
case $ac_f in
-) ac_f="$ac_tmp/stdin";;
*) # Look for the file first in the build tree, then in the source tree
# (if the path is not absolute). The absolute path cannot be DOS-style,
# because $ac_f cannot contain `:'.
test -f "$ac_f" ||
case $ac_f in
[\\/$]*) false;;
*) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";;
esac ||
as_fn_error 1 "cannot find input file: \`$ac_f'" "$LINENO" 5;;
esac
case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac
as_fn_append ac_file_inputs " '$ac_f'"
done
# Let's still pretend it is `configure' which instantiates (i.e., don't
# use $as_me), people would be surprised to read:
# /* config.h. Generated by config.status. */
configure_input='Generated from '`
$as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g'
`' by configure.'
if test x"$ac_file" != x-; then
configure_input="$ac_file. $configure_input"
{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5
$as_echo "$as_me: creating $ac_file" >&6;}
fi
# Neutralize special characters interpreted by sed in replacement strings.
case $configure_input in #(
*\&* | *\|* | *\\* )
ac_sed_conf_input=`$as_echo "$configure_input" |
sed 's/[\\\\&|]/\\\\&/g'`;; #(
*) ac_sed_conf_input=$configure_input;;
esac
case $ac_tag in
*:-:* | *:-) cat >"$ac_tmp/stdin" \
|| as_fn_error $? "could not create $ac_file" "$LINENO" 5 ;;
esac
;;
esac
ac_dir=`$as_dirname -- "$ac_file" ||
$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
X"$ac_file" : 'X\(//\)[^/]' \| \
X"$ac_file" : 'X\(//\)$' \| \
X"$ac_file" : 'X\(/\)' \| . 2>/dev/null ||
$as_echo X"$ac_file" |
sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
s//\1/
q
}
/^X\(\/\/\)[^/].*/{
s//\1/
q
}
/^X\(\/\/\)$/{
s//\1/
q
}
/^X\(\/\).*/{
s//\1/
q
}
s/.*/./; q'`
as_dir="$ac_dir"; as_fn_mkdir_p
ac_builddir=.
case "$ac_dir" in
.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;;
*)
ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'`
# A ".." for each directory in $ac_dir_suffix.
ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'`
case $ac_top_builddir_sub in
"") ac_top_builddir_sub=. ac_top_build_prefix= ;;
*) ac_top_build_prefix=$ac_top_builddir_sub/ ;;
esac ;;
esac
ac_abs_top_builddir=$ac_pwd
ac_abs_builddir=$ac_pwd$ac_dir_suffix
# for backward compatibility:
ac_top_builddir=$ac_top_build_prefix
case $srcdir in
.) # We are building in place.
ac_srcdir=.
ac_top_srcdir=$ac_top_builddir_sub
ac_abs_top_srcdir=$ac_pwd ;;
[\\/]* | ?:[\\/]* ) # Absolute name.
ac_srcdir=$srcdir$ac_dir_suffix;
ac_top_srcdir=$srcdir
ac_abs_top_srcdir=$srcdir ;;
*) # Relative name.
ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix
ac_top_srcdir=$ac_top_build_prefix$srcdir
ac_abs_top_srcdir=$ac_pwd/$srcdir ;;
esac
ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix
case $ac_mode in
:F)
#
# CONFIG_FILE
#
case $INSTALL in
[\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;;
*) ac_INSTALL=$ac_top_build_prefix$INSTALL ;;
esac
# If the template does not know about datarootdir, expand it.
# FIXME: This hack should be removed a few years after 2.60.
ac_datarootdir_hack=; ac_datarootdir_seen=
ac_sed_dataroot='
/datarootdir/ {
p
q
}
/@datadir@/p
/@docdir@/p
/@infodir@/p
/@localedir@/p
/@mandir@/p'
case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in
*datarootdir*) ac_datarootdir_seen=yes;;
*@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*)
{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5
$as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;}
ac_datarootdir_hack='
s&@datadir@&${datarootdir}&g
s&@docdir@&${datarootdir}/doc/${PACKAGE_TARNAME}&g
s&@infodir@&${datarootdir}/info&g
s&@localedir@&${datarootdir}/locale&g
s&@mandir@&${datarootdir}/man&g
s&\${datarootdir}&${prefix}/share&g' ;;
esac
ac_sed_extra="
:t
/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
s|@configure_input@|$ac_sed_conf_input|;t t
s&@top_builddir@&$ac_top_builddir_sub&;t t
s&@top_build_prefix@&$ac_top_build_prefix&;t t
s&@srcdir@&$ac_srcdir&;t t
s&@abs_srcdir@&$ac_abs_srcdir&;t t
s&@top_srcdir@&$ac_top_srcdir&;t t
s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t
s&@builddir@&$ac_builddir&;t t
s&@abs_builddir@&$ac_abs_builddir&;t t
s&@abs_top_builddir@&$ac_abs_top_builddir&;t t
s&@INSTALL@&$ac_INSTALL&;t t
$ac_datarootdir_hack
"
eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$ac_tmp/subs.awk" \
>$ac_tmp/out || as_fn_error $? "could not create $ac_file" "$LINENO" 5
test -z "$ac_datarootdir_hack$ac_datarootdir_seen" &&
{ ac_out=`sed -n '/\${datarootdir}/p' "$ac_tmp/out"`; test -n "$ac_out"; } &&
{ ac_out=`sed -n '/^[ ]*datarootdir[ ]*:*=/p' \
"$ac_tmp/out"`; test -z "$ac_out"; } &&
{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir'
which seems to be undefined. Please make sure it is defined" >&5
$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir'
which seems to be undefined. Please make sure it is defined" >&2;}
rm -f "$ac_tmp/stdin"
case $ac_file in
-) cat "$ac_tmp/out" && rm -f "$ac_tmp/out";;
*) rm -f "$ac_file" && mv "$ac_tmp/out" "$ac_file";;
esac \
|| as_fn_error $? "could not create $ac_file" "$LINENO" 5
;;
esac
done # for ac_tag
as_fn_exit 0
+26 -4
View File
@@ -633,6 +633,7 @@ gr_srcs
gr_libs
gr_dflags
gr_cflags
DIST_DIR
cadinstall
programs
unused
@@ -734,6 +735,7 @@ ac_subst_files=''
ac_user_opts='
enable_option_checking
with_gnu_ld
with_distdir
with_interpreter
with_tcl
with_tk
@@ -1372,6 +1374,7 @@ Optional Packages:
--with-PACKAGE[=ARG] use PACKAGE [ARG=yes]
--without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no)
--with-gnu-ld assume the C compiler uses GNU ld [default=no]
--with-distdir=DIR install into location DIR for distribution
--with-interpreter=arg enable interpreter
--with-tcl=DIR Find tclConfig.sh in DIR
--with-tk=DIR Find tkConfig.sh in DIR
@@ -4798,6 +4801,24 @@ usingTcl=1
usingX11=
# For distributed installs, where the run-time files are installed in a
# place that is a temporary staging area, like DESTDIR, but unlike DESTDIR,
# the prefix is replaced by the destination directory, rather than appended
# to it.
DIST_DIR="\${exec_prefix}"
# Check whether --with-distdir was given.
if test "${with_distdir+set}" = set; then :
withval=$with_distdir;
if test "$withval" = "no" -o "$withval" = "NO" ; then
DIST_DIR="\${exec_prefix}"
else
DIST_DIR=${withval}
fi
fi
# Check whether --with-interpreter was given.
if test "${with_interpreter+set}" = set; then :
@@ -6413,7 +6434,7 @@ fi
# Not available on all versions: check for include file.
SHLIB_CFLAGS="-fpic"
LDDL_FLAGS="-shared ${LIB_SPECS}"
CFLAGS="${CFLAGS} -l/usr/X11R6/include"
CFLAGS="${CFLAGS} -L/usr/X11R6/include"
;;
*-netbsd*|*-openbsd*)
@@ -6587,6 +6608,7 @@ fi
ac_config_files="$ac_config_files defs.mak"
@@ -7779,7 +7801,9 @@ else
fi
${ECHO_N} "Python3: "
if test "x${HAVE_PYTHON3}" == "x"; then
if test "${HAVE_PYTHON3}" == "yes"; then
echo "yes"
else
echo "no"
echo
echo " Without Python3, you cannot run the GUI interface to netgen."
@@ -7788,8 +7812,6 @@ if test "x${HAVE_PYTHON3}" == "x"; then
echo " python3 support, make sure that you have installed python3"
echo " on your system."
echo
else
echo "yes"
fi
echo "-----------------------------------------------------------"
+19 -4
View File
@@ -249,6 +249,20 @@ usingX11=
dnl Compile-time options below. . .
# For distributed installs, where the run-time files are installed in a
# place that is a temporary staging area, like DESTDIR, but unlike DESTDIR,
# the prefix is replaced by the destination directory, rather than appended
# to it.
DIST_DIR="\${exec_prefix}"
AC_ARG_WITH(distdir,
[ --with-distdir=DIR install into location DIR for distribution], [
if test "$withval" = "no" -o "$withval" = "NO" ; then
DIST_DIR="\${exec_prefix}"
else
DIST_DIR=${withval}
fi
], )
AC_ARG_WITH(interpreter,
[ --with-interpreter=[arg] enable interpreter], [
if test "$withval" = "no" -o "$withval" = "NO"; then
@@ -1120,7 +1134,7 @@ if test $usingTcl ; then
# Not available on all versions: check for include file.
SHLIB_CFLAGS="-fpic"
LDDL_FLAGS="-shared ${LIB_SPECS}"
CFLAGS="${CFLAGS} -l/usr/X11R6/include"
CFLAGS="${CFLAGS} -L/usr/X11R6/include"
;;
*-netbsd*|*-openbsd*)
@@ -1272,6 +1286,7 @@ AC_SUBST(modules)
AC_SUBST(unused)
AC_SUBST(programs)
AC_SUBST(cadinstall)
AC_SUBST(DIST_DIR)
AC_SUBST(gr_cflags)
AC_SUBST(gr_dflags)
@@ -1319,7 +1334,9 @@ else
fi
${ECHO_N} "Python3: "
if test "x${HAVE_PYTHON3}" == "x"; then
if test "${HAVE_PYTHON3}" == "yes"; then
echo "yes"
else
echo "no"
echo
echo " Without Python3, you cannot run the GUI interface to netgen."
@@ -1328,8 +1345,6 @@ if test "x${HAVE_PYTHON3}" == "x"; then
echo " python3 support, make sure that you have installed python3"
echo " on your system."
echo
else
echo "yes"
fi
echo "-----------------------------------------------------------"
File diff suppressed because it is too large Load Diff
-85
View File
@@ -1,85 +0,0 @@
# defs.mak.in --
# source file for autoconf-generated "defs.mak" for netgen
# defs.mak. Generated from defs.mak.in by configure.
# Feel free to change the values in here to suit your needs.
# Be aware that running scripts/configure again will overwrite
# any changes!
SHELL = /bin/sh
prefix = ${BUILDROOT}/usr/local
exec_prefix = ${prefix}
bindir = ${exec_prefix}/bin
libdir = ${exec_prefix}/lib
mandir = ${prefix}/share/man
VERSION =
SCRIPTS = ${NETGENDIR}/scripts
INSTALL = /bin/install -c
INSTALL_PROGRAM = ${INSTALL}
INSTALL_DATA = ${INSTALL} -m 644
INSTALL_SCRIPT = ${INSTALL}
# Override standard "make" target when compiling under TCL
ALL_TARGET = tcl
INSTALL_TARGET = install-tcl
# Change CADDIR to install in a different place
BINDIR = ${bindir}
MANDIR = ${mandir}
LIBDIR = ${libdir}
DOCDIR = ${libdir}/netgen/doc
TCLDIR = ${libdir}/netgen/tcl
PYDIR = ${libdir}/netgen/python
MAIN_EXTRA_LIBS = ${NETGENDIR}/tcltk/libtcltk.o
LD_EXTRA_LIBS =
LD_SHARED =
TOP_EXTRA_LIBS =
SUB_EXTRA_LIBS =
MODULES += tcltk
UNUSED_MODULES +=
PROGRAMS += tcltk
INSTALL_CAD_DIRS += tcltk
RM = rm -f
CP = cp
AR = @AR@
ARFLAGS = crv
LINK = /bin/ld -r
LD = /bin/ld
M4 = /bin/m4
RANLIB = ranlib
SHDLIB_EXT = .so
LDDL_FLAGS = -shared -Wl,-soname,$@ -Wl,--version-script=${NETGENDIR}/netgen/symbol.map
LD_RUN_PATH =
LIB_SPECS = -L/usr/lib64 -ltkstub8.6 -L/usr/lib64 -ltclstub8.6
LIB_SPECS_NOSTUB = -L/usr/lib64 -ltk8.6 -L/usr/lib64 -ltcl8.6
WISH_EXE = /usr/bin/wish
TCL_LIB_DIR = /usr/lib
CC = gcc
CPP = gcc -E -x c
CXX = @CXX@
CPPFLAGS = -I. -I${NETGENDIR}
DFLAGS = -DCAD_DIR=\"${LIBDIR}\" -DTCL_DIR=\"${TCLDIR}\" -DUSE_TCL_STUBS -DUSE_TK_STUBS -DPACKAGE_NAME=\"netgen\" -DPACKAGE_TARNAME=\"netgen\" -DPACKAGE_VERSION=\"1.3\" -DPACKAGE_STRING=\"netgen\ 1.3\" -DPACKAGE_BUGREPORT=\"[email protected]\" -DPACKAGE_URL=\"\" -DNETGEN_VERSION=\"1.5\" -DNETGEN_REVISION=\"102\" -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DSIZEOF_VOID_P=8 -DSIZEOF_UNSIGNED_INT=4 -DSIZEOF_UNSIGNED_LONG=8 -DSIZEOF_UNSIGNED_LONG_LONG=8 -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DHAVE_DIRENT_H=1 -DHAVE_LIMITS_H=1 -DHAVE_VA_COPY=1 -DHAVE___VA_COPY=1 -DDBUG_OFF=1 -DTCL_NETGEN=1 -Dlinux=1 -DSYSV=1 -DISC=1 -DSHDLIB_EXT=\".so\" -DNDEBUG
DFLAGS_NOSTUB = -DCAD_DIR=\"${LIBDIR}\" -DTCL_DIR=\"${TCLDIR}\" -DPACKAGE_NAME=\"netgen\" -DPACKAGE_TARNAME=\"netgen\" -DPACKAGE_VERSION=\"1.3\" -DPACKAGE_STRING=\"netgen\ 1.3\" -DPACKAGE_BUGREPORT=\"[email protected]\" -DPACKAGE_URL=\"\" -DNETGEN_VERSION=\"1.5\" -DNETGEN_REVISION=\"102\" -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DSIZEOF_VOID_P=8 -DSIZEOF_UNSIGNED_INT=4 -DSIZEOF_UNSIGNED_LONG=8 -DSIZEOF_UNSIGNED_LONG_LONG=8 -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DHAVE_DIRENT_H=1 -DHAVE_LIMITS_H=1 -DHAVE_VA_COPY=1 -DHAVE___VA_COPY=1 -DDBUG_OFF=1 -DTCL_NETGEN=1 -Dlinux=1 -DSYSV=1 -DISC=1 -DSHDLIB_EXT=\".so\" -DNDEBUG
CFLAGS = -g -m64 -fPIC -fPIC
DEPEND_FILE = Depend
DEPEND_FLAG = -MM
EXEEXT =
GR_CFLAGS =
GR_DFLAGS = -DX11 -DXLIB -DNDEBUG
GR_LIBS = -lX11
GR_SRCS = ${TK_SRCS}
OBJS = ${SRCS:.c=.o}
LIB_OBJS = ${LIB_SRCS:.c=.o}
CLEANS = ${OBJS} ${LIB_OBJS} lib${MODULE}.a lib${MODULE}.o ${MODULE}
+7
View File
@@ -35,6 +35,13 @@ DOCDIR = ${libdir}/netgen/doc
TCLDIR = ${libdir}/netgen/tcl
PYDIR = ${libdir}/netgen/python
INSTALL_BINDIR = @DIST_DIR@/bin
INSTALL_MANDIR = @DIST_DIR@/share/man
INSTALL_LIBDIR = @DIST_DIR@/lib
INSTALL_DOCDIR = ${INSTALL_LIBDIR}/netgen/doc
INSTALL_TCLDIR = ${INSTALL_LIBDIR}/netgen/tcl
INSTALL_PYDIR = ${INSTALL_LIBDIR}/netgen/python
MAIN_EXTRA_LIBS = @extra_libs@
LD_EXTRA_LIBS = @ld_extra_libs@
LD_SHARED = @ld_extra_objs@
-187
View File
@@ -1,187 +0,0 @@
#!/bin/csh -f
#
# makes the "database.h" (1st argument, $1) file from "database.h.in"
# (2nd argument, $2), setting various mask operation definitions
# according to the number of words implied by the value of TT_MAXTYPES
# The following mess grabs the value of TT_MAXTYPES from database.h.in
#
set maxtypes=`sed -n -e '/^#define[[:space:]]*TT_MAXTYPES/s/#define[[:space:]]*TT_MAXTYPES[[:space:]]*//p' < $1 | sed -e 's/\/\*[[:print:]]*\*\/[[:space:]]*//g' `
#
# Alternative method works with outdated versions of sed/ed.
#
if ($maxtypes == "") then
set maxtypes=`sed -n -e '/^#define[ ]*TT_MAXTYPES/s/#define[ ]*TT_MAXTYPES[ ]*//p' < $1 | sed -e 's/\/\*.*\*\/[ ]*//g' `
endif
#
# If we can't generate database.h correctly, nothing is going to compile.
#
if ($maxtypes == "") then
echo "Bad sed script in scripts/makedbh: Cannot generate database/database.h!"
exit
endif
# Find derived values from bits per word
# Note that bits-per-word should be determined from the compiler, but
# 32 bits per word has always been hardwired into magic.
#
set bpw = 32
# @ wordmask=$bpw - 1
# set wordshift=`echo "c=l($bpw); d=l(2); scale=0; c/d" | bc -l`
# @ maskwords=$maxtypes + $bpw - 1
# @ maskwords/=$bpw
@ maskwords=$maxtypes + $bpw - 1
@ maskwords/=$bpw
# Generate the main part of the database.h file from database.h.in
cat $1 > $2
# Generate a list of integers from 0 to the value of "maskwords" - 1
set count=""
@ maskwords--
while (${maskwords} >= 0)
set count=`echo ${count} ${maskwords}`
@ maskwords--
end
# Definitions
echo "#define TTMaskZero(m) ( \" >> $2
foreach i (${count})
echo -n " (m)->tt_words[$i] = 0" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskIsZero(m) ( \" >> $2
foreach i (${count})
echo -n " (m)->tt_words[$i] == 0" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo " && \" >> $2
endif
end
echo "#define TTMaskEqual(m, n) ( \" >> $2
foreach i (${count})
echo -n " (m)->tt_words[$i] == (n)->tt_words[$i]" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo " && \" >> $2
endif
end
echo "#define TTMaskIntersect(m, n) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] & (n)->tt_words[$i])" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo " || \" >> $2
endif
end
echo "#define TTMaskCom(m) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] = ~(m)->tt_words[$i])" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskCom2(m, n) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] = ~(n)->tt_words[$i])" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskSetMask(m, n) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] |= (n)->tt_words[$i])" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskSetMask3(m, n, o) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] |= (n)->tt_words[$i] | (o)->tt_words[$i])" \
>> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskAndMask(m, n) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] &= (n)->tt_words[$i])" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskAndMask3(m, n, o) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] = (n)->tt_words[$i] & (o)->tt_words[$i])" \
>> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskClearMask(m, n) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] &= ~(n)->tt_words[$i])" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskClearMask3(m, n, o) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] = (n)->tt_words[$i] & ~(o)->tt_words[$i])" \
>> $2
if ($i == 0) then
echo ")" >> $2
else
echo ", \" >> $2
endif
end
echo "" >> $2
echo "#endif /* _DATABASE_H */" >> $2
+14 -14
View File
@@ -12,20 +12,20 @@ CLEANS += netgen.sh netgen.tcl netgenexec${EXEEXT}
CFLAGS += -I${NETGENDIR}/base
TCL_FILES = \
$(DESTDIR)${TCLDIR}/tkcon.tcl \
$(DESTDIR)${TCLDIR}/console.tcl \
$(DESTDIR)${TCLDIR}/netgen.tcl
$(DESTDIR)${INSTALL_TCLDIR}/tkcon.tcl \
$(DESTDIR)${INSTALL_TCLDIR}/console.tcl \
$(DESTDIR)${INSTALL_TCLDIR}/netgen.tcl
tcl-main: netgenexec${EXEEXT} netgen.tcl netgen.sh
install-tcl: netgenexec${EXEEXT} $(DESTDIR)${BINDIR}/netgen.sh ${TCL_FILES}
${RM} $(DESTDIR)${TCLDIR}/netgenexec${EXEEXT}
${CP} netgenexec${EXEEXT} $(DESTDIR)${TCLDIR}/netgenexec${EXEEXT}
install-tcl: netgenexec${EXEEXT} $(DESTDIR)${INSTALL_BINDIR}/netgen.sh ${TCL_FILES}
${RM} $(DESTDIR)${INSTALL_TCLDIR}/netgenexec${EXEEXT}
${CP} netgenexec${EXEEXT} $(DESTDIR)${INSTALL_TCLDIR}/netgenexec${EXEEXT}
netgenexec${EXEEXT}: netgenexec.c
${CC} ${CFLAGS} ${CPPFLAGS} ${DFLAGS_NOSTUB} netgenexec.c \
-o netgenexec${EXEEXT} \
${LDFLAGS} ${LIBS} ${LIB_SPECS_NOSTUB}
${LIB_SPECS_NOSTUB} ${LDFLAGS} ${LIBS} ${GR_LIBS}
netgen.tcl: netgen.tcl.in
sed -e 's%TCL_DIR%${TCLDIR}%g' \
@@ -39,13 +39,13 @@ netgen.sh: netgen.sh.in
-e 's%WISH_EXE%${WISH_EXE}%g' \
netgen.sh.in > netgen.sh
$(DESTDIR)${TCLDIR}/%: %
${RM} $(DESTDIR)${TCLDIR}/$*
${CP} $* $(DESTDIR)${TCLDIR}/$*
$(DESTDIR)${INSTALL_TCLDIR}/%: %
${RM} $(DESTDIR)${INSTALL_TCLDIR}/$*
${CP} $* $(DESTDIR)${INSTALL_TCLDIR}/$*
$(DESTDIR)${BINDIR}/netgen.sh: netgen.sh
${RM} $(DESTDIR)${BINDIR}/netgen.sh $(DESTDIR)${BINDIR}/netgen
${CP} netgen.sh $(DESTDIR)${BINDIR}/netgen
(cd $(DESTDIR)${BINDIR}; chmod 0755 netgen)
$(DESTDIR)${INSTALL_BINDIR}/netgen.sh: netgen.sh
${RM} $(DESTDIR)${INSTALL_BINDIR}/netgen.sh $(DESTDIR)${INSTALL_BINDIR}/netgen
${CP} netgen.sh $(DESTDIR)${INSTALL_BINDIR}/netgen
(cd $(DESTDIR)${INSTALL_BINDIR}; chmod 0755 netgen)
include ${NETGENDIR}/rules.mak
+108 -20
View File
@@ -138,7 +138,7 @@ proc netgen::convert_to_json {filename lvs_final} {
foreach net $cktval {
incr nidx
puts $fjson " \["
set netname [string map {"\\" ""} [lindex $net 0]]
set netname [string map {"\\" "\\\\"} [lindex $net 0]]
puts $fjson " \"$netname\","
puts $fjson " \["
set netconn [lindex $net 1]
@@ -169,7 +169,7 @@ proc netgen::convert_to_json {filename lvs_final} {
foreach net $cktval {
incr nidx
puts $fjson " \["
set netname [string map {"\\" ""} [lindex $net 0]]
set netname [string map {"\\" "\\\\"} [lindex $net 0]]
puts $fjson " \"$netname\","
puts $fjson " \["
set netconn [lindex $net 1]
@@ -221,7 +221,7 @@ proc netgen::convert_to_json {filename lvs_final} {
foreach inst $cktval {
incr iidx
puts $fjson " \["
set instname [lindex $inst 0]
set instname [string map {"\\" "\\\\"} [lindex $inst 0]]
puts $fjson " \"$instname\","
puts $fjson " \["
set instpins [lindex $inst 1]
@@ -250,7 +250,7 @@ proc netgen::convert_to_json {filename lvs_final} {
foreach inst $cktval {
incr iidx
puts $fjson " \["
set instname [lindex $inst 0]
set instname [string map {"\\" "\\\\"} [lindex $inst 0]]
puts $fjson " \"$instname\","
puts $fjson " \["
set instpins [lindex $inst 1]
@@ -292,8 +292,8 @@ proc netgen::convert_to_json {filename lvs_final} {
foreach instance $value {
incr pidx
puts $fjson " \["
set instnames [lindex $instance 0]
set instname0 [lindex $instnames 0]
set instnames [string map {"\\" "\\\\"} [lindex $instance 0]]
set instname0 [string map {"\\" "\\\\"} [lindex $instnames 0]]
puts $fjson " \["
puts $fjson " \"${instname0}\","
puts $fjson " \["
@@ -310,7 +310,7 @@ proc netgen::convert_to_json {filename lvs_final} {
puts $fjson " \[\"${propname}\", \"${propval}\"\]"
puts $fjson " \]"
puts $fjson " \],"
set instname1 [lindex $instnames 1]
set instname1 [string map {"\\" "\\\\"} [lindex $instnames 1]]
puts $fjson " \["
puts $fjson " \"${instname1}\","
puts $fjson " \["
@@ -352,7 +352,7 @@ proc netgen::convert_to_json {filename lvs_final} {
close $fjson
}
#----------------------------------------------------------------
#-----------------------------------------------------------------------
# Define the "lvs" command as a way of calling the netgen options
# for standard compare, essentially the same as the old "netcomp"
# standalone program.
@@ -361,14 +361,20 @@ proc netgen::convert_to_json {filename lvs_final} {
# although if the cells have not been read in yet, then the
# original syntax of filename or {filename cellname} is required.
#
# "args" is passed to verify and may therefore contain only the
# value "-list" or nothing. If "-list", then output is returned
# as a nested list.
#----------------------------------------------------------------
# "args" may be "-list", "-json", or "-blackbox".
# "-list" returns output as a nested list.
# "-json" creates a .json-format output file in addition to stdout.
# "-blackbox" treats empty cells as black-box entries.
# "-noflatten={list}" is a list of cells not to flatten if mismatched.
# i.e., the cells are expected to match and any mismatch cannot be
# expected to be resolved by flattening the contents of the mismatched
# cells.
#-----------------------------------------------------------------------
proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
set dolist 0
set dojson 0
set noflat {}
foreach arg $args {
if {$arg == "-list"} {
puts stdout "Generating list result"
@@ -382,6 +388,30 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
} elseif {$arg == "-blackbox"} {
puts stdout "Treating empty subcircuits as black-box cells"
netgen::model blackbox on
} elseif {[string first "-noflatten=" $arg] == 0} {
set value [string range $arg 11 end]
# If argument is a filename then read the list of cells from it;
# otherwise, argument is the list of files itself in quotes or
# braces.
if {![catch {file exists $value}]} {
if {![catch {open $value r} fnf]} {
while {[gets $fnf line] >= 0} {
if {[lindex $line 0] != "#"} {
foreach cell $line {
lappend noflat $cell
}
}
}
close $fnf
} else {
puts stderr "Cannot open file $value for reading cell list."
}
} else {
set noflat [string trim $value \"\{\}]
}
if {[llength $noflat] > 0} {
puts stdout "Will not flatten these subcells: $noflat"
}
}
}
@@ -501,6 +531,8 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
return
}
set properr {}
set matcherr {}
set pinsgood -1
while {$endval != {}} {
if {$dolist == 1} {
netgen::run -list converge
@@ -528,12 +560,32 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
# Flatten the non-matching subcircuit (but not the top-level cells)
if {[netgen::print queue] != {}} {
netgen::log put " Flattening non-matched subcircuits $endval"
netgen::flatten class "[lindex $endval 0] $fnum1"
netgen::flatten class "[lindex $endval 1] $fnum2"
if {([lsearch $noflat [lindex $endval 0]] == -1) &&
([lsearch $noflat [lindex $endval 1]] == -1)} {
netgen::log put " Flattening non-matched subcircuits $endval"
netgen::flatten class "[lindex $endval 0] $fnum1"
netgen::flatten class "[lindex $endval 1] $fnum2"
} else {
netgen::log put " Continuing with black-boxed subcircuits $endval"
lappend matcherr [lindex $endval 0]
# Match pins
netgen::log echo off
if {$dolist == 1} {
set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
if {$result != 0} {
equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"
}
set pinsgood $result
netgen::log echo on
}
}
} else {
# Match pins
netgen::log echo off
if {$dolist == 1} {
set result [equate -list pins "$fnum1 [lindex $endval 0]" \
@@ -546,15 +598,43 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"
}
# If $uresult == -1 then these are black-box entries and
# $pinsgood should not be set to the resulting value.
if {$uresult > 0} {
set pinsgood $result
}
netgen::log echo on
}
if {$uresult == 2} {lappend properr [lindex $endval 0]}
} else {
# Flatten the non-matching subcircuit (but not the top-level cells)
if {[netgen::print queue] != {}} {
netgen::log put " Flattening non-matched subcircuits $endval"
netgen::flatten class "[lindex $endval 0] $fnum1"
netgen::flatten class "[lindex $endval 1] $fnum2"
if {([lsearch $noflat [lindex $endval 1]] == -1) &&
([lsearch $noflat [lindex $endval 1]] == -1)} {
netgen::log put " Flattening non-matched subcircuits $endval"
netgen::flatten class "[lindex $endval 0] $fnum1"
netgen::flatten class "[lindex $endval 1] $fnum2"
} else {
netgen::log put " Continuing with black-boxed subcircuits $endval"
lappend matcherr [lindex $endval 0]
netgen::log put " Continuing with black-boxed subcircuits $endval"
lappend matcherr [lindex $endval 0]
# Match pins
netgen::log echo off
if {$dolist == 1} {
set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
if {$result != 0} {
equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"
}
set pinsgood $result
netgen::log echo on
}
}
}
netgen::log echo off
@@ -569,10 +649,18 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
netgen::log echo off
puts stdout "Result: " nonewline
netgen::log echo on
verify only
if {$pinsgood == 0} {
# NOTE: Need to disambiguate these two cases. . .
netgen::log put "Cells failed matching, or top level cell failed pin matching.\n"
} else {
verify only
}
if {$properr != {}} {
netgen::log put "The following cells had property errors: $properr\n"
}
if {$matcherr != {}} {
netgen::log put "The following subcells failed to match: $matcherr\n"
}
if {$dolog} {
netgen::log end
}
+367 -76
View File
@@ -85,6 +85,7 @@ int _netcmp_compare(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_iterate(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_summary(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_print(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_format(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_run(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_verify(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_automorphs(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
@@ -93,6 +94,7 @@ int _netcmp_ignore(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_permute(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_property(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_exhaustive(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_symmetry(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_restart(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_global(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
int _netcmp_convert(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
@@ -199,6 +201,9 @@ Command netcmp_cmds[] = {
{"print", _netcmp_print,
"\n "
"print netcomp internal data structure"},
{"format", _netcmp_format,
"<col1_width> <col2_width>\n "
"set width of formatted output"},
{"run", _netcmp_run,
"[converge|resolve]\n "
"converge: run netcomp to completion (convergence)\n "
@@ -240,6 +245,8 @@ Command netcmp_cmds[] = {
{"exhaustive", _netcmp_exhaustive,
"\n "
"toggle exhaustive subdivision"},
{"symmetry", _netcmp_symmetry,
"(deprecated)"},
{"restart", _netcmp_restart,
"\n "
"start over (reset data structures)"},
@@ -1528,23 +1535,24 @@ int
_netgen_model(ClientData clientData,
Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
{
struct nlist *tp;
struct nlist *tp, *tp2;
char *model, *retclass;
unsigned char class;
int fnum = -1;
int result, index, nports;
int result, index, nports, nports2;
char *modelclasses[] = {
"undefined", "nmos", "pmos", "pnp", "npn",
"resistor", "capacitor", "diode",
"inductor", "module", "blackbox", "xline",
"moscap", "mosfet", "bjt", "subcircuit", NULL
"moscap", "mosfet", "bjt", "subcircuit", "copy",
NULL
};
enum OptionIdx {
UNDEF_IDX, NMOS_IDX, PMOS_IDX, PNP_IDX, NPN_IDX,
RES_IDX, CAP_IDX, DIODE_IDX, INDUCT_IDX,
MODULE_IDX, BLACKBOX_IDX, XLINE_IDX, MOSCAP_IDX,
MOSFET_IDX, BJT_IDX, SUBCKT_IDX
MOSFET_IDX, BJT_IDX, SUBCKT_IDX, COPY_IDX
};
if (objc != 3 && objc != 2) {
@@ -1576,7 +1584,7 @@ _netgen_model(ClientData clientData,
if (objc == 3) {
model = Tcl_GetString(objv[2]);
nports = NumberOfPorts(model);
nports = NumberOfPorts(model, fnum);
if (Tcl_GetIndexFromObj(interp, objv[2], (CONST84 char **)modelclasses,
"class", 0, &index) != TCL_OK) {
@@ -1640,6 +1648,40 @@ _netgen_model(ClientData clientData,
break;
case SUBCKT_IDX:
class = CLASS_SUBCKT;
break;
case COPY_IDX:
/* "copy" is not a class, but indicates that the cell, */
/* if undefined or a module, should have its class */
/* taken from the other circuit, if that circuit has a */
/* cell of the same name. */
if (Circuit1 == NULL || Circuit2 == NULL) {
Tcl_SetResult(interp, "Circuits have not been queued for comparison.",
NULL);
return TCL_ERROR;
}
if (tp == Circuit1) {
tp2 = LookupCellFile(tp->name, Circuit2->file);
nports2 = NumberOfPorts(tp2->name, Circuit2->file);
}
else if (tp == Circuit2) {
tp2 = LookupCellFile(tp->name, Circuit1->file);
nports2 = NumberOfPorts(tp2->name, Circuit1->file);
}
else {
Tcl_SetResult(interp, "The referenced netlist is not being compared.",
NULL);
return TCL_ERROR;
}
/* Should a non-matching number of ports be considered a fatal error? */
// if (nports2 != nports) {
// Tcl_SetResult(interp, "The number of ports for this cell does not "
// "match between netlists.", NULL);
// return TCL_ERROR;
// }
class = tp2->class;
/* To do (maybe): Rename tp ports to match tp2? */
break;
}
tp->class = class;
@@ -1971,6 +2013,61 @@ _netgen_printmem(ClientData clientData,
}
#endif
/*------------------------------------------------------*/
/* Function name: _netcmp_format */
/* Syntax: */
/* netgen::format [col1_width [col2_width]] */
/* Formerly: (none) */
/* Results: */
/* Side Effects: */
/*------------------------------------------------------*/
int
_netcmp_format(ClientData clientData,
Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
{
int col1_width = 41, col2_width = 41;
if (objc > 1) {
if (Tcl_GetIntFromObj(interp, objv[1], &col1_width) != TCL_OK)
return TCL_ERROR;
if (objc > 2) {
if (Tcl_GetIntFromObj(interp, objv[2], &col2_width) != TCL_OK)
return TCL_ERROR;
} else {
/* If only one argument is given, then apply it to both columns */
col2_width = col1_width;
}
if (col1_width <= 0 || col2_width <= 0) {
Tcl_SetResult(interp, "Column width cannot be zero or less\n", NULL);
}
// Default values for left and right columns are 43 and 87
left_col_end = col1_width + 2;
right_col_end = left_col_end + col2_width + 3;
}
else if (objc == 1) {
Tcl_Obj *lobj, *tobj;
col1_width = left_col_end - 2;
col2_width = right_col_end - col1_width - 5;
lobj = Tcl_NewListObj(0, NULL);
tobj = Tcl_NewIntObj(col1_width);
Tcl_ListObjAppendElement(interp, lobj, Tcl_NewIntObj(col1_width));
Tcl_ListObjAppendElement(interp, lobj, Tcl_NewIntObj(col2_width));
Tcl_SetObjResult(interp, lobj);
return TCL_OK;
}
else {
Tcl_WrongNumArgs(interp, 1, objv, "[col1_width [col2_width]]");
return TCL_ERROR;
}
}
/*------------------------------------------------------*/
/* The following code breaks up the NETCOMP() command */
/* from netcmp.c into individual functions w/arguments */
@@ -2331,6 +2428,8 @@ _netcmp_run(ClientData clientData,
else {
enable_interrupt();
while (!Iterate() && !InterruptPending);
ExhaustiveSubdivision = 1;
while (!Iterate() && !InterruptPending);
if (dolist) {
result = _netcmp_verify(clientData, interp, 2, objv - 1);
}
@@ -2349,6 +2448,8 @@ _netcmp_run(ClientData clientData,
else {
enable_interrupt();
while (!Iterate() && !InterruptPending);
ExhaustiveSubdivision = 1;
while (!Iterate() && !InterruptPending);
automorphisms = VerifyMatching();
if (automorphisms == -1)
Fprintf(stdout, "Netlists do not match.\n");
@@ -2360,8 +2461,7 @@ _netcmp_run(ClientData clientData,
automorphisms = ResolveAutomorphsByProperty();
if (automorphisms == 0)
Fprintf(stdout, "Netlists match uniquely.\n");
else {
else if (automorphisms > 0) {
// Next, attempt to resolve automorphisms uniquely by
// using the pin names
automorphisms = ResolveAutomorphsByPin();
@@ -2369,14 +2469,17 @@ _netcmp_run(ClientData clientData,
if (automorphisms == 0)
Fprintf(stdout, "Netlists match uniquely.\n");
else
else if (automorphisms > 0) {
// Anything left is truly indistinguishable
Fprintf(stdout, "Netlists match with %d symmetr%s.\n",
automorphisms, (automorphisms == 1) ? "y" : "ies");
while ((automorphisms = ResolveAutomorphisms()) > 0);
if (automorphisms == -1) Fprintf(stdout, "Netlists do not match.\n");
else Fprintf(stdout, "Circuits match correctly.\n");
while ((automorphisms = ResolveAutomorphisms()) > 0);
}
if (automorphisms == -1)
Fprintf(stdout, "Netlists do not match.\n");
else
Fprintf(stdout, "Circuits match correctly.\n");
}
if (PropertyErrorDetected) {
Fprintf(stdout, "There were property errors.\n");
@@ -2730,11 +2833,13 @@ _netcmp_equate(ClientData clientData,
char *name1 = NULL, *name2 = NULL, *optstart;
struct nlist *tp1, *tp2, *SaveC1, *SaveC2;
struct objlist *ob1, *ob2;
struct ElementClass *saveEclass = NULL;
struct NodeClass *saveNclass = NULL;
int file1, file2;
int i, l1, l2, ltest, lent, dolist = 0;
int i, l1, l2, ltest, lent, dolist = 0, doforce = 0;
Tcl_Obj *tobj1, *tobj2, *tobj3;
if (objc > 1) {
while (objc > 1) {
optstart = Tcl_GetString(objv[1]);
if (*optstart == '-') optstart++;
if (!strcmp(optstart, "list")) {
@@ -2742,6 +2847,13 @@ _netcmp_equate(ClientData clientData,
objv++;
objc--;
}
else if (!strcmp(optstart, "force")) {
doforce = 1;
objv++;
objc--;
}
else
break;
}
if ((objc != 2) && (objc != 4) && (objc != 6)) {
@@ -2899,16 +3011,41 @@ _netcmp_equate(ClientData clientData,
break;
case PINS_IDX:
if ((ElementClasses == NULL) && (auto_blackbox == FALSE)) {
if (CurrentCell == NULL)
Fprintf(stderr, "Equate elements: no current cell.\n");
Fprintf(stderr, "Equate pins: cell %s and/or %s has no elements.\n",
name1, name2);
Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
return TCL_OK;
if ((ElementClasses != NULL) && (doforce == TRUE)) {
saveEclass = ElementClasses;
saveNclass = NodeClasses;
ElementClasses = NULL;
NodeClasses = NULL;
}
else if (ElementClasses == NULL) {
/* This has been called outside of a netlist compare, */
if ((ElementClasses == NULL) && (auto_blackbox == FALSE)) {
if (CurrentCell == NULL) {
Fprintf(stderr, "Equate elements: no current cell.\n");
Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
return TCL_OK;
}
else if ((tp1->flags & CELL_PLACEHOLDER) ||
(tp2->flags & CELL_PLACEHOLDER)) {
if (tp1->flags & CELL_PLACEHOLDER) {
Fprintf(stdout, "Warning: Equate pins: cell %s "
"has no definition, treated as a black box.\n", name1);
}
if (tp2->flags & CELL_PLACEHOLDER) {
Fprintf(stdout, "Warning: Equate pins: cell %s "
"has no definition, treated as a black box.\n", name2);
}
// If a cell in either circuit is marked as a black box, then
// the cells in both circuits should be marked as a black box.
tp1->flags |= CELL_PLACEHOLDER;
tp2->flags |= CELL_PLACEHOLDER;
}
else {
Fprintf(stdout, "Equate pins: cell %s and/or %s "
"has no elements.\n", name1, name2);
/* This is not necessarily an error, so go ahead and match pins. */
}
}
if (ElementClasses == NULL) {
/* This may have been called outside of a netlist compare, */
/* probably to force name matching of pins on black-box */
/* devices. But MatchPins only works if tp1 == Circuit1 */
/* and tp2 == Circuit2, so preserve these values and */
@@ -2942,6 +3079,12 @@ _netcmp_equate(ClientData clientData,
/* Recover temporarily set global variables (see above) */
Circuit1 = SaveC1;
Circuit2 = SaveC2;
/* Recover ElementClasses if forcing pins on mismatched circuits */
if (doforce == TRUE) {
ElementClasses = saveEclass;
NodeClasses = saveNclass;
}
}
break;
@@ -3157,19 +3300,25 @@ _netcmp_equate(ClientData clientData,
/* add --- add new property */
/* remove --- delete existing property */
/* tolerance --- set property tolerance */
/* merge --- set property merge behavior */
/* merge --- (deprecated) */
/* or */
/* netgen::property default */
/* or */
/* netgen::property <device>|<model> <option> */
/* yes|no */
/* Where <option> is one of: */
/* serial --- allow/prohibit serial combination */
/* series --- allow/prohibit series combination */
/* parallel --- allow/prohibit parallel combination */
/* or */
/* netgen::property parallel none */
/* --- prohibit parallel combinations by */
/* default. */
/* default (for all devices). */
/* */
/* series|parallel options are: */
/* enable|disable|none|{<key> <combine_option>} */
/* */
/* combine options are: */
/* par|add|par_critical|add_critical */
/* */
/* Formerly: (none) */
/* Results: */
@@ -3189,31 +3338,45 @@ _netcmp_property(ClientData clientData,
char *options[] = {
"add", "create", "remove", "delete", "tolerance", "merge", "serial",
"parallel", NULL
"series", "parallel", NULL
};
enum OptionIdx {
ADD_IDX, CREATE_IDX, REMOVE_IDX, DELETE_IDX, TOLERANCE_IDX, MERGE_IDX,
SERIAL_IDX, PARALLEL_IDX
SERIAL_IDX, SERIES_IDX, PARALLEL_IDX
};
int result, index, idx2;
char *suboptions[] = {
"integer", "double", "value", "string", NULL
"integer", "double", "value", "string", "expression", NULL
};
enum SubOptionIdx {
INTEGER_IDX, DOUBLE_IDX, VALUE_IDX, STRING_IDX
INTEGER_IDX, DOUBLE_IDX, VALUE_IDX, STRING_IDX, EXPRESSION_IDX
};
/* Note: "merge" has been deprecated, but kept for backwards compatibility. */
/* It has been replaced by "combineoptions" below, used with "series" and */
/* "parallel". */
char *mergeoptions[] = {
"none", "add", "add_critical", "par", "par_critical",
"parallel", "parallel_critical", "ser_critical", "ser",
"serial_critical", "serial", NULL
"serial_critical", "series_critical", "serial", "series", NULL
};
enum MergeOptionIdx {
NONE_IDX, ADD_ONLY_IDX, ADD_CRIT_IDX,
PAR_ONLY_IDX, PAR_CRIT_IDX, PAR2_ONLY_IDX, PAR2_CRIT_IDX,
SER_CRIT_IDX, SER_IDX, SER2_CRIT_IDX, SER2_IDX
SER_CRIT_IDX, SER_IDX, SER2_CRIT_IDX, SER3_CRIT_IDX, SER2_IDX, SER3_IDX
};
char *combineoptions[] = {
"none", "par", "add", "critical", NULL
};
enum CombineOptionIdx {
COMB_NONE_IDX, COMB_PAR_IDX, COMB_ADD_IDX, COMB_CRITICAL_IDX
};
char *yesno[] = {
"on", "yes", "true", "enable", "allow",
"off", "no", "false", "disable", "prohibit", NULL
@@ -3238,25 +3401,34 @@ _netcmp_property(ClientData clientData,
case CLASS_NMOS: case CLASS_PMOS: case CLASS_FET3:
case CLASS_NMOS4: case CLASS_PMOS4: case CLASS_FET4:
case CLASS_FET:
PropertyMerge(tp->name, tp->file, "w", MERGE_ADD_CRIT);
PropertyMerge(tp->name, tp->file, "w", MERGE_P_ADD | MERGE_P_CRIT,
MERGE_ALL_MASK);
PropertyDelete(tp->name, tp->file, "as");
PropertyDelete(tp->name, tp->file, "ad");
PropertyDelete(tp->name, tp->file, "ps");
PropertyDelete(tp->name, tp->file, "pd");
break;
case CLASS_RES: case CLASS_RES3:
PropertyMerge(tp->name, tp->file, "w", MERGE_ADD_CRIT);
PropertyMerge(tp->name, tp->file, "l", MERGE_SER_CRIT);
tp->flags |= COMB_SERIAL;
PropertyMerge(tp->name, tp->file, "w",
MERGE_P_PAR | MERGE_S_CRIT, MERGE_ALL_MASK);
PropertyMerge(tp->name, tp->file, "l",
MERGE_S_ADD | MERGE_P_CRIT, MERGE_ALL_MASK);
PropertyMerge(tp->name, tp->file, "value",
MERGE_S_ADD | MERGE_P_PAR, MERGE_ALL_MASK);
tp->flags |= COMB_SERIES;
break;
case CLASS_CAP: case CLASS_ECAP: case CLASS_CAP3:
// NOTE: No attempt to combine area, width, or length;
// only value.
PropertyMerge(tp->name, tp->file, "value", MERGE_ADD_CRIT);
/* NOTE: No attempt to modify perimeter, length, or width */
PropertyMerge(tp->name, tp->file, "area",
MERGE_P_ADD | MERGE_S_PAR, MERGE_ALL_MASK);
PropertyMerge(tp->name, tp->file, "value",
MERGE_P_ADD | MERGE_S_PAR, MERGE_ALL_MASK);
tp->flags |= COMB_SERIES;
break;
case CLASS_INDUCTOR:
PropertyMerge(tp->name, tp->file, "value", MERGE_PAR_CRIT);
tp->flags |= COMB_SERIAL;
PropertyMerge(tp->name, tp->file, "value",
MERGE_S_ADD | MERGE_P_PAR, MERGE_ALL_MASK);
tp->flags |= COMB_SERIES;
break;
}
tp = NextCell();
@@ -3272,9 +3444,30 @@ _netcmp_property(ClientData clientData,
GlobalParallelNone = FALSE;
SetParallelCombine(TRUE);
}
else if (!strcmp(Tcl_GetString(objv[2]), "connected")) {
GlobalParallelOpen = FALSE;
}
else if (!strcmp(Tcl_GetString(objv[2]), "open")) {
GlobalParallelOpen = TRUE;
}
else {
Tcl_SetResult(interp, "Bad option, should be property parallel none|all",
NONE);
Tcl_SetResult(interp, "Bad option, should be property parallel "
"none|all|connected", NULL);
return TCL_ERROR;
}
return TCL_OK;
}
else if ((objc == 3) && ((!strcmp(Tcl_GetString(objv[1]), "series")) ||
(!strcmp(Tcl_GetString(objv[1]), "serial")))) {
if (!strcmp(Tcl_GetString(objv[2]), "none")) {
SetSeriesCombine(FALSE);
}
else if (!strcmp(Tcl_GetString(objv[2]), "all")) {
SetSeriesCombine(TRUE);
}
else {
Tcl_SetResult(interp, "Bad option, should be property series none|all",
NULL);
return TCL_ERROR;
}
return TCL_OK;
@@ -3329,10 +3522,11 @@ _netcmp_property(ClientData clientData,
switch (index) {
case SERIAL_IDX:
case SERIES_IDX:
case PARALLEL_IDX:
if (objc == 3) {
if (index == SERIAL_IDX) {
tobj1 = Tcl_NewBooleanObj((tp->flags & COMB_SERIAL) ? 1 : 0);
if (index == SERIAL_IDX || index == SERIES_IDX) {
tobj1 = Tcl_NewBooleanObj((tp->flags & COMB_SERIES) ? 1 : 0);
Tcl_SetObjResult(interp, tobj1);
return TCL_OK;
}
@@ -3342,30 +3536,97 @@ _netcmp_property(ClientData clientData,
return TCL_OK;
}
}
else if (objc == 4) {
if (Tcl_GetIndexFromObj(interp, objv[3],
(CONST84 char **)yesno,
"combine", 0, &idx2) != TCL_OK) {
Tcl_WrongNumArgs(interp, 3, objv, "enable|disable");
return TCL_ERROR;
}
if (idx2 <= 4) { /* true, enable, etc. */
if (index == SERIAL_IDX)
tp->flags |= COMB_SERIAL;
else
tp->flags &= ~COMB_NO_PARALLEL;
}
else { /* false, disable, etc. */
if (index == SERIAL_IDX)
tp->flags &= ~COMB_SERIAL;
else
tp->flags |= COMB_NO_PARALLEL;
}
}
else {
Tcl_WrongNumArgs(interp, 2, objv, "serial|parallel enable|disable");
else if (objc < 4) {
Tcl_WrongNumArgs(interp, 2, objv, "series|parallel enable|disable");
return TCL_ERROR;
}
for (i = 3; i < objc; i++) {
// Each value must be a list of two, or a yes/no answer.
if (Tcl_GetIndexFromObj(interp, objv[i],
(CONST84 char **)yesno,
"combine", 0, &idx2) == TCL_OK) {
if (idx2 <= 4) { /* true, enable, etc. */
if (index == SERIAL_IDX || index == SERIES_IDX)
tp->flags |= COMB_SERIES;
else
tp->flags &= ~COMB_NO_PARALLEL;
}
else { /* false, disable, etc. */
if (index == SERIAL_IDX || index == SERIES_IDX)
tp->flags &= ~COMB_SERIES;
else
tp->flags |= COMB_NO_PARALLEL;
}
continue;
}
result = Tcl_ListObjLength(interp, objv[i], &llen);
if ((result != TCL_OK) || (llen != 2)) {
Tcl_SetResult(interp, "Not a {key merge_type} pair list.",
NULL);
}
else {
int mergeval = MERGE_NONE;
int mergemask = MERGE_NONE;
result = Tcl_ListObjIndex(interp, objv[i], 0, &tobj1);
if (result != TCL_OK) return result;
result = Tcl_ListObjIndex(interp, objv[i], 1, &tobj2);
if (result != TCL_OK) return result;
result = Tcl_GetIndexFromObj(interp, tobj2,
(CONST84 char **)combineoptions,
"combine_type", 0, &idx2);
if (result != TCL_OK) return result;
if (index == SERIAL_IDX || index == SERIES_IDX) {
mergemask = MERGE_S_MASK;
switch (idx2) {
case COMB_NONE_IDX:
mergeval &= ~(MERGE_S_MASK);
tp->flags &= ~COMB_SERIES;
break;
case COMB_PAR_IDX:
mergeval = MERGE_S_PAR;
tp->flags |= COMB_SERIES;
break;
case COMB_ADD_IDX:
mergeval |= MERGE_S_ADD;
tp->flags |= COMB_SERIES;
break;
case COMB_CRITICAL_IDX:
mergeval |= MERGE_S_CRIT;
tp->flags |= COMB_SERIES;
break;
}
}
else { /* index == PARALLEL_IDX */
mergemask = MERGE_P_MASK;
switch (idx2) {
case COMB_NONE_IDX:
mergeval &= ~(MERGE_P_MASK);
tp->flags |= COMB_NO_PARALLEL;
break;
case COMB_PAR_IDX:
mergeval |= MERGE_P_PAR;
tp->flags &= ~COMB_NO_PARALLEL;
break;
case COMB_ADD_IDX:
mergeval |= MERGE_P_ADD;
tp->flags &= ~COMB_NO_PARALLEL;
break;
case COMB_CRITICAL_IDX:
mergeval |= MERGE_P_CRIT;
tp->flags &= ~COMB_NO_PARALLEL;
break;
}
}
PropertyMerge(tp->name, fnum, Tcl_GetString(tobj1), mergeval,
mergemask);
}
}
break;
case ADD_IDX:
@@ -3478,6 +3739,11 @@ _netcmp_property(ClientData clientData,
PropertyString(tp->name, fnum,
Tcl_GetString(tobj1), ival, NULL);
break;
case EXPRESSION_IDX:
PropertyString(tp->name, fnum,
Tcl_GetString(tobj1), 0,
Tcl_GetString(tobj3));
break;
}
break;
}
@@ -3535,6 +3801,11 @@ _netcmp_property(ClientData clientData,
break;
case MERGE_IDX:
// NOTE: This command option is deprecated, kept for backwards
// compatibility, with updated flag values. This command format
// is unable to specify a property as being a critical property
// for merging both in series and in parallel.
if (objc == 3) {
Tcl_WrongNumArgs(interp, 1, objv, "{property_key merge_type} ...");
return TCL_ERROR;
@@ -3564,29 +3835,32 @@ _netcmp_property(ClientData clientData,
mergeval = MERGE_NONE;
break;
case ADD_ONLY_IDX:
mergeval = MERGE_ADD;
mergeval = MERGE_P_ADD;
break;
case ADD_CRIT_IDX:
mergeval = MERGE_ADD_CRIT;
mergeval = MERGE_P_ADD | MERGE_P_XCRIT;
break;
case PAR_ONLY_IDX:
case PAR2_ONLY_IDX:
mergeval = MERGE_PAR;
mergeval = MERGE_P_PAR;
break;
case PAR_CRIT_IDX:
case PAR2_CRIT_IDX:
mergeval = MERGE_PAR_CRIT;
mergeval = MERGE_P_PAR | MERGE_P_XCRIT;
break;
case SER_CRIT_IDX:
case SER2_CRIT_IDX:
mergeval = MERGE_SER_CRIT;
case SER3_CRIT_IDX:
mergeval = MERGE_S_ADD | MERGE_S_XCRIT;
break;
case SER_IDX:
case SER2_IDX:
mergeval = MERGE_SER;
case SER3_IDX:
mergeval = MERGE_S_ADD;
break;
}
PropertyMerge(tp->name, fnum, Tcl_GetString(tobj1), mergeval);
PropertyMerge(tp->name, fnum, Tcl_GetString(tobj1), mergeval,
MERGE_ALL_MASK);
}
}
break;
@@ -3691,8 +3965,8 @@ _netcmp_permute(ClientData clientData,
if (PermuteForget(tp->name, fnum, NULL, NULL))
Fprintf(stdout, "No permutations on circuit %s\n", tp->name);
else
Fprintf(stderr, "Unable to reset model %s pin permutation %s, %s.\n",
tp->name, pin1, pin2);
Fprintf(stderr, "Unable to reset model %s pin permutations.\n",
tp->name);
}
return TCL_OK;
}
@@ -3739,6 +4013,23 @@ _netcmp_permute(ClientData clientData,
return TCL_OK;
}
/*------------------------------------------------------*/
/* Function name: _netcmp_symmetry */
/* Syntax: netgen::symmetry [fast|full] */
/* Formerly: x */
/* Results: */
/* Side Effects: */
/* Notes: Deprecated, retained for compatibility. */
/*------------------------------------------------------*/
int
_netcmp_symmetry(ClientData clientData,
Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
{
Printf("Symmetry breaking method has been deprecated.\n");
return TCL_OK;
}
/*------------------------------------------------------*/
/* Function name: _netcmp_exhaustive */
/* Syntax: netgen::exhaustive [on|off] */
@@ -3760,7 +4051,7 @@ _netcmp_exhaustive(ClientData clientData,
int result, index;
if (objc == 1)
index = YES_IDX;
index = -1;
else {
if (Tcl_GetIndexFromObj(interp, objv[1], (CONST84 char **)yesno,
"option", 0, &index) != TCL_OK)
+10 -10
View File
@@ -741,9 +741,9 @@ proc ::tkcon::EvalCmd {w cmd} {
set tag [UniqueTag $w]
$w insert output $res [list stderr $tag] \n stderr
$w tag bind $tag <Enter> \
[list $w tag configure $tag -under 1]
[list $w tag configure $tag -underline 1]
$w tag bind $tag <Leave> \
[list $w tag configure $tag -under 0]
[list $w tag configure $tag -underline 0]
$w tag bind $tag <ButtonRelease-1> \
"if {!\[info exists tkPriv(mouseMoved)\] || !\$tkPriv(mouseMoved)} \
{[list edit -attach [Attach] -type error -- $PRIV(errorInfo)]}"
@@ -2472,8 +2472,8 @@ proc ::tkcon::ErrorHighlight w {
set tag [UniqueTag $w]
$w tag add $tag $start+${c0}c $start+1c+${c1}c
$w tag configure $tag -foreground $COLOR(stdout)
$w tag bind $tag <Enter> [list $w tag configure $tag -under 1]
$w tag bind $tag <Leave> [list $w tag configure $tag -under 0]
$w tag bind $tag <Enter> [list $w tag configure $tag -underline 1]
$w tag bind $tag <Leave> [list $w tag configure $tag -underline 0]
$w tag bind $tag <ButtonRelease-1> "if {!\$tkPriv(mouseMoved)} \
{[list edit -attach $app -type proc -find $what -- $cmd]}"
}
@@ -2501,8 +2501,8 @@ proc ::tkcon::ErrorHighlight w {
set tag [UniqueTag $w]
$w tag add $tag $ix+1c $start
$w tag configure $tag -foreground $COLOR(proc)
$w tag bind $tag <Enter> [list $w tag configure $tag -under 1]
$w tag bind $tag <Leave> [list $w tag configure $tag -under 0]
$w tag bind $tag <Enter> [list $w tag configure $tag -underline 1]
$w tag bind $tag <Leave> [list $w tag configure $tag -underline 0]
$w tag bind $tag <ButtonRelease-1> "if {!\$tkPriv(mouseMoved)} \
{[list edit -attach $app -type proc -- $cmd]}"
}
@@ -2954,14 +2954,14 @@ proc edit {args} {
##
set text $w.text
set m [menu [::tkcon::MenuButton $menu Edit edit]]
$m add command -label "Cut" -under 2 \
$m add command -label "Cut" -underline 2 \
-command [list tk_textCut $text]
$m add command -label "Copy" -under 0 \
$m add command -label "Copy" -underline 0 \
-command [list tk_textCopy $text]
$m add command -label "Paste" -under 0 \
$m add command -label "Paste" -underline 0 \
-command [list tk_textPaste $text]
$m add separator
$m add command -label "Find" -under 0 \
$m add command -label "Find" -underline 0 \
-command [list ::tkcon::FindBox $text]
## Send To Menu