Fischer Moseley
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9611c0b554
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uart: fix #36, explicitly handle scientific notation in YAML config
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2025-04-06 18:28:29 -06:00 |
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Fischer Moseley
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f91f7c5fbb
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meta: add pre-commit, commit changes it makes
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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da21a3a414
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ethernet: load divider.sv via symlink
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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363bef8d87
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ethernet: add HWITL ethernet test
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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9ac3181502
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examples: fix typos
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2024-11-07 09:50:55 -07:00 |
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Fischer Moseley
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1c1c514a39
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logic_analyzer: only set triggers if extra info provided in config
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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9f2dffb069
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examples: make verilog/amaranth versions of uart_logic_analyzer match
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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daedb91ff2
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meta: sort imports with ruff
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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b31a655d58
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tests: include building examples in test suite
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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8f45546b5a
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manta: fix code generation from config file, update tests
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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13bc196a34
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rename Nexys A7 to Nexys 4 DDR
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2024-05-12 10:35:18 -07:00 |
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Fischer Moseley
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978937e4bc
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modify example design naming convention
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2024-05-12 10:25:00 -07:00 |
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Fischer Moseley
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4ae061ffdc
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add missing .gitignore
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2024-03-07 09:21:40 -08:00 |
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Fischer Moseley
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04cfa41190
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add logic analyzer/io core ethernet example
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2024-03-07 09:18:30 -08:00 |
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Fischer Moseley
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60066ccdca
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add examples for the Nexys4DDR, bump version to 1.0.0
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2024-03-06 23:07:20 -08:00 |
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Fischer Moseley
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05b9b450e8
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add logic analyzer icestick example
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2024-03-06 22:05:24 -08:00 |