examples: use symlinked build scripts, remove per-directory gitignores

.github/workflows/run_tests.yml

@@ -19,7 +19,7 @@ jobs:
 
       - name: Run tests
         run: |
-          source ./environment.sh
+          source .env
           uv run make test
 
       - name: Upload coverage reports

.gitignore

@@ -11,25 +11,11 @@ __pycache__/
 build/
 dist/
 
+# Autogenerated Manta source
+manta.v
+
 # Miscellaneous file types
-*.v
-*.sv
 *.vcd
-*.out
 *.csv
 *.xml
 .coverage*
-
-# Vivado files
-*.log
-*.jou
-*.rpt
-*.bin
-*.bit
-*.out
-.Xil/
-
-# Yosys/IceStorm files
-*.asc
-*.bin
-*.json

examples/common/.gitignore

@@ -1 +0,0 @@
-!divider.sv

examples/common/build.tcl

@@ -0,0 +1,35 @@
+#!/usr/bin/tclsh
+
+set partNum xc7a100tcsg324-1
+
+read_verilog -sv [ glob ../*.{sv,v,svh,vh} ]
+read_xdc ../top_level.xdc
+
+set_part $partNum
+
+# synth
+synth_design -top top_level -part $partNum -verbose
+report_utilization -file post_synth_util.rpt
+report_timing_summary -file post_synth_timing_summary.rpt
+report_timing -file post_synth_timing.rpt
+
+# place
+opt_design
+place_design
+phys_opt_design
+report_utilization -file post_place_util.rpt
+
+report_clock_utilization -file clock_util.rpt
+report_timing_summary -file post_place_timing_summary.rpt
+report_timing -file post_place_timing.rpt
+
+# route design and generate bitstream
+route_design -directive Explore
+write_bitstream -force out.bit
+
+report_route_status -file post_route_status.rpt
+report_timing_summary -file post_route_timing_summary.rpt
+report_timing -file post_route_timing.rpt
+report_power -file post_route_power.rpt
+report_drc -file post_imp_drc.rpt
+write_verilog -force cpu_impl_netlist.v -mode timesim -sdf_anno true

examples/common/build_ice40.sh

@@ -0,0 +1,21 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+# shellcheck source=examples/common/find_tool.sh
+source "$(dirname "$(readlink -f "$0")")/find_tool.sh"
+
+# Make sure tools are accessible
+YOSYS_CMD=$(find_tool yosys)
+NEXTPNR_ICE40_CMD=$(find_tool nextpnr-ice40)
+ICEPACK_CMD=$(find_tool icepack)
+
+# Generate Verilog source for Manta
+python3 -m manta gen manta.yaml manta.v
+
+# Clean build/ directory, and run tools from within it
+rm -rf build/
+mkdir -p build/
+cd build
+$YOSYS_CMD -p 'synth_ice40 -top top_level -json top_level.json' ../top_level.sv
+$NEXTPNR_ICE40_CMD --hx1k --json top_level.json --pcf ../top_level.pcf --asc top_level.asc
+$ICEPACK_CMD top_level.asc top_level.bin

examples/common/build_vivado.sh

@@ -0,0 +1,17 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+# shellcheck source=examples/common/find_tool.sh
+source "$(dirname "$(readlink -f "$0")")/find_tool.sh"
+
+# Make sure Vivado is accessible
+VIVADO_CMD=$(find_tool vivado)
+
+# Generate Verilog source for Manta
+python3 -m manta gen manta.yaml manta.v
+
+# Clean build/ directory, and run Vivado from within it
+rm -rf build/
+mkdir -p build/
+cd build
+$VIVADO_CMD -mode batch -source ../../../../common/build.tcl

examples/common/find_tool.sh

@@ -0,0 +1,35 @@
+#!/usr/bin/env bash
+
+# Find a tool binary from either the $PATH environment variable, or another
+# environment variable named after the tool (ie, $VIVADO or $YOSYS).
+# Usage: find_tool <tool_name>
+# The environment variable is the uppercased tool name, with any hyphens converted to underscores.
+# Prints the command to use, or exits with an error.
+find_tool() {
+    local tool="$1"
+    local env_var
+    env_var=$(echo "$tool" | tr '[:lower:]' '[:upper:]')
+    env_var="${env_var//-/_}"
+    local on_path=false
+    local env_set=false
+
+    if command -v "$tool" &> /dev/null; then
+        on_path=true
+    fi
+
+    if [[ -n "${!env_var+x}" ]]; then
+        env_set=true
+    fi
+
+    if $on_path && $env_set; then
+        echo "Error: Both \$$env_var is set and '$tool' is on PATH. Please use only one." >&2
+        exit 1
+    elif $on_path; then
+        echo "$tool"
+    elif $env_set; then
+        echo "${!env_var}"
+    else
+        echo "Error: $tool not found. Either set \$$env_var environment variable or add '$tool' to PATH." >&2
+        exit 1
+    fi
+}

examples/verilog/icestick/uart_io_core/.gitignore

@@ -1 +0,0 @@
-!top_level.sv

examples/verilog/icestick/uart_io_core/build.sh

@@ -1,7 +0,0 @@
-#!/usr/bin/env bash
-set -e
-
-python3 -m manta gen manta.yaml manta.v
-$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv
-$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc
-$ICEPACK top_level.asc top_level.bin

examples/verilog/icestick/uart_io_core/build.sh

@@ -0,0 +1 @@
+../../../common/build_ice40.sh

examples/verilog/icestick/uart_logic_analyzer/.gitignore

@@ -1 +0,0 @@
-!top_level.sv

examples/verilog/icestick/uart_logic_analyzer/build.sh

@@ -1,7 +0,0 @@
-#!/usr/bin/env bash
-set -e
-
-python3 -m manta gen manta.yaml manta.v
-$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv
-$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc
-$ICEPACK top_level.asc top_level.bin

examples/verilog/icestick/uart_logic_analyzer/build.sh

@@ -0,0 +1 @@
+../../../common/build_ice40.sh

examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/.gitignore

@@ -1,2 +0,0 @@
-!top_level.sv
-!divider.sv

examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh

@@ -1,6 +0,0 @@
-#!/usr/bin/env bash
-set -e
-
-python3 -m manta gen manta.yaml manta.v
-mkdir -p build/
-$VIVADO -mode batch -source build.tcl

examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh

@@ -0,0 +1 @@
+../../../common/build_vivado.sh

examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.tcl

@@ -1,36 +0,0 @@
-#!/usr/bin/tclsh
-
-set partNum xc7a100tcsg324-1
-set outputDir build
-
-read_verilog -sv [ glob *.{sv,v,svh,vh} ]
-read_xdc top_level.xdc
-
-set_part $partNum
-
-# synth
-synth_design -top top_level -part $partNum -verbose
-report_utilization -file $outputDir/post_synth_util.rpt
-report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
-report_timing -file $outputDir/post_synth_timing.rpt
-
-# place
-opt_design
-place_design
-phys_opt_design
-report_utilization -file $outputDir/post_place_util.rpt
-
-report_clock_utilization -file $outputDir/clock_util.rpt
-report_timing_summary -file $outputDir/post_place_timing_summary.rpt
-report_timing -file $outputDir/post_place_timing.rpt
-
-# route design and generate bitstream
-route_design -directive Explore
-write_bitstream -force $outputDir/out.bit
-
-report_route_status -file $outputDir/post_route_status.rpt
-report_timing_summary -file $outputDir/post_route_timing_summary.rpt
-report_timing -file $outputDir/post_route_timing.rpt
-report_power -file $outputDir/post_route_power.rpt
-report_drc -file $outputDir/post_imp_drc.rpt
-write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true

examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/.gitignore

@@ -1 +0,0 @@
-!top_level.sv

examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh

@@ -1,6 +0,0 @@
-#!/usr/bin/env bash
-set -e
-
-python3 -m manta gen manta.yaml manta.v
-mkdir -p build/
-$VIVADO -mode batch -source build.tcl

examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh

@@ -0,0 +1 @@
+../../../common/build_vivado.sh

examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.tcl

@@ -1,36 +0,0 @@
-#!/usr/bin/tclsh
-
-set partNum xc7a100tcsg324-1
-set outputDir build
-
-read_verilog -sv [ glob *.{sv,v,svh,vh} ]
-read_xdc top_level.xdc
-
-set_part $partNum
-
-# synth
-synth_design -top top_level -part $partNum -verbose
-report_utilization -file $outputDir/post_synth_util.rpt
-report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
-report_timing -file $outputDir/post_synth_timing.rpt
-
-# place
-opt_design
-place_design
-phys_opt_design
-report_utilization -file $outputDir/post_place_util.rpt
-
-report_clock_utilization -file $outputDir/clock_util.rpt
-report_timing_summary -file $outputDir/post_place_timing_summary.rpt
-report_timing -file $outputDir/post_place_timing.rpt
-
-# route design and generate bitstream
-route_design -directive Explore
-write_bitstream -force $outputDir/out.bit
-
-report_route_status -file $outputDir/post_route_status.rpt
-report_timing_summary -file $outputDir/post_route_timing_summary.rpt
-report_timing -file $outputDir/post_route_timing.rpt
-report_power -file $outputDir/post_route_power.rpt
-report_drc -file $outputDir/post_imp_drc.rpt
-write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true

examples/verilog/nexys4_ddr/uart_io_core/.gitignore

@@ -1 +0,0 @@
-!top_level.sv

examples/verilog/nexys4_ddr/uart_io_core/build.sh

@@ -1,6 +0,0 @@
-#!/usr/bin/env bash
-set -e
-
-python3 -m manta gen manta.yaml manta.v
-mkdir -p build/
-$VIVADO -mode batch -source build.tcl

examples/verilog/nexys4_ddr/uart_io_core/build.sh

@@ -0,0 +1 @@
+../../../common/build_vivado.sh

examples/verilog/nexys4_ddr/uart_io_core/build.tcl

@@ -1,36 +0,0 @@
-#!/usr/bin/tclsh
-
-set partNum xc7a100tcsg324-1
-set outputDir build
-
-read_verilog -sv [ glob *.{sv,v,svh,vh} ]
-read_xdc top_level.xdc
-
-set_part $partNum
-
-# synth
-synth_design -top top_level -part $partNum -verbose
-report_utilization -file $outputDir/post_synth_util.rpt
-report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
-report_timing -file $outputDir/post_synth_timing.rpt
-
-# place
-opt_design
-place_design
-phys_opt_design
-report_utilization -file $outputDir/post_place_util.rpt
-
-report_clock_utilization -file $outputDir/clock_util.rpt
-report_timing_summary -file $outputDir/post_place_timing_summary.rpt
-report_timing -file $outputDir/post_place_timing.rpt
-
-# route design and generate bitstream
-route_design -directive Explore
-write_bitstream -force $outputDir/out.bit
-
-report_route_status -file $outputDir/post_route_status.rpt
-report_timing_summary -file $outputDir/post_route_timing_summary.rpt
-report_timing -file $outputDir/post_route_timing.rpt
-report_power -file $outputDir/post_route_power.rpt
-report_drc -file $outputDir/post_imp_drc.rpt
-write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true

examples/verilog/nexys4_ddr/uart_logic_analyzer/.gitignore

@@ -1 +0,0 @@
-!top_level.sv

examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh

@@ -1,6 +0,0 @@
-#!/usr/bin/env bash
-set -e
-
-python3 -m manta gen manta.yaml manta.v
-mkdir -p build/
-$VIVADO -mode batch -source build.tcl

examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh

@@ -0,0 +1 @@
+../../../common/build_vivado.sh

examples/verilog/nexys4_ddr/uart_logic_analyzer/build.tcl

@@ -1,36 +0,0 @@
-#!/usr/bin/tclsh
-
-set partNum xc7a100tcsg324-1
-set outputDir build
-
-read_verilog -sv [ glob *.{sv,v,svh,vh} ]
-read_xdc top_level.xdc
-
-set_part $partNum
-
-# synth
-synth_design -top top_level -part $partNum -verbose
-report_utilization -file $outputDir/post_synth_util.rpt
-report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
-report_timing -file $outputDir/post_synth_timing.rpt
-
-# place
-opt_design
-place_design
-phys_opt_design
-report_utilization -file $outputDir/post_place_util.rpt
-
-report_clock_utilization -file $outputDir/clock_util.rpt
-report_timing_summary -file $outputDir/post_place_timing_summary.rpt
-report_timing -file $outputDir/post_place_timing.rpt
-
-# route design and generate bitstream
-route_design -directive Explore
-write_bitstream -force $outputDir/out.bit
-
-report_route_status -file $outputDir/post_route_status.rpt
-report_timing_summary -file $outputDir/post_route_timing_summary.rpt
-report_timing -file $outputDir/post_route_timing.rpt
-report_power -file $outputDir/post_route_power.rpt
-report_drc -file $outputDir/post_imp_drc.rpt
-write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true