Fischer Moseley
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f8dcf116d5
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docs: autogenerate Python API docs, update IO core docs
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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4f82973135
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meta: sort imports with ruff
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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85bfa3f9ae
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meta: switch from black to ruff
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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b3434cb3c5
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meta: expose Amaranth API via __all__
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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06c4fb496f
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tests: fix mem_core_hw
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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f32167162d
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tests: refactor to use Amaranth-native API
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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b87f8cbc48
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meta: move to lib.io and lib.mem, enable bidirectional mem tests on xilinx
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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71ec1174d1
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add parameterized HW tests for all memory core modes
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2024-03-06 14:53:27 -08:00 |
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Fischer Moseley
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d1a772784a
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add environment.sh for tool paths and serial ports
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2024-03-06 11:26:31 -08:00 |
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Fischer Moseley
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5d5a50042f
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make model tracking automatic in memory core tests
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2024-03-06 01:12:36 -08:00 |
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Fischer Moseley
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b00e4d0e60
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revert wiring.Component instead of Elaboratable
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2024-03-04 01:18:31 -08:00 |
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Fischer Moseley
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f83dc59b4e
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add more MemoryCore tests
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2024-03-04 00:17:36 -08:00 |
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Fischer Moseley
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08adbd8ede
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switch to wiring.Component instead of Elaboratable
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2024-03-03 19:10:06 -08:00 |
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Fischer Moseley
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b729deb144
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hardcode device paths in hardware tests
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2024-03-03 18:31:11 -08:00 |
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Fischer Moseley
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2e2397013e
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make mem_core_hw tests pass
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2024-03-02 14:08:52 -08:00 |
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Fischer Moseley
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6438a55192
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partially revert MemoryCore updates
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2024-03-02 13:31:01 -08:00 |
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Fischer Moseley
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6aea5cc6e1
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update MemoryCore references
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2024-03-02 12:52:04 -08:00 |
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Fischer Moseley
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e2450ddbff
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complete IO core refactor
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2024-02-18 15:50:51 -08:00 |
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Fischer Moseley
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1528f569ef
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update submodule usage, tidy logic analyzer config check
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2024-01-14 12:51:52 -08:00 |
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Fischer Moseley
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7a6ab45b92
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revert UART and InternalBus() refactor
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2024-01-07 21:39:44 -08:00 |
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Fischer Moseley
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bc616fd3bf
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |