Fischer Moseley
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277d561a63
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logic_analyzer: fix missing import
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2024-10-08 07:37:31 -07:00 |
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Fischer Moseley
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40fdb3409a
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logic_analyzer: pass interface when constructing LogicAnalyzerCapture
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2024-10-07 23:14:29 -07:00 |
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Fischer Moseley
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4799d5ce57
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logic_analyzer: tidy some formatting/typos from rebase
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2024-10-07 20:58:18 -07:00 |
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Fischer Moseley
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28b6767e68
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uart: remove flaky nexys4ddr baudrate mismatch test case
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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c683a2e880
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tests: fix test_config_export
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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60da631fa7
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uart: add stall_interval parameter and tests
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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7f36072e90
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logic_analyzer: only set triggers if extra info provided in config
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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758dec80ff
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logic_analyzer: add set_triggers method, simplify trigger validation
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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f7dc5a808c
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logic_analyzer: default to immediate instead of single-shot, add intelligence to to_config()
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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21c18006a6
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docs: wordsmithing
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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4944eeb70b
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doc: reference use cases/examples in index.md
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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90c52030d0
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meta: formatting
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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d86c5f1fe6
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docs: update Ethernet Interface
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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2bfa39896d
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docs: update UART Interface
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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4e73f584b4
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docs: update layout and references for LogicAnalyzerCore docs
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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4d8d7fed4a
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docs: update memory_core
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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f8dcf116d5
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docs: autogenerate Python API docs, update IO core docs
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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f30f74c284
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docs: document amaranth-based flow
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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323d8e0a10
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ethernet: move LiteEth core connections from Signals to IOPorts
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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7dec6f513f
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examples: make verilog/amaranth versions of uart_logic_analyzer match
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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24555a77fc
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tests: fix bug where base_addr was not passed but not used
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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c59132a319
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meta: fix circular imports
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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5164dea212
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docs: condense a few pages
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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4f82973135
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meta: sort imports with ruff
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2024-10-07 20:51:03 -07:00 |
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Fischer Moseley
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85bfa3f9ae
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meta: switch from black to ruff
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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217f85f5fd
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cli: remove JSON loader, add test for instantiation generation
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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3f62be3f8c
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deps: load liteeth from PyPI
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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967918717a
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tests: include building examples in test suite
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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cd91e7d708
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formatting
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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c867e9f8e5
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manta: fix code generation from config file, update tests
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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b3434cb3c5
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meta: expose Amaranth API via __all__
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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d4fc96ddfe
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ethernet: update __init__ away from config dict
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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06c4fb496f
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tests: fix mem_core_hw
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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0254703957
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tests: fix logic_analyzer_sim
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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84b1a4846e
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ci: check formatting with black
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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f32167162d
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tests: refactor to use Amaranth-native API
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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8e07f8e254
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logic analyzer: move __init__ away from config dict
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2024-10-07 20:50:15 -07:00 |
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Fischer Moseley
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3c2b69579d
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meta: add boilerplate for Amaranth-native API
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2024-10-07 18:38:16 -07:00 |
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Fischer Moseley
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3c6ec65511
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uart: update length checking to accomodate extra newlines
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2024-10-07 18:38:16 -07:00 |
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Fischer Moseley
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f907a58041
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add newline every 32 read requests
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2024-10-07 18:38:16 -07:00 |
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Fischer Moseley
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080af6c5ee
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logic_analyzer: find nearest integer timestep in VCD export
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2024-10-07 13:39:39 -06:00 |
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Fischer Moseley
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49e8d340ba
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logic_analyzer: obtain clock frequency in capture_vcd from self
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2024-10-07 13:39:39 -06:00 |
Carlos Azevedo
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ebcb11fdba
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VCD time step is calculated from the frequency of the clock provided to Manta. The value changes are also timed accurately, instead of expressed in 10 ns intervals always.
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2024-10-07 13:39:39 -06:00 |
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Fischer Moseley
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929312181e
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ci: clone entire repo when building docs
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2024-10-06 13:11:32 -06:00 |
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Fischer Moseley
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b998d21810
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ci: do not cache clone between builds
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2024-10-06 13:05:22 -06:00 |
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Fischer Moseley
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6f2a0eab15
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ci: add GitHub Actions user to fix mike deploy
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2024-10-06 13:03:30 -06:00 |
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Fischer Moseley
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ead8a7b5bf
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docs: push to dev instead of latest from main
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2024-10-06 11:42:57 -06:00 |
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Fischer Moseley
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c5bc148a57
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docs: fix old version warning
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2024-10-06 11:34:31 -06:00 |
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Fischer Moseley
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4e93a049cd
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docs: deploy using mike in CI
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2024-10-06 11:25:14 -06:00 |
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Fischer Moseley
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1f8bf643fd
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docs: add mike
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2024-10-06 10:52:23 -06:00 |