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2152 Commits

Author SHA1 Message Date
Matthias Köfferlein ede217cd0b Fixed #302 and plus a potential invalid memory access fixed 2019-07-15 00:17:01 +02:00
Matthias Köfferlein 1a25b19ab1
Merge pull request #266 from KLayout/dvb 
Dvb
 2019-07-14 18:56:59 +02:00
matthias 89ce2be5c2 Merge remote-tracking branch 'origin/master' into dvb 2019-07-14 01:28:11 +02:00
Matthias Köfferlein 1b08656835
Merge pull request #300 from KLayout/issue-264 
Issue 264
 2019-07-14 00:12:58 +02:00
Matthias Köfferlein ea50ff1914
Merge pull request #301 from KLayout/issue-287 
Issue 287
 2019-07-14 00:12:07 +02:00
Matthias Köfferlein 397e86f4b4 Merge branch 'dvb' of https://github.com/klayout/klayout into dvb 2019-07-13 23:39:16 +02:00
Matthias Köfferlein 4172b60d60 Fixed a build issue on Windows. 2019-07-13 23:38:26 +02:00
matthias 8b17a4da4f A few utility functions 
Polygon#is_rectilinear?, Polygon#is_empty?
and same for SimplePolygon
 2019-07-13 22:45:22 +02:00
matthias 5f27341995 Some refactoring, better templates 
1.) tl::Stream now can read from resources
    (:<path> URL's)
2.) LVS/DRC templates are kept as resource,
    "create_template" uses the URL to read them.
3.) Added samples for LVS
4.) Configured LVS to match sample
 2019-07-13 18:40:00 +02:00
matthias ebca5e1ce6 Bugfix: small LVS and DRC macro iessues (LVS and DRC menus not working etc.) 2019-07-13 17:00:05 +02:00
Matthias Koefferlein 1251fb2cd6 Added < and > to allowed chars for net names in Spice reader 2019-07-13 08:50:13 +02:00
Matthias Koefferlein 2d57a11f8c Fixed #287 (RecursiveShapeIterator to ObjectInstPath) 
There is a new constructor for ObjectInstPath to
create one from a RecursiveShapeIterator.
 2019-07-12 23:13:50 +02:00
Matthias Koefferlein e8ff8156a0 fix for #264 
1. Errors in coerce_parameters are now shown as
   red label + warning icon in the parameters dialog
2. Errors during produce are always logged now

Plus: the scroll bars of the PCell parameters page
don't jump back on "Apply".
 2019-07-12 21:13:18 +02:00
Matthias Koefferlein a9e1af0a1b Updated tests 2019-07-12 20:06:35 +02:00
Matthias Koefferlein c7e883cdb2 SPICE reader now assigned net names as pin names. 2019-07-12 19:00:27 +02:00
Matthias Koefferlein f66b094e88 Merge branch 'dvb' into dvb_test 2019-07-12 17:44:11 +02:00
Matthias Koefferlein a47190f3ab Write short versions of LVS and L2N DB by default. 2019-07-12 17:43:43 +02:00
Matthias Koefferlein 85717beca6 Allow saving LVS DB files from netlist browser. 2019-07-12 17:29:44 +02:00
Matthias Koefferlein ca6d05d3c1 Updated tests 2019-07-12 00:22:45 +02:00
Matthias Koefferlein d109a22cf5 Renaming (distro nodes->virtual nodes) 2019-07-11 23:20:42 +02:00
Matthias Koefferlein e32ee570c7 Alternative algorithm for subcircuit matching - tests updated, refactoring 2019-07-11 23:19:02 +02:00
Matthias Koefferlein 7bc4acd8f6 WIP: new version of subcircuit match algorithm - needs refactoring. 2019-07-11 23:14:53 +02:00
Matthias Koefferlein 0d9273aaf6 WIP: new subcircuit match algorithm 2019-07-11 00:16:36 +02:00
Matthias Koefferlein 2f01c7a0bd WIP: other algorithm for handling subcircuits in netlist compare 2019-07-10 23:40:16 +02:00
Matthias Koefferlein 67f786035c WIP: during refactoring 2019-07-10 00:32:53 +02:00
Matthias Koefferlein 1fd069ca99 Provide a better description for net mismatch with warning. 2019-07-09 20:29:35 +02:00
Matthias Koefferlein 1e3d62ca3a Provide bulk label for blackboxed cells 2019-07-09 20:23:47 +02:00
Matthias Koefferlein cef96902ad Boundary for circuits, reverted automatic generation of global pins 
- global pins have been generated for device cells too and lead
  to implicit pins which may not be desired. The original problem
  was how to make abstract circuits comparable. This has to be
  solved differently.
- Circuit boundaries are good for displaying the boxes for
  abstract circuits
 2019-07-09 19:55:48 +02:00
Matthias Koefferlein 0c6ead6f90 WIP: introduced boundary into L2N format so we have something to display for abstracts. 2019-07-09 01:18:23 +02:00
Matthias Koefferlein c9e08c4500 WIP: propagate global nets to parent hierarchy even if there is no shape inside the cell. 2019-07-08 23:11:35 +02:00
Matthias Koefferlein bdb8a7bcc2 WIP: reverted modifications on SPICE reader. 2019-07-08 21:51:59 +02:00
Matthias Koefferlein 9625caea65 WIP: added full LVS test. 2019-07-08 21:43:06 +02:00
Matthias Koefferlein b48453633f WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
Matthias Koefferlein bc2d9448d6 Providing LVS tests. 2019-07-07 21:33:28 +02:00
Matthias Koefferlein 95a1e38fe3 WIP: better reproducablility for .lvsdb layer names, updated tests. 2019-07-07 19:39:00 +02:00
Matthias Koefferlein 993ef78575 WIP: some cleanup/enhancement 
General topic: abstracts and swappable pins.
Issue: we work bottom up and assign pins. This is the
basis for net graph building. But swappable means those
pins can change. The compare works fine, but debugging
output is strange: as the pin assigned is fixed, the nets
found to be attached to a circuit might not fit any
proposed pin pair (which does not contain swapping).

The problem gets worse with abstracts.

The enhancements are
- Such cases generate only warnings in the browser
  and the message says swapping might be the case
- Floating nets are treated differently. This should
  lead to a better performance for abstracts/black boxes,
  but in case of disconnected pins (due to wire errors),
  floating nets happen to create mismatches in the nets above.
- Net graph building does not consider swappable nets. In
  case of two swappable pins this wouldn't be an issue, but
  for more than two this would create ambiguities and
  prevent topological matching.

Plus: Debug output option for net graph

Tests updated
 2019-07-07 18:17:14 +02:00
Matthias Koefferlein ace0788f85 WIP: Spice reader reads pin names from nets 2019-07-07 00:05:22 +02:00
Matthias Koefferlein 0e5ecdc36b Attempt to make LVS compare output a little more predictable with boundary cases 
- For unattached subcircuit pins no error should be reported
- For abstract nets, graph propagation through subcircuit pins isn't attempted.
  Abstract nets are only dummy-associated currently.
 2019-07-06 23:40:49 +02:00
Matthias Koefferlein 903b1f7505 WIP: fixed 'equivalent_pins' 2019-07-06 21:47:25 +02:00
Matthias Koefferlein 5ce8dd2684 WIP: added circuit blankout. 2019-07-06 19:50:20 +02:00
Matthias Koefferlein fb8a64b0e1 WIP: updated LVS doc. 2019-07-06 09:37:54 +02:00
Matthias Koefferlein 24a0c3dd00 LVS template for macros. Enhancement: 'schematic' statement can now be anywhere in LVS script. 2019-07-06 09:35:51 +02:00
Matthias Koefferlein a179705a03 WIP: more refactoring. 2019-07-06 09:15:33 +02:00
Matthias Koefferlein 0595ec2e0f WIP: one more test for LVS 2019-07-06 09:08:32 +02:00
Matthias Koefferlein 2f6aae7204 WIP: refactoring, added first tests for LVS 2019-07-06 08:52:40 +02:00
Matthias Koefferlein 15022709b4 WIP: doc update, robustness of LVS browser model (xref) 2019-07-05 23:35:14 +02:00
Matthias Koefferlein a6a0d9946c Updated documentation 2019-07-05 21:45:50 +02:00
Matthias Koefferlein fade779238 WIP: doc update. 2019-07-05 17:48:23 +02:00
Matthias Koefferlein 153bfa9c52 Updated doc. 2019-07-04 23:56:04 +02:00
Matthias Koefferlein 68f98d9f0d Some typos fixed, connect_implicit now can be used multiple times (but without glob pattern) 2019-07-04 23:55:46 +02:00