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403 Commits

Author SHA1 Message Date
Matthias Koefferlein 834dcc7474 WIP: LVSDB reader/writer fixes 2019-05-19 23:42:31 +02:00
Matthias Koefferlein ea8320dcf8 WIP: LVSDB reader/writer: bugfixes, refactoring, tests. 2019-05-19 22:55:03 +02:00
Matthias Koefferlein f72790e808 WIP: glob pattern - GSI binding to enable compatible implementations. 2019-05-11 22:35:50 +02:00
Matthias Koefferlein 0f0dd42b4d Refactoring and GSI binding for combined device interface. 2019-05-10 18:32:05 +02:00
Matthias Koefferlein ea28530c55 L2N: combined device persistance (complex concept - needs simplification?) 2019-05-10 00:15:51 +02:00
Matthias Koefferlein 8aeab5f131 Provide alternative golden data to make test pass on CentOS 7 (different hasher?) 2019-05-07 20:55:23 +02:00
Matthias Koefferlein 90ef5f9c2e Added missing files 2019-05-06 19:01:34 +02:00
Matthias Koefferlein 30fdb0089b Integration of netlist extractor with net tracer plugin (-> "trace all nets") 2019-05-05 22:30:07 +02:00
Matthias Koefferlein c33fd40ec9 Switched l2n format to relative mode by default (relative mode is an option and maybe shorter) 2019-05-04 23:06:18 +02:00
Matthias Koefferlein 548f16f1df WIP: tried to provide a more consistent net building feature (here: building hierarchical nets with properties as net annotation - needs cell variants if properties are assigned to subcells too) 2019-05-04 00:37:38 +02:00
Matthias Koefferlein 2aaec56adb WIP: netlist browser - extended the net export scheme of build_net to support net annotation and flattening. 2019-05-03 23:33:37 +02:00
Matthias Koefferlein e661bac0a7 Netlist browser: fixed a segfault on 'unload all' 2019-04-28 22:57:06 +02:00
Matthias Koefferlein 7f9da5e8de Introduced concept of device class templates 
This concept allows to persist at least the standard
(built-in) device classes into L2N DB files. This way
device classes are persisted.
 2019-04-23 19:44:07 +02:00
Matthias Koefferlein 8121f70e65 Netlist compare: Net mismatches reported if nets don't match but we still will proceed 2019-04-18 00:01:21 +02:00
Matthias Koefferlein 213a6f306b More robust unit tests. 2019-04-17 22:16:57 +02:00
Matthias Koefferlein 66eabe9aec Test data normalization for netlist writer test (Ruby) 2019-04-17 22:05:51 +02:00
Matthias Koefferlein 3de4a8408e Merge remote-tracking branch 'origin/dvb' 2019-04-16 18:55:37 +02:00
Matthias Koefferlein 86f05456b8 Fixed pya:qtbinding test 2019-04-16 07:07:19 +02:00
Matthias Koefferlein eabf558186 netlist exaction: selective net joining with labels 
Now, a glob pattern can be used to identify the labels
which implicitly join nets. Also, net joining now
only happens on top level.
 2019-04-15 23:24:27 +02:00
Matthias Koefferlein 92524dcf57 WIP: netlist compare - bugfixed latest version and updated tests. 2019-04-13 19:56:08 +02:00
Matthias Koefferlein e855d8df35 WIP: fixed unit tests. 2019-04-12 00:31:48 +02:00
Matthias Koefferlein 648aa9e077 WIP: fixed unit tests. 2019-04-12 00:23:45 +02:00
Matthias Koefferlein f34d161e2f WIP: new backtracking algorithm for net matching. 2019-04-09 23:13:40 +02:00
Matthias Koefferlein 2e9422a753 Netlist compare: a little less freedom when picking derived net pairs ... 2019-04-08 21:32:41 +02:00
Matthias Koefferlein 7cdd40dabb Netlist compare: more detailed derivation of net assignments from known nets (pairing by deduction) 2019-04-08 21:21:34 +02:00
Matthias Koefferlein f6836b96a2 WIP: some enhancements 
Spice writer: don't prefix model name with "M"
Added "device_class_mismatch" message to netlist compare
Assertion if device classes or circuits are nil on
"same_..."
 2019-04-07 10:15:57 +02:00
Matthias Koefferlein df2bd5e80a Netlist: flatten subcircuits, circuits 2019-04-06 23:36:08 +02:00
Matthias Koefferlein aad52b77ba Netlist compare: added the ability to filter small caps and high resistance devices 2019-04-06 19:46:13 +02:00
Matthias Koefferlein da5680ef24 Netlist compare: configurable device parameter compare scheme. 2019-04-06 15:19:43 +02:00
Matthias Koefferlein 43f65e4d29 Added tests for GSI binding of dbNetlistCompare 2019-04-06 00:18:37 +02:00
Matthias Koefferlein 52fb8b0f65 Merge remote-tracking branch 'remotes/origin/master' into dvb 2019-04-04 07:35:43 +02:00
Ruben Undheim d287b6958b A few more spelling fixes 2019-04-03 08:23:27 +02:00
Matthias Koefferlein 89ffd7e3da WIP: Simple SPICE reader. 2019-04-01 22:46:33 +02:00
Matthias Koefferlein 9613ad72c8 WIP: netlist compare - using it for more tests 
Issue solved: some circuit pins may not have a net - these
need to be ignored.

Requirement: all pins with a net must be mapped.

Detached pins are not present in the mapping table.
A dummy mapping table was introduced to allow dropping
of pins in the second circuit too.

Output of compare should not depend on memory location
anymore and pin mismatch reporting should include all
pins.
 2019-03-31 23:59:43 +02:00
Ruben Undheim 5d26cf4c77 Spelling errors in code and comments fixed 2019-03-31 15:25:18 +00:00
Matthias Koefferlein d255617051 WIP: netlist compare - tests for device class equivalence mapping, added Netlist#device_class_by_name 2019-03-28 18:01:22 +01:00
Matthias Koefferlein 0003c38918 Netlist normalization for unit tests also for RBA test. 2019-03-23 09:29:37 +01:00
Matthias Koefferlein e545d6af3f Refined solution for issue-245 by providing a better name mapping (checked with ngspice) 2019-03-22 00:05:17 +01:00
Matthias Koefferlein 9356f32026 Fixed issue-245 (support Spice netlist with names instead of numbers) 
The option is in the Spice writer (writer.use_net_names=true).
 2019-03-21 23:34:16 +01:00
Matthias Koefferlein 2d4f23abd1 Updated tests. 2019-03-19 00:08:47 +01:00
Matthias Koefferlein 41fdd74189 Custom devices for device extractor - tests in the DRC framework 2019-03-10 22:37:32 +01:00
Matthias Koefferlein 510c675d21 Test cases for DRC-based net extraction and flat extraction 
Flat extraction requires that texts of subcells are not
considered. Otherwise they pollute the net namespace of
the top cell.
 2019-03-10 19:35:13 +01:00
Matthias Koefferlein ab8107de2d Bugfix: Spice writer needs 'P' suffix for source/drain area of MOS 2019-03-10 01:26:52 +01:00
Matthias Koefferlein 6932977273 A few bug fixes and test updates 
- edge pairs are normalized before turning them into polygons.
  This makes flat and deep implementation more consistent.
- deep region and flat regions were not cooperating in geo
  checks
- unnamed layers are not registered in make_layer - this
  does not make sense and will just hold a fake ref
- tests now use GDS to represent texts after transformation
  (with orientation, OASIS can't do this)
- texts are more consistently handled in the tests
- test debug output is not written in the same format
  than golden data unless special normalization is
  requested.
- a non-orientable polygon was converted to orientable in
  a text because this can be represented in GDS consistently
- DRC testsuite uses "polygons" instead of "input" to achieve
  identical behavior for deep and flat mode with respect to
  texts
- dbRegionTests are updated because texts are not allowed
  for non-original layers too
 2019-03-09 19:40:38 +01:00
Matthias Koefferlein 745696507f Two bug fixes in DRC related to flatten: 
- Merge semantics wasn't transferred to flat region
- Merge semantics wasn't set at all in deep region
 2019-03-09 09:59:23 +01:00
Matthias Koefferlein b30a9278d6 WIP: updated test cases. 2019-03-06 07:41:44 +01:00
Matthias Koefferlein 1b450c6499 Added missing file. 2019-03-06 00:36:05 +01:00
Matthias Koefferlein 8b29b30ff9 WIP: more consistent text handling 
Texts are not only kept inside original layers, but
also inside deep layers. This enables using texts
from DRC.

However, texts in deep layers are kept as markers.
Mostly they are converted back to texts, but the
orientation will be lost.

The change eliminates the need to using Iterators
in DRC instead of original layers and use of
label layers in deep mode.

A drawback is the presence of marker shapes in
deep mode (unless polygon layers are created).
Also, text output to RDB is not supported from
deep layers currently.
 2019-03-06 00:34:56 +01:00
Matthias Koefferlein bacd565d05 Bugfix: Spice writer added one pin too much to MOS4 transistors. 2019-03-04 17:26:35 +01:00
Matthias Koefferlein 9c75ee8c92 Added DRC tests for antenna check. 2019-03-02 11:23:40 +01:00
Matthias Koefferlein 261fb027fd GSI binding of antenna check function + tests. 2019-03-02 00:38:51 +01:00
Matthias Koefferlein 8d3b94201e Antenna check: tests added, 'catchall' diode protection 2019-03-01 23:07:28 +01:00
Matthias Koefferlein 9f4f2d58d7 First version of antenna check. 2019-02-28 23:56:49 +01:00
Matthias Koefferlein fccdee5186 WIP: provisions for DRC/network extractor integration. 2019-02-28 00:55:06 +01:00
Matthias Koefferlein d4ed21f42a Just new tests 2019-02-25 22:34:06 +01:00
Matthias Koefferlein 3c6aafcc0c Region: hierarchical text object detection implementated. 2019-02-23 00:56:55 +01:00
Matthias Koefferlein c7b17fb65a Merged master into dvb branch 2019-02-22 23:16:44 +01:00
Matthias Koefferlein 792de1e0e9 'break' function for regions (split polygons into pieces if required) 2019-02-22 23:10:26 +01:00
Matthias Koefferlein 18f74bac1e Enabled transformations for deep regions/edges/edge pairs - important for handling layouts with different DBUs in DRC 2019-02-22 01:02:48 +01:00
Matthias Koefferlein 91407ddaa9 Added tests for region processors. 2019-02-20 21:40:43 +01:00
Matthias Koefferlein 496b695ef0 Refactoring of the polygon processing in Region 2019-02-19 22:11:55 +01:00
Matthias Koefferlein 0111b3916c Included a test for DRC's 'flatten' method 2019-02-18 23:51:39 +01:00
Matthias Koefferlein 7f71cc3a56 Some bug fixes, added tests for hier DRC (at least for what is there yet) 2019-02-18 22:24:34 +01:00
Matthias Koefferlein 9ec6b44c93 Added some tests for the previous commit. 2019-02-18 00:15:26 +01:00
Matthias Koefferlein b91edbabde Enabled deep mode for DRC 2019-02-17 23:21:23 +01:00
Matthias Koefferlein 311318c578 Ported edge/edge DRC functions to hierarchical mode. 2019-02-17 18:54:33 +01:00
Matthias Koefferlein c40f147dc7 Edge/edge and edge/polygon interaction test ported to hierarchical mode. 2019-02-17 18:36:15 +01:00
Matthias Koefferlein 7ef0451ca8 Partial segments of edges converted to hierarchical operations. 2019-02-17 17:53:21 +01:00
Matthias Koefferlein 74006b6208 Hierarchical implementation of extended method for edges 2019-02-17 17:34:31 +01:00
Matthias Koefferlein ae783a2245 Hiearchical implementation of edge filter. 2019-02-17 16:18:24 +01:00
Matthias Koefferlein 61d766bd4c Hierarchical implementation of edge to region operations. 2019-02-17 16:05:39 +01:00
Matthias Koefferlein e6ee1c064e Hierarchical implementation of edge/edge booleans. 2019-02-17 15:07:16 +01:00
Matthias Koefferlein 8e5bffcf18 Hierarchical angle check. 2019-02-17 11:42:30 +01:00
Matthias Koefferlein a7bfaac424 Cell variant resolution by propagation, grid check now implementation hierarchically (with propagation) 2019-02-17 10:59:04 +01:00
Matthias Koefferlein 6e35e80963 Hierarchical implementation of polygon vs. edge interact 2019-02-15 23:43:45 +01:00
Matthias Koefferlein 78617930dd Hierarchical implementation of self-overlap merge. 2019-02-13 22:41:12 +01:00
Matthias Koefferlein ddcfda8761 Some optimization: keep merged state in deep region. 2019-02-13 17:17:03 +01:00
Matthias Koefferlein 68947bedd2 Updated golden test data. 2019-02-13 01:11:15 +01:00
Matthias Koefferlein b0fc2be96e Deep regions: some more operations implemented hierarchically 
- snap (!) - but only for gx == gy
- filtering
- interact/inside/outside/overlap + not_... variants
- edges
 2019-02-13 01:07:32 +01:00
Matthias Koefferlein 7404ad8f3a WIP: added a comment. 2019-02-12 00:10:52 +01:00
Matthias Koefferlein 6404ca6b1d WIP: Deep edge pairs 2019-02-12 00:08:47 +01:00
Matthias Koefferlein 82ad528dbe Added one more testcase for inserting a plain region into a RDB 2019-02-11 19:24:24 +01:00
Matthias Koefferlein 43014d6923 WIP: some testing and bug fixes for hierarchical report db generation. 2019-02-11 00:22:19 +01:00
Matthias Koefferlein 2d9a3aaaa6 WIP: Hierarchical production of error db's. Needs testing. 2019-02-11 00:11:03 +01:00
Matthias Koefferlein d35e86e189 Updated tests after last change (edge transformation behaviour) 2019-02-10 16:21:44 +01:00
Matthias Koefferlein a81a8cdbc8 Modified edge transformation to maintain the orientation paradigm 
When the transformation is mirroring, edges now swap their
points to maintain the right-is-inside paradigm.
 2019-02-10 16:03:46 +01:00
Matthias Koefferlein 4abc38a5cc Test for deep/flat collaboration 2019-02-10 08:28:48 +01:00
Matthias Koefferlein e8e45b7272 Some tests, smooth and round method of deep region 2019-02-09 23:51:35 +01:00
Matthias Koefferlein 404f0f8328 Added a missing test golden data. 2019-02-09 22:56:44 +01:00
Matthias Koefferlein b6dd149f53 Changed variant suffix to to be consistent with cell name suffix generation in KLayout. 2019-02-09 19:21:14 +01:00
Matthias Koefferlein 1f3af7bbfe Hierarchical area and perimeter and sizing 
Area and perimeter computation happens hierarchically
now. Magnified instances are supported.

Sizing is implemented hierarchically.

For anisotropic sizing, orientation variants may be
generated. For both isotropic and anisotropic
magnification variants will be created.
 2019-02-09 19:13:54 +01:00
Matthias Koefferlein bbf7b2768b WIP: cell variant collecting and building. 2019-02-09 16:29:34 +01:00
Matthias Koefferlein ac7baf96ff Added golden data for deep region regression test. 2019-02-07 21:08:52 +01:00
Matthias Koefferlein decc5ede13 Robustification of Region 
- Tests for merge
- Locking the layout when writing back the data for
  performance improvement
 2019-02-05 23:39:31 +01:00
Matthias Koefferlein 9c0123df20 Implemented implicit joining of nets with the same label. 2019-02-03 21:34:23 +01:00
Matthias Koefferlein 3f1cd226a5 Made net name optional in l2n format. 2019-02-03 13:33:58 +01:00
Matthias Koefferlein f9c33733b9 l2n format writer and reader: more compact output 2019-02-03 01:49:48 +01:00
Matthias Koefferlein 99f111fe01 Attempt to achieve reproducibility between MSVC and gcc 
Applies to dbHierProcessor.cc:

The issue was related to std::unordered_set/map which
(as the name says) is not ordered. The output of the
boolean core computation step is currently dependent
on the order (it's single pass), hence the order of
the contexts matters.

Using ordered sets where possible and explicit
sorting might help.
 2019-02-02 22:43:42 +01:00
Matthias Koefferlein c90f7e4af9 Introduced perimeter parameters for MOS3/MOS4 2019-02-02 01:29:28 +01:00
Matthias Koefferlein 57305977a4 Spice writer delegate fix 
- Changed to const & objects in the Spice writer delegate
  to non-const & for Ruby/Python reimplementation (as const/non-const
  ambiguity is an issue for Ruby/Python we cannot efficiently
  work with const refs)
- Updated test data because the previous implementation wasn't
  using refs but rather copies of device and device class
  objects.
 2019-01-31 22:23:58 +01:00
Matthias Koefferlein 30e26c4f96 Avoid an issue with virtual functions 
Reimplementing virtual functions with
"const &" arguments wasn't behaving as
expected because these arguments were
copied.

Now, "const &" for arguments (in virtual
function reimplementation) is not implemented
as a copy.

In addition, now it's possible to declare
results as references always (also if const &).

See gsiTest.cc:1078 for example:

  //  gsi::arg_make_reference makes the function's return value
  //  always being taken as a reference
  gsi::method<C_P, const CopyDetector &, const CopyDetector &, gsi::arg_make_reference> ("pass_cd_cref_as_ref", &C_P::pass_cd_cref)
 2019-01-31 01:07:15 +01:00
Matthias Koefferlein 7b07782cdf Avoid an issue with virtual functions 
Reimplementing virtual functions with
"const &" arguments wasn't behaving as
expected because these arguments were
copied.

Now, "const &" for arguments (in virtual
function reimplementation) is not implemented
as a copy.

In addition, now it's possible to declare
results as references always (also if const &).

See gsiTest.cc:1078 for example:

  //  gsi::arg_make_reference makes the function's return value
  //  always being taken as a reference
  gsi::method<C_P, const CopyDetector &, const CopyDetector &, gsi::arg_make_reference> ("pass_cd_cref_as_ref", &C_P::pass_cd_cref)
 2019-01-31 00:36:44 +01:00
Matthias Koefferlein 4068478887 Implemented SPICE writer + tests. 2019-01-31 00:07:10 +01:00
Matthias Koefferlein 4712ee0f29 Activated DeviceAbstract for GSI. 2019-01-25 22:40:41 +01:00
Matthias Koefferlein 29264013b0 WIP: more consistent handling of polygon splitting parameters. 2019-01-25 22:28:25 +01:00
Matthias Koefferlein 6da9bc5e85 Updated tests after switching to boolean core. 2019-01-25 21:38:45 +01:00
Matthias Koefferlein f83e1dae43 Refactoring, some bugfixes, GSI bindings for L2N methods. 2019-01-20 23:12:27 +01:00
Matthias Koefferlein 4c7f43d749 More l2n reader tests. 2019-01-20 17:31:58 +01:00
Matthias Koefferlein dd39168dc8 WIP: Enabled layout generation from read l2n data. 2019-01-20 02:50:23 +01:00
Matthias Koefferlein a5e2cf58c3 l2n dump format is leaner (device terminal shapes dropped from nets as they are contained in the device abstracts). Some refactoring. 2019-01-19 23:00:19 +01:00
Matthias Koefferlein 8213e71a79 WIP: l2n reader implementation, some bug fixes, refactoring. 2019-01-19 22:19:08 +01:00
Matthias Koefferlein 56bb39a273 LayoutToNetlist enhancements in the area of the dumper. 2019-01-16 22:45:58 +01:00
Matthias Koefferlein 5962d66940 WIP: major enhancements with respect to device handling 
The device handling in the netlist extractor was now
entirely moved to device cells. New options are introduced
for exporting these cells. Tests have been updated.
 2019-01-15 21:33:41 +01:00
Matthias Koefferlein 1af81b74d2 WIP: refactoring - turning devices into cells for better backannotation. 2019-01-14 00:59:47 +01:00
Matthias Koefferlein aeeb6d7c87 Fixed #200 by introducing layout locking during iteration 
The cause for the problem was that the layout got updated
while iterating causing the mess within the iterator.

This solution is to lock the layout while an iterator
is present. This happens for various Cell and Shapes
iterator, so it's a major enhancement.
 2019-01-09 01:06:11 +01:00
Matthias Koefferlein 9fa5618034 Added test for device combination. 2019-01-08 23:49:12 +01:00
Matthias Koefferlein d4d7ea8022 Updated copyright. 2019-01-08 01:09:25 +01:00
Matthias Koefferlein b0d7f5f7f5 Updated copyright. 2019-01-08 00:58:45 +01:00
Matthias Koefferlein feb2b69aa9 Merge remote-tracking branch 'origin/master' into dvb 2019-01-08 00:49:16 +01:00
Matthias Koefferlein fb4048d317 Added RBA tests for four-terminal MOS extraction plus global nets. 2019-01-08 00:17:58 +01:00
Matthias Koefferlein 294f1701b5 Added a test for joining of layers through multiple global net assignment. 2019-01-07 23:57:52 +01:00
Matthias Koefferlein 315bcdd016 WIP: bugfixed netlist extractor with global nets. 2019-01-07 23:33:57 +01:00
Matthias Koefferlein c80e335cd6 WIP: global nets integration in cluster builder. 2019-01-07 02:08:59 +01:00
Matthias Koefferlein a4f0fd665e Provided a solution for connectivity through global nets. 2019-01-06 17:50:51 +01:00
Matthias Koefferlein 64c2548ab8 WIP: first steps towards global nets. 2019-01-06 15:28:40 +01:00
Matthias Koefferlein eb435d5d85 WIP: refactoring - separated pins of net into outgoing and subcircuit. 2019-01-06 12:53:22 +01:00
Matthias Koefferlein 261b14a260 WIP: GSI binding of LayoutToNetlist::build_nets 2019-01-06 02:15:04 +01:00
Matthias Koefferlein 8d51d1e4bb WIP: better optimization of hierarchical net output. 2019-01-06 01:54:36 +01:00
Matthias Koefferlein ec3a3b0f8c WIP: added ability to export nets to layouts. 2019-01-06 01:32:20 +01:00
Matthias Koefferlein bc4f9efa5d One more test for probing with a slightly more complex hierarchy. 2019-01-05 23:21:37 +01:00
Matthias Koefferlein f86f8149eb Fixed a bug that caused a segfault in the Layout2Netlist object (array repo references to original layout rather than to the working layout) 2019-01-05 22:40:53 +01:00
Matthias Koefferlein 6e468b43e0 WIP: bugfix - local to instance interaction did shortcut too early. 2019-01-05 10:12:55 +01:00
Matthias Koefferlein c31c87916c WIP: bugfix - array reference were not always considered correctly. 2019-01-05 01:34:10 +01:00
Matthias Koefferlein ad6d9b5715 WIP: provide a less memory intensive way to deliver shapes from nets. 2019-01-04 17:41:09 +01:00
Matthias Koefferlein 3fd99407a3 WIP: bugfix - hierarchical net extractor wasn't considering self-interactions between instance array elements. 2019-01-03 23:25:28 +01:00
Matthias Koefferlein 62d9941c4a WIP: Bugfix - hierarchy was dropping instances. 2019-01-03 22:09:19 +01:00
Matthias Koefferlein e3b8d3635c Small bugfix: object._destroy wasn't working for directly passed objects. 2019-01-02 23:18:14 +01:00
Matthias Koefferlein 9c607d7663 Added a first version of the layout to netlist extraction feature 
The main entry point is RBA::LayoutToNetlist which is the
GSI binding for the layout to netlist extractor. For a first
impression about the abilities of this extractor see the
Ruby tests in testdata/ruby/dbLayoutToNetlist.rb.

The framework itself consists of many classes, specifically

- RBA::Netlist for the netlist representation
- RBA::DeviceClass and superclasses (e.g. RBA::DeviceClassResistor and
  RBA::DeviceClassMOS3Transistor) for the description of devices.
- RBA::DeviceExtractor and superclasses (i.e. RBA::DeviceExtractorMOS3Transistor or
  the generic RBA::GenericDeviceExtractor) for the implementation of the
  device extraction.
- RBA::Connectivity for the description of inter- and intra-layer connections.
 2018-12-30 22:43:56 +01:00
Matthias Koefferlein f989a85642 WIP: introduced Circuit::is_external_net 2018-12-30 18:44:30 +01:00
Matthias Koefferlein 72a140957d WIP: added test for recursive net shape retrieval 2018-12-30 18:22:45 +01:00
Matthias Koefferlein a787204e77 WIP: connect and disconnect terminal by name in GSI 2018-12-30 13:28:11 +01:00
Matthias Koefferlein 293c6f496e WIP: more query functions for netlist classes (i.e. net by name, device by name etc.), some refactoring, GSI bindings, tests. 2018-12-30 13:00:03 +01:00
Matthias Koefferlein c571535e55 WIP: standard device classes, added GSI binding plus tests. 2018-12-29 23:48:31 +01:00
Matthias Koefferlein 45b35f3aae WIP: to_string for netlist, tests, some bugfixes on device combination. 2018-12-29 22:18:58 +01:00
Matthias Koefferlein d57ede441c WIP: netlist topology - children, parents, top-down and bottom-up iteration. 2018-12-29 00:48:28 +01:00
Matthias Koefferlein 2f48479838 WIP: a bit of simplification, renaming of methods, parents for subcircuits, devices. References for circuits pointing to subcircuits. 2018-12-28 22:51:11 +01:00
Matthias Koefferlein 8b2902c31b WIP: introduced expanded net name 2018-12-27 10:43:25 +01:00
Matthias Koefferlein f0f620b1cd WIP: added subcircuit IDs for easier referencing. 2018-12-27 01:58:34 +01:00
Matthias Koefferlein 62ffcd38e6 WIP: refactoring of the netlist property thing. Now it's internal and there is only the device terminal property. The property also does not store device pointers but just IDs 2018-12-27 01:27:58 +01:00
Matthias Koefferlein 2171b98bd8 WIP: introduced device IDs 2018-12-27 00:59:44 +01:00