mirror of https://github.com/KLayout/klayout.git
WIP: netlist topology - children, parents, top-down and bottom-up iteration.
This commit is contained in:
Matthias Koefferlein
parent
2f48479838
commit
d57ede441c
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@ -504,13 +504,13 @@ void Net::set_circuit (Circuit *circuit)
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// Circuit class implementation
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Circuit::Circuit ()
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: mp_netlist (0), m_valid_device_id_table (false), m_valid_subcircuit_id_table (false)
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: mp_netlist (0), m_valid_device_id_table (false), m_valid_subcircuit_id_table (false), m_index (0)
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{
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// .. nothing yet ..
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}
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Circuit::Circuit (const Circuit &other)
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: mp_netlist (0), m_valid_device_id_table (false), m_valid_subcircuit_id_table (false)
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: mp_netlist (0), m_valid_device_id_table (false), m_valid_subcircuit_id_table (false), m_index (0)
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{
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operator= (other);
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}
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@ -609,6 +609,54 @@ void Circuit::set_cell_index (const db::cell_index_type ci)
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m_cell_index = ci;
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}
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Circuit::child_circuit_iterator Circuit::begin_children ()
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{
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tl_assert (mp_netlist != 0);
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return mp_netlist->child_circuits (this).begin ();
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}
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Circuit::child_circuit_iterator Circuit::end_children ()
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{
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tl_assert (mp_netlist != 0);
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return mp_netlist->child_circuits (this).end ();
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}
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Circuit::const_child_circuit_iterator Circuit::begin_children () const
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{
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tl_assert (mp_netlist != 0);
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return reinterpret_cast<const tl::vector<const Circuit *> &> (mp_netlist->child_circuits (const_cast <Circuit *> (this))).begin ();
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}
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Circuit::const_child_circuit_iterator Circuit::end_children () const
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{
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tl_assert (mp_netlist != 0);
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return reinterpret_cast<const tl::vector<const Circuit *> &> (mp_netlist->child_circuits (const_cast <Circuit *> (this))).end ();
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}
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Circuit::child_circuit_iterator Circuit::begin_parents ()
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{
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tl_assert (mp_netlist != 0);
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return mp_netlist->parent_circuits (this).begin ();
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}
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Circuit::child_circuit_iterator Circuit::end_parents ()
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{
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tl_assert (mp_netlist != 0);
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return mp_netlist->parent_circuits (this).end ();
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}
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Circuit::const_child_circuit_iterator Circuit::begin_parents () const
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{
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tl_assert (mp_netlist != 0);
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return reinterpret_cast<const tl::vector<const Circuit *> &> (mp_netlist->parent_circuits (const_cast <Circuit *> (this))).begin ();
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}
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Circuit::const_child_circuit_iterator Circuit::end_parents () const
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{
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tl_assert (mp_netlist != 0);
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return reinterpret_cast<const tl::vector<const Circuit *> &> (mp_netlist->parent_circuits (const_cast <Circuit *> (this))).end ();
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}
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const Pin &Circuit::add_pin (const Pin &pin)
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{
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m_pins.push_back (pin);
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@ -687,12 +735,20 @@ void Circuit::add_subcircuit (SubCircuit *subcircuit)
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m_subcircuits.push_back (subcircuit);
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invalidate_subcircuit_id_table ();
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if (mp_netlist) {
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mp_netlist->invalidate_topology ();
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}
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}
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void Circuit::remove_subcircuit (SubCircuit *subcircuit)
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{
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m_subcircuits.erase (subcircuit);
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invalidate_subcircuit_id_table ();
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if (mp_netlist) {
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mp_netlist->invalidate_topology ();
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}
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}
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void Circuit::validate_subcircuit_id_table ()
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@ -1073,21 +1129,25 @@ size_t DeviceClass::terminal_id_for_name (const std::string &name) const
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// Netlist class implementation
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Netlist::Netlist ()
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: m_valid_topology (false)
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{
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// .. nothing yet ..
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m_circuits.changed ().add (this, &Netlist::invalidate_topology);
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}
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Netlist::Netlist (const Netlist &other)
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: m_valid_topology (false)
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{
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operator= (other);
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m_circuits.changed ().add (this, &Netlist::invalidate_topology);
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}
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Netlist &Netlist::operator= (const Netlist &other)
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{
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if (this != &other) {
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clear ();
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std::map<const DeviceClass *, DeviceClass *> dct;
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m_device_classes.clear ();
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for (const_device_class_iterator dc = other.begin_device_classes (); dc != other.end_device_classes (); ++dc) {
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DeviceClass *dc_new = dc->clone ();
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dct [dc.operator-> ()] = dc_new;
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@ -1110,6 +1170,223 @@ Netlist &Netlist::operator= (const Netlist &other)
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return *this;
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}
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void Netlist::invalidate_topology ()
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{
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if (m_valid_topology) {
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m_valid_topology = false;
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m_top_circuits = 0;
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m_top_down_circuits.clear ();
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m_child_circuits.clear ();
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m_parent_circuits.clear ();
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}
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}
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namespace {
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struct sort_by_index
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{
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bool operator () (const Circuit *a, const Circuit *b) const
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{
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return a->index () < b->index ();
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}
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};
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}
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void Netlist::validate_topology ()
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{
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if (m_valid_topology) {
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return;
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}
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m_child_circuits.clear ();
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m_parent_circuits.clear ();
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size_t max_index = 0;
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for (circuit_iterator c = begin_circuits (); c != end_circuits (); ++c) {
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c->set_index (max_index);
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++max_index;
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}
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// build the child circuit list ... needed for the topology sorting
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m_child_circuits.reserve (max_index);
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m_parent_circuits.reserve (max_index);
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for (circuit_iterator c = begin_circuits (); c != end_circuits (); ++c) {
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std::set<Circuit *> children;
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for (Circuit::subcircuit_iterator sc = c->begin_subcircuits (); sc != c->end_subcircuits (); ++sc) {
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if (sc->circuit_ref ()) {
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children.insert (sc->circuit_ref ());
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}
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}
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m_child_circuits.push_back (tl::vector<Circuit *> ());
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tl::vector<Circuit *> &cc = m_child_circuits.back ();
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cc.reserve (children.size ());
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cc.insert (cc.end (), children.begin (), children.end ());
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// sort by index for better reproducibility
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std::sort (cc.begin (), cc.end (), sort_by_index ());
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std::set<Circuit *> parents;
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for (Circuit::refs_iterator sc = c->begin_refs (); sc != c->end_refs (); ++sc) {
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if (sc->circuit ()) {
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parents.insert (sc->circuit ());
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}
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}
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m_parent_circuits.push_back (tl::vector<Circuit *> ());
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tl::vector<Circuit *> &pc = m_parent_circuits.back ();
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pc.reserve (parents.size ());
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pc.insert (pc.end (), parents.begin (), parents.end ());
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// sort by index for better reproducibility
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std::sort (pc.begin (), pc.end (), sort_by_index ());
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}
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// do topology sorting
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m_top_circuits = 0;
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m_top_down_circuits.clear ();
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m_top_down_circuits.reserve (max_index);
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std::vector<size_t> num_parents (max_index, 0);
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// while there are cells to treat ..
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while (m_top_down_circuits.size () != max_index) {
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size_t n_top_down_circuits = m_top_down_circuits.size ();
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// Treat all circuits that do not have all parents reported.
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// For all such a circuits, disable the parent counting,
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// add the circuits's index to the top-down sorted list and
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// increment the reported parent count in all the
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// child circuits.
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for (circuit_iterator c = begin_circuits (); c != end_circuits (); ++c) {
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if (m_parent_circuits [c->index ()].size () == num_parents [c->index ()]) {
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m_top_down_circuits.push_back (c.operator-> ());
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num_parents [c->index ()] = std::numeric_limits<cell_index_type>::max ();
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}
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}
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// For all these a circuits, increment the reported parent instance
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// count in all the child circuits.
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for (tl::vector<Circuit *>::const_iterator ii = m_top_down_circuits.begin () + n_top_down_circuits; ii != m_top_down_circuits.end (); ++ii) {
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const tl::vector<Circuit *> &cc = m_child_circuits [(*ii)->index ()];
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for (tl::vector<Circuit *>::const_iterator icc = cc.begin (); icc != cc.end (); ++icc) {
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tl_assert (num_parents [(*icc)->index ()] != std::numeric_limits<cell_index_type>::max ());
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num_parents [(*icc)->index ()] += 1;
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}
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}
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// If no new cells have been reported this is basically a
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// sign of recursion in the graph.
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if (n_top_down_circuits == m_top_down_circuits.size ()) {
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throw tl::Exception (tl::to_string (tr ("Recursive hierarchy detected in netlist")));
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}
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}
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// Determine the number of top cells
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for (tl::vector<Circuit *>::const_iterator e = m_top_down_circuits.begin (); e != m_top_down_circuits.end () && m_parent_circuits [(*e)->index ()].empty (); ++e) {
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++m_top_circuits;
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}
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m_valid_topology = true;
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}
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const tl::vector<Circuit *> &Netlist::child_circuits (Circuit *circuit)
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{
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if (! m_valid_topology) {
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validate_topology ();
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}
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tl_assert (circuit->index () < m_child_circuits.size ());
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return m_child_circuits [circuit->index ()];
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}
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const tl::vector<Circuit *> &Netlist::parent_circuits (Circuit *circuit)
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{
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if (! m_valid_topology) {
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validate_topology ();
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}
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tl_assert (circuit->index () < m_parent_circuits.size ());
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return m_parent_circuits [circuit->index ()];
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}
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Netlist::top_down_circuit_iterator Netlist::begin_top_down ()
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{
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if (! m_valid_topology) {
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validate_topology ();
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}
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return m_top_down_circuits.begin ();
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}
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Netlist::top_down_circuit_iterator Netlist::end_top_down ()
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{
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if (! m_valid_topology) {
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validate_topology ();
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}
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return m_top_down_circuits.end ();
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}
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Netlist::const_top_down_circuit_iterator Netlist::begin_top_down () const
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{
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if (! m_valid_topology) {
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const_cast<Netlist *> (this)->validate_topology ();
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}
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return reinterpret_cast<const tl::vector<const Circuit *> &> (m_top_down_circuits).begin ();
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}
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Netlist::const_top_down_circuit_iterator Netlist::end_top_down () const
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{
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if (! m_valid_topology) {
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const_cast<Netlist *> (this)->validate_topology ();
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}
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return reinterpret_cast<const tl::vector<const Circuit *> &> (m_top_down_circuits).end ();
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}
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size_t Netlist::top_circuit_count () const
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{
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if (! m_valid_topology) {
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const_cast<Netlist *> (this)->validate_topology ();
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}
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return m_top_circuits;
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}
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Netlist::bottom_up_circuit_iterator Netlist::begin_bottom_up ()
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{
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if (! m_valid_topology) {
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validate_topology ();
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}
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return m_top_down_circuits.rbegin ();
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}
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Netlist::bottom_up_circuit_iterator Netlist::end_bottom_up ()
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{
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if (! m_valid_topology) {
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validate_topology ();
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}
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return m_top_down_circuits.rend ();
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}
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Netlist::const_bottom_up_circuit_iterator Netlist::begin_bottom_up () const
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{
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if (! m_valid_topology) {
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const_cast<Netlist *> (this)->validate_topology ();
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}
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return reinterpret_cast<const tl::vector<const Circuit *> &> (m_top_down_circuits).rbegin ();
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}
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Netlist::const_bottom_up_circuit_iterator Netlist::end_bottom_up () const
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{
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if (! m_valid_topology) {
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const_cast<Netlist *> (this)->validate_topology ();
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}
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return reinterpret_cast<const tl::vector<const Circuit *> &> (m_top_down_circuits).rend ();
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}
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void Netlist::clear ()
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{
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m_device_classes.clear ();
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@ -920,6 +920,10 @@ public:
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typedef subcircuit_list::iterator subcircuit_iterator;
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typedef tl::weak_collection<SubCircuit>::const_iterator const_refs_iterator;
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typedef tl::weak_collection<SubCircuit>::iterator refs_iterator;
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typedef tl::vector<Circuit *>::const_iterator child_circuit_iterator;
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typedef tl::vector<const Circuit *>::const_iterator const_child_circuit_iterator;
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typedef tl::vector<Circuit *>::const_iterator parent_circuit_iterator;
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typedef tl::vector<const Circuit *>::const_iterator const_parent_circuit_iterator;
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/**
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* @brief Constructor
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@ -974,6 +978,15 @@ public:
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return m_name;
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}
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/**
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* @brief The index of the circuit in the netlist
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* CAUTION: this attribute is used for internal purposes and may not be valid always.
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*/
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size_t index () const
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{
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return m_index;
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}
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/**
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* @brief Sets the layout cell reference for this circuit
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*
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@ -1016,6 +1029,52 @@ public:
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return m_refs.begin ();
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}
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/**
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* @brief Gets the child circuits iterator (begin)
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* The child circuits are the circuits referenced by all subcircuits
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* in the circuit.
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*/
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child_circuit_iterator begin_children ();
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/**
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* @brief Gets the child circuits iterator (end)
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*/
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child_circuit_iterator end_children ();
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/**
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* @brief Gets the child circuits iterator (begin, const version)
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* The child circuits are the circuits referenced by all subcircuits
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* in the circuit.
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*/
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const_child_circuit_iterator begin_children () const;
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/**
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* @brief Gets the child circuits iterator (end, const version)
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*/
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const_child_circuit_iterator end_children () const;
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/**
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* @brief Gets the parent circuits iterator (begin)
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* The parents circuits are the circuits referencing this circuit via subcircuits.
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*/
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parent_circuit_iterator begin_parents ();
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/**
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* @brief Gets the parent circuits iterator (end)
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*/
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parent_circuit_iterator end_parents ();
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/**
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* @brief Gets the parent circuits iterator (begin, const version)
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* The parents circuits are the circuits referencing this circuit via subcircuits.
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*/
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const_parent_circuit_iterator begin_parents () const;
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/**
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* @brief Gets the parent circuits iterator (end, const version)
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*/
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const_parent_circuit_iterator end_parents () const;
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/**
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* @brief Gets the references to this circuit (end, const version)
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* This iterator will deliver all subcircuits referencing this circuit
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@ -1300,10 +1359,13 @@ private:
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bool m_valid_subcircuit_id_table;
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std::map<size_t, SubCircuit *> m_subcircuit_id_table;
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tl::weak_collection<SubCircuit> m_refs;
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size_t m_index;
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void set_index (size_t index)
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{
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m_index = index;
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}
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/**
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* @brief Sets the pin reference for a specific pin
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*/
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void set_pin_ref_for_pin (size_t ppin_id, Net::pin_iterator iter);
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void register_ref (SubCircuit *sc);
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@ -1717,6 +1779,10 @@ public:
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typedef tl::shared_collection<DeviceClass> device_class_list;
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typedef device_class_list::const_iterator const_device_class_iterator;
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typedef device_class_list::iterator device_class_iterator;
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typedef tl::vector<Circuit *>::const_iterator top_down_circuit_iterator;
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typedef tl::vector<const Circuit *>::const_iterator const_top_down_circuit_iterator;
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typedef tl::vector<Circuit *>::const_reverse_iterator bottom_up_circuit_iterator;
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typedef tl::vector<const Circuit *>::const_reverse_iterator const_bottom_up_circuit_iterator;
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/**
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* @brief Constructor
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@ -1784,6 +1850,65 @@ public:
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return m_circuits.end ();
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}
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/**
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* @brief Gets the top-down circuits iterator (begin)
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* This iterator will deliver the circuits in a top-down way - i.e. child circuits
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* will always come after parent circuits.
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* The first "top_circuit_count" elements will be top circuits (those which are not
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* referenced by other circuits).
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*/
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top_down_circuit_iterator begin_top_down ();
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/**
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* @brief Gets the top-down circuits iterator (end)
|
||||
*/
|
||||
top_down_circuit_iterator end_top_down ();
|
||||
|
||||
/**
|
||||
* @brief Gets the top-down circuits iterator (begin, const version)
|
||||
* This iterator will deliver the circuits in a top-down way - i.e. child circuits
|
||||
* will always come after parent circuits.
|
||||
* The first "top_circuit_count" elements will be top circuits (those which are not
|
||||
* referenced by other circuits).
|
||||
*/
|
||||
const_top_down_circuit_iterator begin_top_down () const;
|
||||
|
||||
/**
|
||||
* @brief Gets the top-down circuits iterator (end, const version)
|
||||
*/
|
||||
const_top_down_circuit_iterator end_top_down () const;
|
||||
|
||||
/**
|
||||
* @brief Gets the number of top circuits
|
||||
* Top circuits are those which are not referenced by other circuits.
|
||||
* In a well-formed netlist there is a single top-level circuit.
|
||||
*/
|
||||
size_t top_circuit_count () const;
|
||||
|
||||
/**
|
||||
* @brief Gets the bottom-up circuits iterator (begin)
|
||||
* This iterator will deliver the circuits in a bottom-up way - i.e. child circuits
|
||||
* will always come before parent circuits.
|
||||
*/
|
||||
bottom_up_circuit_iterator begin_bottom_up ();
|
||||
|
||||
/**
|
||||
* @brief Gets the bottom-up circuits iterator (end)
|
||||
*/
|
||||
bottom_up_circuit_iterator end_bottom_up ();
|
||||
|
||||
/**
|
||||
* @brief Gets the bottom-up circuits iterator (begin, const version)
|
||||
* This iterator will deliver the circuits in a bottom-up way - i.e. child circuits
|
||||
* will always come before parent circuits.
|
||||
*/
|
||||
const_bottom_up_circuit_iterator begin_bottom_up () const;
|
||||
|
||||
/**
|
||||
* @brief Gets the bottom-up circuits iterator (end, const version)
|
||||
*/
|
||||
const_bottom_up_circuit_iterator end_bottom_up () const;
|
||||
|
||||
/**
|
||||
* @brief Adds a device class to this netlist
|
||||
*
|
||||
|
|
@ -1844,8 +1969,21 @@ public:
|
|||
void combine_devices ();
|
||||
|
||||
private:
|
||||
friend class Circuit;
|
||||
|
||||
circuit_list m_circuits;
|
||||
device_class_list m_device_classes;
|
||||
bool m_valid_topology;
|
||||
tl::vector<Circuit *> m_top_down_circuits;
|
||||
tl::vector<tl::vector<Circuit *> > m_child_circuits;
|
||||
tl::vector<tl::vector<Circuit *> > m_parent_circuits;
|
||||
size_t m_top_circuits;
|
||||
|
||||
void invalidate_topology ();
|
||||
void validate_topology ();
|
||||
|
||||
const tl::vector<Circuit *> &child_circuits (Circuit *circuit);
|
||||
const tl::vector<Circuit *> &parent_circuits (Circuit *circuit);
|
||||
};
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -627,6 +627,14 @@ Class<db::Circuit> decl_dbCircuit ("db", "Circuit",
|
|||
"to the outside through such a pin. The pin is added after all existing "
|
||||
"pins. For more details see the \\Pin class."
|
||||
) +
|
||||
gsi::iterator ("each_child", (db::Circuit::child_circuit_iterator (db::Circuit::*) ()) &db::Circuit::begin_children, (db::Circuit::child_circuit_iterator (db::Circuit::*) ()) &db::Circuit::end_children,
|
||||
"@brief Iterates over the child circuits of this circuit\n"
|
||||
"Child circuits are the ones that are referenced from this circuit via subcircuits."
|
||||
) +
|
||||
gsi::iterator ("each_parent", (db::Circuit::parent_circuit_iterator (db::Circuit::*) ()) &db::Circuit::begin_parents, (db::Circuit::parent_circuit_iterator (db::Circuit::*) ()) &db::Circuit::end_parents,
|
||||
"@brief Iterates over the parent circuits of this circuit\n"
|
||||
"Child circuits are the ones that are referencing this circuit via subcircuits."
|
||||
) +
|
||||
gsi::iterator ("each_ref", (db::Circuit::refs_iterator (db::Circuit::*) ()) &db::Circuit::begin_refs, (db::Circuit::refs_iterator (db::Circuit::*) ()) &db::Circuit::end_refs,
|
||||
"@brief Iterates over the subcircuit objects referencing this circuit\n"
|
||||
) +
|
||||
|
|
@ -800,6 +808,21 @@ Class<db::Netlist> decl_dbNetlist ("db", "Netlist",
|
|||
"@brief Removes the given circuit object from the netlist\n"
|
||||
"After the object has been removed, it becomes invalid and cannot be used further."
|
||||
) +
|
||||
gsi::iterator ("each_circuit_top_down", (db::Netlist::top_down_circuit_iterator (db::Netlist::*) ()) &db::Netlist::begin_top_down, (db::Netlist::top_down_circuit_iterator (db::Netlist::*) ()) &db::Netlist::end_top_down,
|
||||
"@brief Iterates over the circuits top-down\n"
|
||||
"Iterating top-down means the parent circuits come before the child circuits. "
|
||||
"The first \\top_circuit_count circuits are top circuits - i.e. those which are not referenced by other circuits."
|
||||
) +
|
||||
gsi::iterator ("each_circuit_bottom_up", (db::Netlist::bottom_up_circuit_iterator (db::Netlist::*) ()) &db::Netlist::begin_bottom_up, (db::Netlist::bottom_up_circuit_iterator (db::Netlist::*) ()) &db::Netlist::end_bottom_up,
|
||||
"@brief Iterates over the circuits bottom-up\n"
|
||||
"Iterating bottom-up means the parent circuits come after the child circuits. "
|
||||
"This is the basically the reverse order as delivered by \\each_circuit_top_down."
|
||||
) +
|
||||
gsi::method ("top_circuit_count", &db::Netlist::top_circuit_count,
|
||||
"@brief Gets the number of top circuits.\n"
|
||||
"Top circuits are those which are not referenced by other circuits via subcircuits. "
|
||||
"A well-formed netlist has a single top circuit."
|
||||
) +
|
||||
gsi::iterator ("each_circuit", (db::Netlist::circuit_iterator (db::Netlist::*) ()) &db::Netlist::begin_circuits, (db::Netlist::circuit_iterator (db::Netlist::*) ()) &db::Netlist::end_circuits,
|
||||
"@brief Iterates over the circuits of the netlist"
|
||||
) +
|
||||
|
|
|
|||
|
|
@ -834,3 +834,121 @@ TEST(11_NetlistCircuitRefs)
|
|||
sc3 = db::SubCircuit ();
|
||||
EXPECT_EQ (refs2string (c2), "sc1,sc2");
|
||||
}
|
||||
|
||||
static std::string children2string (const db::Circuit *c)
|
||||
{
|
||||
std::string res;
|
||||
for (db::Circuit::const_child_circuit_iterator r = c->begin_children (); r != c->end_children (); ++r) {
|
||||
if (!res.empty ()) {
|
||||
res += ",";
|
||||
}
|
||||
res += (*r)->name ();
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
||||
static std::string parents2string (const db::Circuit *c)
|
||||
{
|
||||
std::string res;
|
||||
for (db::Circuit::const_parent_circuit_iterator r = c->begin_parents (); r != c->end_parents (); ++r) {
|
||||
if (!res.empty ()) {
|
||||
res += ",";
|
||||
}
|
||||
res += (*r)->name ();
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
||||
static std::string td2string (const db::Netlist *nl)
|
||||
{
|
||||
std::string res;
|
||||
for (db::Netlist::const_top_down_circuit_iterator r = nl->begin_top_down (); r != nl->end_top_down (); ++r) {
|
||||
if (!res.empty ()) {
|
||||
res += ",";
|
||||
}
|
||||
res += (*r)->name ();
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
||||
static std::string bu2string (const db::Netlist *nl)
|
||||
{
|
||||
std::string res;
|
||||
for (db::Netlist::const_bottom_up_circuit_iterator r = nl->begin_bottom_up (); r != nl->end_bottom_up (); ++r) {
|
||||
if (!res.empty ()) {
|
||||
res += ",";
|
||||
}
|
||||
res += (*r)->name ();
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
||||
TEST(12_NetlistTopology)
|
||||
{
|
||||
std::auto_ptr<db::Netlist> nl (new db::Netlist ());
|
||||
EXPECT_EQ (nl->top_circuit_count (), size_t (0));
|
||||
|
||||
db::Circuit *c1 = new db::Circuit ();
|
||||
c1->set_name ("c1");
|
||||
nl->add_circuit (c1);
|
||||
EXPECT_EQ (nl->top_circuit_count (), size_t (1));
|
||||
EXPECT_EQ (td2string (nl.get ()), "c1");
|
||||
EXPECT_EQ (bu2string (nl.get ()), "c1");
|
||||
|
||||
db::Circuit *c2 = new db::Circuit ();
|
||||
c2->set_name ("c2");
|
||||
nl->add_circuit (c2);
|
||||
EXPECT_EQ (nl->top_circuit_count (), size_t (2));
|
||||
EXPECT_EQ (td2string (nl.get ()), "c1,c2");
|
||||
EXPECT_EQ (bu2string (nl.get ()), "c2,c1");
|
||||
|
||||
db::Circuit *c3 = new db::Circuit ();
|
||||
c3->set_name ("c3");
|
||||
nl->add_circuit (c3);
|
||||
EXPECT_EQ (nl->top_circuit_count (), size_t (3));
|
||||
EXPECT_EQ (td2string (nl.get ()), "c1,c2,c3");
|
||||
EXPECT_EQ (bu2string (nl.get ()), "c3,c2,c1");
|
||||
|
||||
db::SubCircuit *sc1 = new db::SubCircuit (c2);
|
||||
sc1->set_name ("sc1");
|
||||
c1->add_subcircuit (sc1);
|
||||
EXPECT_EQ (children2string (c1), "c2");
|
||||
EXPECT_EQ (parents2string (c2), "c1");
|
||||
EXPECT_EQ (nl->top_circuit_count (), size_t (2));
|
||||
EXPECT_EQ (td2string (nl.get ()), "c1,c3,c2");
|
||||
EXPECT_EQ (bu2string (nl.get ()), "c2,c3,c1");
|
||||
|
||||
db::SubCircuit *sc2 = new db::SubCircuit (c2);
|
||||
sc2->set_name ("sc2");
|
||||
c1->add_subcircuit (sc2);
|
||||
EXPECT_EQ (children2string (c1), "c2");
|
||||
EXPECT_EQ (parents2string (c2), "c1");
|
||||
EXPECT_EQ (nl->top_circuit_count (), size_t (2));
|
||||
EXPECT_EQ (td2string (nl.get ()), "c1,c3,c2");
|
||||
EXPECT_EQ (bu2string (nl.get ()), "c2,c3,c1");
|
||||
|
||||
db::SubCircuit *sc3 = new db::SubCircuit (c3);
|
||||
sc3->set_name ("sc3");
|
||||
c1->add_subcircuit (sc3);
|
||||
EXPECT_EQ (children2string (c1), "c2,c3");
|
||||
EXPECT_EQ (children2string (c2), "");
|
||||
EXPECT_EQ (children2string (c3), "");
|
||||
EXPECT_EQ (parents2string (c2), "c1");
|
||||
EXPECT_EQ (parents2string (c3), "c1");
|
||||
EXPECT_EQ (nl->top_circuit_count (), size_t (1));
|
||||
EXPECT_EQ (td2string (nl.get ()), "c1,c2,c3");
|
||||
EXPECT_EQ (bu2string (nl.get ()), "c3,c2,c1");
|
||||
|
||||
db::SubCircuit *sc4 = new db::SubCircuit (*sc2);
|
||||
sc4->set_name ("sc4");
|
||||
c3->add_subcircuit (sc4);
|
||||
|
||||
EXPECT_EQ (children2string (c1), "c2,c3");
|
||||
EXPECT_EQ (children2string (c2), "");
|
||||
EXPECT_EQ (children2string (c3), "c2");
|
||||
EXPECT_EQ (parents2string (c2), "c1,c3");
|
||||
EXPECT_EQ (parents2string (c3), "c1");
|
||||
EXPECT_EQ (nl->top_circuit_count (), size_t (1));
|
||||
EXPECT_EQ (td2string (nl.get ()), "c1,c3,c2");
|
||||
EXPECT_EQ (bu2string (nl.get ()), "c2,c3,c1");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -563,6 +563,98 @@ class DBNetlist_TestClass < TestBase
|
|||
|
||||
end
|
||||
|
||||
def test_10_NetlistTopology
|
||||
|
||||
nl = RBA::Netlist::new
|
||||
assert_equal(nl.top_circuit_count, 0)
|
||||
|
||||
c1 = RBA::Circuit::new
|
||||
c1.name = "C1"
|
||||
nl.add(c1)
|
||||
assert_equal(nl.top_circuit_count, 1)
|
||||
|
||||
c2 = RBA::Circuit::new
|
||||
c2.name = "C2"
|
||||
nl.add(c2)
|
||||
assert_equal(nl.top_circuit_count, 2)
|
||||
|
||||
c3 = RBA::Circuit::new
|
||||
c3.name = "C3"
|
||||
nl.add(c3)
|
||||
assert_equal(nl.top_circuit_count, 3)
|
||||
|
||||
names = []
|
||||
nl.each_circuit_top_down { |c| names << c.name }
|
||||
assert_equal(names.join(","), "C1,C2,C3")
|
||||
|
||||
names = []
|
||||
nl.each_circuit_bottom_up { |c| names << c.name }
|
||||
assert_equal(names.join(","), "C3,C2,C1")
|
||||
|
||||
names = []
|
||||
c1.each_child { |c| names << c.name }
|
||||
assert_equal(names.join(","), "")
|
||||
|
||||
names = []
|
||||
c2.each_parent { |c| names << c.name }
|
||||
assert_equal(names.join(","), "")
|
||||
|
||||
c1.create_subcircuit(c2)
|
||||
assert_equal(nl.top_circuit_count, 2)
|
||||
|
||||
names = []
|
||||
c1.each_child { |c| names << c.name }
|
||||
assert_equal(names.join(","), "C2")
|
||||
|
||||
names = []
|
||||
c2.each_parent { |c| names << c.name }
|
||||
assert_equal(names.join(","), "C1")
|
||||
|
||||
c1.create_subcircuit(c2)
|
||||
c1.create_subcircuit(c3)
|
||||
assert_equal(nl.top_circuit_count, 1)
|
||||
|
||||
names = []
|
||||
c1.each_child { |c| names << c.name }
|
||||
assert_equal(names.join(","), "C2,C3")
|
||||
|
||||
names = []
|
||||
c2.each_parent { |c| names << c.name }
|
||||
assert_equal(names.join(","), "C1")
|
||||
|
||||
names = []
|
||||
c3.each_parent { |c| names << c.name }
|
||||
assert_equal(names.join(","), "C1")
|
||||
|
||||
names = []
|
||||
nl.each_circuit_top_down { |c| names << c.name }
|
||||
assert_equal(names.join(","), "C1,C2,C3")
|
||||
|
||||
names = []
|
||||
nl.each_circuit_bottom_up { |c| names << c.name }
|
||||
assert_equal(names.join(","), "C3,C2,C1")
|
||||
|
||||
c3.create_subcircuit(c2)
|
||||
assert_equal(nl.top_circuit_count, 1)
|
||||
|
||||
names = []
|
||||
c2.each_parent { |c| names << c.name }
|
||||
assert_equal(names.join(","), "C1,C3")
|
||||
|
||||
names = []
|
||||
c3.each_parent { |c| names << c.name }
|
||||
assert_equal(names.join(","), "C1")
|
||||
|
||||
names = []
|
||||
nl.each_circuit_top_down { |c| names << c.name }
|
||||
assert_equal(names.join(","), "C1,C3,C2")
|
||||
|
||||
names = []
|
||||
nl.each_circuit_bottom_up { |c| names << c.name }
|
||||
assert_equal(names.join(","), "C2,C3,C1")
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
load("test_epilogue.rb")
|
||||
|
|
|
|||
Loading…
Reference in New Issue