mirror of https://github.com/KLayout/klayout.git
Added RBA tests for four-terminal MOS extraction plus global nets.
This commit is contained in:
Matthias Koefferlein
parent
294f1701b5
commit
fb4048d317
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@ -106,6 +106,12 @@ template<> struct type_traits<db::NetlistDeviceExtractorMOS3Transistor> : public
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typedef tl::false_tag has_default_constructor;
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};
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template<> struct type_traits<db::NetlistDeviceExtractorMOS4Transistor> : public tl::type_traits<void>
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{
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typedef tl::false_tag has_copy_constructor;
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typedef tl::false_tag has_default_constructor;
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};
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}
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#endif
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@ -415,4 +415,39 @@ Class<db::NetlistDeviceExtractorMOS3Transistor> decl_NetlistDeviceExtractorMOS3T
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"This class has been introduced in version 0.26."
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);
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db::NetlistDeviceExtractorMOS4Transistor *make_mos4_extractor (const std::string &name)
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{
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return new db::NetlistDeviceExtractorMOS4Transistor (name);
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}
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Class<db::NetlistDeviceExtractorMOS4Transistor> decl_NetlistDeviceExtractorMOS4Transistor (decl_dbNetlistDeviceExtractor, "db", "DeviceExtractorMOS4Transistor",
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gsi::constructor ("new", &make_mos4_extractor, gsi::arg ("name"),
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"@brief Creates a new device extractor with the given name."
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),
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"@brief A device extractor for a four-terminal MOS transistor\n"
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"\n"
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"This class supplies the generic extractor for a MOS device.\n"
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"The device is defined by two basic input layers: the diffusion area\n"
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"(source and drain) and the gate area. It requires a third layer\n"
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"(poly) to put the gate terminals on and a forth layer to put the bulk\n"
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"terminal an. The separation between poly\n"
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"and allows separating the device recognition layer (gate) from the\n"
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"conductive layer.\n"
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"\n"
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"The bulk terminal layer can be an empty layer representing the substrate.\n"
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"In this use mode the bulk terminal shapes will be produced there. This\n"
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"layer then needs to be connected to a global net to establish the net.\n"
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"\n"
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"The device class produced by this extractor is \\DeviceClassMOS4Transistor.\n"
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"The extractor extracts the four parameters of this class: L, W, AS and AD.\n"
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"\n"
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"The diffusion area is distributed on the number of gates connecting to\n"
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"the particular source or drain area.\n"
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"\n"
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"This class is a closed one and methods cannot be reimplemented. To reimplement "
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"specific methods, see \\DeviceExtractor.\n"
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"\n"
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"This class has been introduced in version 0.26."
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);
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}
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@ -290,6 +290,134 @@ END
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end
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def test_12_LayoutToNetlistExtractionWithDevicesAndGlobalNets
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ly = RBA::Layout::new
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ly.read(File.join($ut_testsrc, "testdata", "algo", "device_extract_l3.gds"))
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l2n = RBA::LayoutToNetlist::new(RBA::RecursiveShapeIterator::new(ly, ly.top_cell, []))
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rbulk = l2n.make_polygon_layer( ly.layer )
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rnwell = l2n.make_polygon_layer( ly.layer(1, 0) )
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ractive = l2n.make_polygon_layer( ly.layer(2, 0) )
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rpoly = l2n.make_polygon_layer( ly.layer(3, 0) )
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rpoly_lbl = l2n.make_text_layer( ly.layer(3, 1) )
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rdiff_cont = l2n.make_polygon_layer( ly.layer(4, 0) )
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rpoly_cont = l2n.make_polygon_layer( ly.layer(5, 0) )
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rmetal1 = l2n.make_polygon_layer( ly.layer(6, 0) )
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rmetal1_lbl = l2n.make_text_layer( ly.layer(6, 1) )
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rvia1 = l2n.make_polygon_layer( ly.layer(7, 0) )
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rmetal2 = l2n.make_polygon_layer( ly.layer(8, 0) )
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rmetal2_lbl = l2n.make_text_layer( ly.layer(8, 1) )
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rpplus = l2n.make_polygon_layer( ly.layer(10, 0) )
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rnplus = l2n.make_polygon_layer( ly.layer(11, 0) )
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ractive_in_nwell = ractive & rnwell
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rpactive = ractive_in_nwell & rpplus
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rntie = ractive_in_nwell & rnplus
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rpgate = rpactive & rpoly
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rpsd = rpactive - rpgate
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ractive_outside_nwell = ractive - rnwell
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rnactive = ractive_outside_nwell & rnplus
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rptie = ractive_outside_nwell & rpplus
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rngate = rnactive & rpoly
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rnsd = rnactive - rngate
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# PMOS transistor device extraction
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pmos_ex = RBA::DeviceExtractorMOS4Transistor::new("PMOS")
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l2n.extract_devices(pmos_ex, { "SD" => rpsd, "G" => rpgate, "P" => rpoly, "W" => rnwell })
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# NMOS transistor device extraction
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nmos_ex = RBA::DeviceExtractorMOS4Transistor::new("NMOS")
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l2n.extract_devices(nmos_ex, { "SD" => rnsd, "G" => rngate, "P" => rpoly, "W" => rbulk })
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# Define connectivity for netlist extraction
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# Intra-layer
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l2n.connect(rpsd)
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l2n.connect(rnsd)
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l2n.connect(rnwell)
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l2n.connect(rpoly)
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l2n.connect(rdiff_cont)
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l2n.connect(rpoly_cont)
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l2n.connect(rmetal1)
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l2n.connect(rvia1)
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l2n.connect(rmetal2)
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l2n.connect(rptie)
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l2n.connect(rntie)
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# Inter-layer
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l2n.connect(rpsd, rdiff_cont)
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l2n.connect(rnsd, rdiff_cont)
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l2n.connect(rpoly, rpoly_cont)
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l2n.connect(rpoly_cont, rmetal1)
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l2n.connect(rdiff_cont, rmetal1)
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l2n.connect(rdiff_cont, rntie)
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l2n.connect(rdiff_cont, rptie)
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l2n.connect(rnwell, rntie)
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l2n.connect(rmetal1, rvia1)
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l2n.connect(rvia1, rmetal2)
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l2n.connect(rpoly, rpoly_lbl) # attaches labels
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l2n.connect(rmetal1, rmetal1_lbl) # attaches labels
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l2n.connect(rmetal2, rmetal2_lbl) # attaches labels
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# Global connections
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l2n.connect_global(rptie, "BULK")
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l2n.connect_global(rbulk, "BULK")
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# Perform netlist extraction
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l2n.extract_netlist
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assert_equal(l2n.netlist.to_s, <<END)
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Circuit RINGO ():
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XINV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD)
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XINV2PAIR $2 (BULK='BULK,VSS',$2=$I22,$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD)
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XINV2PAIR $3 (BULK='BULK,VSS',$2=$I23,$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD)
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XINV2PAIR $4 (BULK='BULK,VSS',$2=$I24,$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD)
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XINV2PAIR $5 (BULK='BULK,VSS',$2=$I25,$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD)
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Circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1):
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XINV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK)
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XINV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK)
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Circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK):
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DPMOS $1 (S=$3,G=IN,D=VDD,B=$1) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
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DPMOS $2 (S=VDD,G=$3,D=OUT,B=$1) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
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DNMOS $3 (S=$3,G=IN,D=VSS,B=BULK) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
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DNMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
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XTRANS $1 ($1=$3,$2=VSS,$3=IN)
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XTRANS $2 ($1=$3,$2=VDD,$3=IN)
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XTRANS $3 ($1=VDD,$2=OUT,$3=$3)
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XTRANS $4 ($1=VSS,$2=OUT,$3=$3)
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Circuit TRANS ($1=$1,$2=$2,$3=$3):
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END
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l2n.netlist.combine_devices
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l2n.netlist.make_top_level_pins
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l2n.netlist.purge
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puts l2n.netlist.to_s
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assert_equal(l2n.netlist.to_s, <<END)
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Circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,'BULK,VSS'='BULK,VSS'):
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XINV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD)
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XINV2PAIR $2 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD)
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XINV2PAIR $3 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD)
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XINV2PAIR $4 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD)
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XINV2PAIR $5 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD)
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Circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1):
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XINV2 $1 ($1=$I1,IN=$I3,$3=(null),OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK)
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XINV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK)
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Circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK):
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DPMOS $1 (S=$3,G=IN,D=VDD,B=$1) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
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DPMOS $2 (S=VDD,G=$3,D=OUT,B=$1) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
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DNMOS $3 (S=$3,G=IN,D=VSS,B=BULK) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
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DNMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
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END
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# cleanup now
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l2n._destroy
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end
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end
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load("test_epilogue.rb")
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