mirror of https://github.com/KLayout/klayout.git
WIP: fixed unit tests.
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187baf2941
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648aa9e077
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@ -229,9 +229,9 @@ END
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assert_equal(logger.text, <<"END")
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begin_circuit INV INV
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match_nets VDD VDD
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match_nets VSS VSS
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match_nets OUT OUT
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match_nets IN IN
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match_nets VSS VSS
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match_pins $0 $1
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match_pins $1 $3
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match_pins $2 $0
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@ -284,9 +284,9 @@ END
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assert_equal(logger.text(), <<"END")
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begin_circuit INV INV
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match_nets VDD VDD
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match_nets VSS VSS
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match_nets OUT OUT
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match_nets IN IN
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match_nets VSS VSS
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match_pins $0 $1
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match_pins $1 $3
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match_pins $2 $0
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@ -388,12 +388,12 @@ END
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assert_equal(logger.text, <<"END")
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begin_circuit BUF BUF
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match_nets OUT OUT
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match_nets VDD VDD
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match_nets IN IN
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match_nets OUT OUT
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match_nets VSS VSS
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match_nets INT $10
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match_nets INT2 $11
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match_nets IN IN
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match_ambiguous_nets INT $10
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match_ambiguous_nets INT2 $11
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match_pins $0 $1
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match_pins $1 $3
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match_pins $2 $0
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@ -460,9 +460,9 @@ END
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assert_equal(logger.text, <<"END")
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begin_circuit BUF BUF
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match_nets OUT OUT
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match_ambiguous_nets INT $10
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match_nets INT2 $11
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match_nets INT $10
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match_nets IN IN
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match_nets INT2 $11
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match_pins $0 $1
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match_pins $1 $3
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match_pins $2 $0
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@ -489,8 +489,8 @@ END
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begin_circuit BUF BUF
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match_nets OUT OUT
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match_nets IN IN
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match_nets INT2 $11
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match_nets INT $10
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match_ambiguous_nets INT $10
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match_ambiguous_nets INT2 $11
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match_pins $0 $1
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match_pins $1 $3
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match_pins $2 $0
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@ -518,8 +518,8 @@ END
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begin_circuit BUF BUF
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match_nets OUT OUT
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match_nets IN IN
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match_nets INT2 $11
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match_nets INT $10
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match_ambiguous_nets INT $10
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match_ambiguous_nets INT2 $11
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match_pins $0 $1
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match_pins $1 $3
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match_pins $2 $0
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@ -547,8 +547,8 @@ END
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begin_circuit BUF BUF
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match_nets OUT OUT
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match_nets IN IN
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match_nets INT2 $11
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match_nets INT $10
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match_ambiguous_nets INT $10
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match_ambiguous_nets INT2 $11
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match_pins $0 $1
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match_pins $1 $3
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match_pins $2 $0
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@ -751,9 +751,9 @@ END
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assert_equal(logger.text, <<"END")
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begin_circuit INV INVB
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match_nets VDD VDD
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match_nets VSS VSS
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match_nets OUT OUT
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match_nets IN IN
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match_nets VSS VSS
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match_pins $0 $1
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match_pins $1 $3
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match_pins $2 $0
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@ -763,9 +763,9 @@ match_devices $1 $2
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end_circuit INV INVB MATCH
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begin_circuit TOP TOP
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match_nets OUT OUT
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match_nets VDD VDD
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match_nets IN IN
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match_nets VSS VSS
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match_nets VDD VDD
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match_nets INT INT
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match_pins $0 $2
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match_pins $1 $0
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@ -823,11 +823,11 @@ END
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assert_equal(logger.text, <<"END")
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begin_circuit NAND NAND
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match_nets VSS VSS
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match_nets INT INT
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match_nets OUT OUT
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match_nets VDD VDD
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match_nets B B
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match_nets OUT OUT
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match_nets A A
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match_nets INT INT
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match_pins $0 $0
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match_pins $1 $1
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match_pins $2 $2
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@ -840,11 +840,11 @@ match_devices $4 $4
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end_circuit NAND NAND MATCH
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begin_circuit TOP TOP
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match_nets OUT OUT
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match_nets VSS VSS
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match_nets VDD VDD
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match_nets IN1 IN1
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match_nets INT INT
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match_nets IN2 IN2
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match_nets INT INT
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match_nets VDD VDD
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match_nets VSS VSS
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match_pins $0 $0
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match_pins $1 $1
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match_pins $2 $2
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@ -867,11 +867,11 @@ END
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assert_equal(logger.text, <<"END")
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begin_circuit NAND NAND
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match_nets VSS VSS
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match_nets INT INT
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match_nets OUT OUT
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match_nets VDD VDD
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match_nets B B
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match_nets OUT OUT
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match_nets A A
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match_nets INT INT
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match_pins $0 $0
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match_pins $1 $1
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match_pins $2 $2
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@ -884,11 +884,11 @@ match_devices $4 $4
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end_circuit NAND NAND MATCH
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begin_circuit TOP TOP
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match_nets OUT OUT
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match_nets IN2 IN2
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match_nets VSS VSS
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match_nets VDD VDD
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match_nets IN1 IN1
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match_nets INT INT
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match_nets IN2 IN2
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match_nets IN1 IN1
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match_nets VDD VDD
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match_nets VSS VSS
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match_pins $0 $0
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match_pins $1 $1
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match_pins $2 $2
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@ -945,8 +945,8 @@ END
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assert_equal(logger.text(), <<"END")
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begin_circuit INV INV
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match_nets VDD VDD
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match_nets VSS VSS
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match_nets OUT OUT
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match_nets VSS VSS
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match_nets IN IN
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match_pins $0 $1
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match_pins $1 $3
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@ -970,9 +970,9 @@ END
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assert_equal(logger.text(), <<"END")
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begin_circuit INV INV
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match_nets VDD VDD
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match_nets VSS VSS
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match_nets OUT OUT
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match_nets IN IN
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match_nets VSS VSS
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match_pins $0 $1
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match_pins $1 $3
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match_pins $2 $0
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