Nick Gasson
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ec23b70bb7
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While loops
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2008-06-21 15:13:44 +01:00 |
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Nick Gasson
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58f2f5007d
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Bitwise AND
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2008-06-21 15:05:48 +01:00 |
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Nick Gasson
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0caf4fd9d0
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Add case statement
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2008-06-21 15:03:36 +01:00 |
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Nick Gasson
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037ce08f72
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Fix tiny bug in $display code
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2008-06-21 14:42:54 +01:00 |
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Nick Gasson
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204862ac3c
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Implement $write
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2008-06-20 19:00:07 +01:00 |
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Nick Gasson
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0f50849fbb
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Add call to To_Integer when printing signed/unsigned
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2008-06-20 18:26:39 +01:00 |
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Nick Gasson
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404c22ac86
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Improved implementation of $display
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2008-06-20 11:51:13 +01:00 |
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Nick Gasson
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08d80b35cb
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Rename signals that would be illegal VHDL names
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2008-06-19 16:15:47 +01:00 |
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Nick Gasson
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6622b5fe3a
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Compare logic values for === and !==
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2008-06-19 16:08:33 +01:00 |
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Nick Gasson
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d7bb5658f2
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Translate IVL_ST_DELAYX statements
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2008-06-19 12:16:19 +01:00 |
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Nick Gasson
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be12f56856
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Document blocking assignment behaviour
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2008-06-18 14:04:16 +01:00 |
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Nick Gasson
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e0f41198d6
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Blocking assignment working correctly
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2008-06-18 13:49:03 +01:00 |
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Nick Gasson
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fb31a88c51
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Blocking assignment nearly working
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2008-06-18 13:30:19 +01:00 |
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Nick Gasson
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254ccb9ccb
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First passing at blocking assignment
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2008-06-18 13:06:27 +01:00 |
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Nick Gasson
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d2bebee9d9
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Refactor before adding blocking assignment
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2008-06-18 12:51:11 +01:00 |
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Nick Gasson
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af8c08e6a7
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Allow optional VHPI $finish implementation
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2008-06-17 20:16:16 +01:00 |
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Nick Gasson
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01249000c3
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Temporarily treat blocking assignment as non-blocking
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2008-06-17 14:07:36 +01:00 |
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Nick Gasson
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1debbc3100
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Simplify edge_detector() a bit
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2008-06-16 20:06:06 +01:00 |
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Nick Gasson
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ae0b09dd3a
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Don't bother emitting else part if it's empty
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2008-06-16 19:53:42 +01:00 |
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Nick Gasson
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8d0afa632d
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Subtraction and multiplication LPM devices
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2008-06-16 19:49:24 +01:00 |
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Nick Gasson
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561953e494
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Minial LPM to support continuous assignments
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2008-06-16 19:41:01 +01:00 |
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Nick Gasson
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83a7796b74
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Make sure signal names conform to VHDL rules
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2008-06-16 17:37:17 +01:00 |
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Nick Gasson
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ce72eb4eb4
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Fix Valgrind warnings
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2008-06-16 14:26:38 +01:00 |
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Nick Gasson
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7cde5f247e
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Add translation for not-equals operator
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2008-06-16 12:47:41 +01:00 |
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Nick Gasson
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849e7cb4d5
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Add equality operator
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2008-06-16 12:20:28 +01:00 |
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Nick Gasson
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92c823680a
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Fix crash when `if' statement had no `else'
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2008-06-16 12:13:01 +01:00 |
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Nick Gasson
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8a9486eb49
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Eliminate useless Resize() call
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2008-06-14 18:11:10 +01:00 |
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Nick Gasson
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2fb57805ea
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Use signed rather than std_logic_vector
Arithmetic operators now working correctly
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2008-06-14 18:03:25 +01:00 |
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Nick Gasson
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919c1d695c
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Adding binary +
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2008-06-14 17:09:31 +01:00 |
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Nick Gasson
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0ea64ad8ab
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Correct misleading comment
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2008-06-13 14:47:06 +01:00 |
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Nick Gasson
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9fbb449e06
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Optimise away empty (VHDL) processes
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2008-06-13 14:17:24 +01:00 |
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Nick Gasson
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be3c4cf268
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Generate signal initial values from `initial' processes
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2008-06-13 14:10:28 +01:00 |
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Nick Gasson
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0a8fd50c4a
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Find assignments that could be initializers
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2008-06-13 13:59:48 +01:00 |
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Nick Gasson
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70db096b6d
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Clean up the edge detector code a bit
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2008-06-13 12:52:20 +01:00 |
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Nick Gasson
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005df31a0d
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Use renamed signal in expressions, if there is one
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2008-06-13 12:39:18 +01:00 |
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Nick Gasson
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d6193c1622
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Add _Reg internal signal if output is registered
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2008-06-13 12:34:27 +01:00 |
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Nick Gasson
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b8c1f9ab67
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A system for linking ivl_signal_t to entities
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2008-06-12 20:26:23 +01:00 |
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Nick Gasson
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0df3eabe26
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Convert `if (foo) ..' to `if foo = '1' then ..'
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2008-06-12 11:36:21 +01:00 |
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Nick Gasson
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8fe2211e2b
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Generate `after' modifier instead of `wait' statements
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2008-06-12 11:24:43 +01:00 |
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Nick Gasson
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645ee2003f
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Translation for unary not
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2008-06-12 10:56:28 +01:00 |
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Nick Gasson
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d6f1162547
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Generate correct VHDL signal values
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2008-06-12 10:50:46 +01:00 |
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Nick Gasson
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46991aa65c
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Generate process bodies in the right place
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2008-06-12 10:47:52 +01:00 |
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Nick Gasson
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7eb41304e6
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Generate rising/falling edge detectors
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2008-06-12 10:36:38 +01:00 |
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Nick Gasson
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19e60b698f
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Translate if statements
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2008-06-11 14:20:05 +01:00 |
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Nick Gasson
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a7cfdc3a87
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Add VHDL if statement to AST types
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2008-06-11 14:11:37 +01:00 |
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Nick Gasson
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b010b8e3ca
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Use `assert false' as initial translation of $finish
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2008-06-11 13:37:21 +01:00 |
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Nick Gasson
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26a2c69c2e
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Change architecture name to `FromVerilog'
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2008-06-11 11:31:43 +01:00 |
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Nick Gasson
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5a7cfd8c02
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Clean up vhdl_comp_inst
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2008-06-10 14:00:15 +01:00 |
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Nick Gasson
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babe694366
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Generate port mappings
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2008-06-10 13:58:41 +01:00 |
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Nick Gasson
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7560b29fb9
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Find signals to map together
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2008-06-10 12:21:48 +01:00 |