pow(int, int) is ambiguous since it could use the double version from
the math library or the verinum version. This patch makes it obvious that
we want to use the double version.
Build up a work library by writing a VHDL representation of the
package header into a source file. This representation needs to
be accurate enough that later invocations of vhdlpp can read them
with the VHDL parser.
SystemVerilog has support for time literals. The time literal for
example #10ns, adds a delay of 10ns no matter the time unit currently
in effect. For more details please refer to
http://iverilog.wikia.com/wiki/Projects#SystemVerilog_Style_Time_Literals
Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
A bit/logic output type in a module initially is defaulted to as a
variable. Depending on how they are used in the module, the type
changes accordingly.
For example
module test(output logic l);
assign l = '0;
endmodule
The variable 'l' would be promoted to a Net data type, when the
'assign' statement is encountered.
Acked-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
The module declaration should allow initialization of the bit and
logic data types.
For example:
$ cat clkgen.sv
module clkgen(output logic clk = 0, output bit p = 1);
initial begin
#200;
$display("p = %b", p);
$finish;
end
initial forever #10 clk = ~clk;
endmodule
$ iverilog -g 2009 clkgen.sv
$ ./a.out
p = 1
Suggested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
SystemVerilog allows passing the 'bit' and 'logic' arguments to a
function. The patch adds support for parsing these function
definitions. The 'bit' data type is treated as boolean, whereas 'logic'
data type remains as logic.
Acked-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
This patch removes the space between -L and the directory in the vpi
Makefile. It also fixes the line to use the correct variable name
for the LDFLAGS.
The patch allows parsing of function definitions which do not have
explicit data type or range. The default return data type is assumed
to be reg unsigned and the default range is 0.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows returning variables of 'reg' type. The icarus verilog
implicitly assumes the default returned type of the function as
'reg unsigned'. The patch allows to explicitly specify the 'reg' return
type.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows user to define variables of primitive types. The patch
adds support for defining variables of type 'logic'. The data type
'logic' is the only primitive data type which supports defining ranges.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows user to define variables of primitive types. The patch
adds support for defining variables of type 'bit'. The data type 'bit'
is the only primitive data type which supports defining ranges.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Remove an unused variable (desired_vector_width) in elaborate.cc.
Reduce the scope of spin to make it obvious it is only used locally
in elaborate.cc. Initialize sel_type_ in the NetAssign_ constructor
(net_assign.cc). The code doesn't currently require this since
sel_type_ is only used when the base is not zero and it is always
defined when base is not zero, but giving this a default value in
the constructor hedges against accidentally using an undefined
value if someone checks the select type when the base is zero.
The $ivlh_attribute_event system function helps the Verilog runtime
support <name>'event expressions in VHDL. The vhdlpp generates a
call to $ivlh_attribute_event, which in turn uses callbacks to handle
the support.
This is also the start of the vhdl_sys vpi module. This module should
by included whenever VHDL code is parsed.
The compiler was handling bi-directional pass switches using the default
case for primitive gates, where the first port is treated as an output
and the remaining ports are treated as inputs. This patch adds a special
case for pass switches, so that the first two ports are treated as
bi-directional.
When a signal (or port) is assigned by a sequential assignment,
the signal or port becomes a reg, instead of a wire(net). Detect
this distinction during elaboration and generate the correct
signal/port declaration.
The -gno-specify flag should only control the delay and timing checks.
It should not also remove the specparams since they can be used outside
of a specify block.
The IEEE standard states that the port expressions used for arrays
of primitive gates must be the exact width required, but is silent
about the requirements for single instances. The consensus among
other simulators is that for input ports of single instances, the
expression is silently truncated to a single bit.
This patch also fixes a compiler crash if an error is found when
elaborating a primitive gate port expression.
Keep the entity/component/module port declarations in the module port
list of the generated code. This clarifies the generated code and
fixes a couple bugs for more complicated types.
R-value expressions are more general then L-value expressions, in that
the expression type may be a bit more complex. If the R-value expression
is part of an assignment, then elaborate with the constrained type from
the L-value. In other cases, where the expression type is not as obvious,
use expression type probes to figure out the type of the expression and
elaborate using that calculated type.
This patch adds code to properly calculate the type and width of a
specparam when it is used in an expression.
This patch also fixes a compiler crash when an unknown identifier is
used in a delay expression.
Icarus is not actually fast enough to run into this issue in a
reasonable amount of time. I discovered this by thinking about
the algorithm and verified the fix with custom code.
Cary R
Stephen Williams
Prasad Joshi
Pawel Szostek
Martin Whitaker