1d28b935e8
Split vhdl_element.cc into multiple files
2008-06-08 13:27:48 +01:00
4b4a1c6cac
Tidy up type casting
2008-06-08 12:55:18 +01:00
110a1b2ac7
Replace type classes with enumeration
2008-06-08 12:48:56 +01:00
79558910d1
Catch case where NULL return wasn't detected
2008-06-07 16:44:01 +01:00
fbf85398da
Support converting bit strings to std_logic
2008-06-07 16:19:10 +01:00
1e4b96aa0a
Simplify code a bit as rval type is never needed
2008-06-07 14:57:20 +01:00
c064ae6bc3
Generate VHDL for non-blocking assignments
2008-06-07 14:54:00 +01:00
39228f3495
VHDL AST element for non-blocking assignment
2008-06-07 14:31:33 +01:00
12e2237131
Add Type'Image cast to $display parameters
2008-06-07 14:21:50 +01:00
066a9b7a61
Add AST element for function call expressions
2008-06-07 13:29:27 +01:00
cdb180e1d4
Associate a type with each VHDL expression node
2008-06-07 13:23:21 +01:00
a8ecce7421
Make sure all declarations have a type
2008-06-07 12:15:46 +01:00
8c3461f0ff
Generate sensitivity lists properly and add signal declarations
2008-06-07 11:48:38 +01:00
305f448d05
Generate code for signal references
2008-06-07 11:24:09 +01:00
5f90a3e48c
Translate sub-statement of @{..}
2008-06-06 18:22:03 +01:00
96cf190720
Generate signals and sensitivity list for @(..) statement
2008-06-06 17:56:52 +01:00
373832ba22
Specify correct sensitivity list
2008-06-06 17:36:15 +01:00
4f472e451e
Stubs for statement types in mux2.v test
2008-06-06 16:55:45 +01:00
d36bbec5b5
Generate VHDL for no-op statements
2008-06-05 13:16:35 +01:00
e258058cf1
Fully qualify std.textio.Output to avoid name collisions
2008-06-04 21:58:51 +01:00
c3ac1aac8c
Remove debugging messages from output
2008-06-04 21:07:50 +01:00
234f73e7bf
Don't generate any output if there were errors
2008-06-04 21:03:36 +01:00
f49dd97d24
Add support for blocks and make hello1.v test pass
2008-06-04 20:57:15 +01:00
7bd1565cfb
$display now (mostly) working
2008-06-04 20:42:44 +01:00
6e448da90d
Emit Write() calls for parameters of $display
2008-06-04 15:19:44 +01:00
9f035108e1
Stub code for translating expressions
2008-06-04 14:59:04 +01:00
4bf2e1669d
Store packages required with entity rather than globally
...
Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
2008-06-04 13:52:56 +01:00
dd30c1b39d
Support procedure call generation for $display
2008-06-04 13:27:42 +01:00
94006cb44c
Working on code generation for $display task
2008-06-03 19:46:10 +01:00
2e6ec91ce0
Scalar types
2008-06-03 19:20:45 +01:00
fe80da362c
Collect required packages as compilation progresses
2008-06-03 19:14:47 +01:00
82aca1b02e
Stub code for handling $display
2008-06-03 18:44:17 +01:00
4211e651d0
Stub file for processing statements
2008-06-03 18:26:36 +01:00
f9e1289463
Tidy up vhdl_element.cc
2008-06-03 17:43:54 +01:00
a09b4e3b92
Initial process have wait at the end
...
(do it properly this time rather than a hack :-)
2008-06-03 17:39:24 +01:00
ab6ae621cb
Remove useless comments in output
2008-06-02 20:24:25 +01:00
17ae0a6a09
Fix a bug where the same instantiation appeared multiple times
2008-06-02 18:05:39 +01:00
041925c123
Component instantiation to replicate Verilog hierarchy
2008-06-02 17:45:58 +01:00
9292a087e8
Generate VHDL processes from Verilog processes
2008-06-02 16:17:01 +01:00
fef0fd82ff
Comments
2008-06-02 00:12:47 +01:00
5cbd587833
Clean up generated objects
2008-05-31 16:08:57 +01:00
7c9d154461
Forgot source files for entity generation
2008-05-31 15:31:48 +01:00
8189c4ee43
Generate VHDL entities and architectures for all module scopes
2008-05-31 15:28:25 +01:00
05de2f56b4
Dummy code for processes
2008-05-30 01:04:47 +01:00
e38494a10c
Pretty-print VHDL output
2008-05-29 16:24:16 +01:00
e178baefbd
Merge branch 'master' of git://github.com/steveicarus/iverilog into vhdl
2008-05-28 17:23:12 +01:00
bfa2bfc8ae
Makefile and autoconf changes to build VHDL code generator
2008-05-28 17:17:39 +01:00
2179797763
Do not allow unknows to be handled as logic immediate.
2008-05-27 19:48:31 -07:00
b5e9e44e07
Fix error in of_SUBI with wide results.
...
This patch fixes an error in the recent rework of of_SUBI.
It was doing a double bit inversion.
2008-05-27 19:42:20 -07:00
5a0fe9ff83
Better use of immediate operands.
...
Clarify that operands are typically 32bits, and have the code generator
make better use of this.
Also improve the %movi implementation to work well with marger vectors.
Add the %andi instruction to use immediate operands.
2008-05-27 17:51:28 -07:00
Nick Gasson
Stephen Williams
Cary R