61930c3b6e
Add file and line information to processes.
...
This patch adds file and line information to processes
(initial and always).
2008-08-01 20:13:29 -07:00
27cdd27889
Add .cast/int and update .cast/real.
...
This patch adds .cast/int and updates .cast/real to act as a local
(temporary) net and to support either a signed or unsigned input.
The vvp_vector4_t class not can convert an arbitrarily sized double
to a vector value. This removes the restriction of lround().
Also document the new statements.
2008-06-20 19:45:18 -07:00
37723698dc
Handle non-real operands to real division.
...
This handles the general case of a non-real operand to a real-valued
division. This can turn up if only 1 operand of a divide is real. In
this case the division as a whole is real and the other operand must
be cast to real.
This method creates an extra node, but it should be a very compact
node and this node does no evaluation tricks so in the run time should
be no more expensive then folding the cast into the .arith/div.r itself.
2008-06-17 17:07:19 -07:00
73e2b297df
Replace the NetPartSelect:BI with NetTran(VP).
...
Fold the bi-directional part select into the pass switch (tran) support
so that it can be really bi-directional. This involves adding a new
tranvp device that does part select in tran islands, and reworking the
tran island resolution to handle non-identical nodes. This will be needed
for resistive tran devices anyhow.
2008-06-03 11:16:25 -07:00
df15a0368c
Collect NetTran devices into islands.
...
NetTran devices must be collected into islands because they are all
a bi-directional mass. This is how vvp will process them and the code
generator will need a head start organizing them.
2008-06-01 19:45:12 -07:00
7898f4e402
Account for swithes linked to nexus in ivl_target.h API.
...
Switches can connect to a nexus too, so add the missing nexus support
for that in the ivl_target.h API.
2008-06-01 14:29:27 -07:00
1be1f65f33
Merge branch 'master' into verilog-ams
2008-05-29 20:11:00 -07:00
7a1180868a
Remove definition for non-existent routines.
...
ivl_switch_scope, ivl_switch_attr_cnt and ivl_switch_attr_val
are non-existent routines and should not be in ivl.def. I also
removed them from ivl_target.h. Cygwin expects that if a routine
is listed in ivl.def that it will find a real implementation.
2008-05-28 09:45:27 -07:00
de7fff8ac6
Elaborate tran devices (switches)
...
This takes the support for switch modeling to the code generator.
Add error messages in the vvp code generator for lack of support.
2008-05-27 20:06:58 -07:00
ca756f3ec3
Bring switch information out to the ivl_target API.
...
This involves defining the API for switches and cleaning up the
elaborated form to match the defined ivl_target API. Also add t-dll
code to support the ivl_switch_t functions, and add stub code that
checks the results.
2008-05-23 20:53:10 -07:00
10ab5cf698
Merge branch 'verilog-ams'
2008-05-06 21:00:12 -07:00
4f8b91e65c
Add file and line information for parameters, etc.
...
This patch adds file and line information for parameters and
local parameters. It also adds file/line stubs for signals in
the tgt-* files. It adds the pform code needed to eventually
do genvar checks and passing of genvar file/line information.
It verifies that a genvar does not have the same name as a
parameter/local parameter.
2008-05-06 07:14:27 -07:00
e91243e1c6
Elaborate abs() is continuous assign expressions.
...
In continuous assign expressions, the abs() operator can't easily be
burried in generic unary handling, so add the IVL_LPM_ABS type and
generate it as needed.
2008-05-05 22:00:39 -07:00
86a4025b58
Push file and line information for scopes to the runtime.
...
This patch adds code to push the file and line information
for scope objects (modules, functions, tasks, etc.) to the
runtime. For modules, this includes the definition fields.
2008-04-29 21:51:34 -07:00
436e2fca13
Add ifnone functionality.
...
This patch adds ifnone functionality. It does not produce an
error when both an ifnone and an unconditional simple module
path are given. For this case the ifnone delays are ignored.
2008-04-29 11:55:32 -07:00
b6f26e62df
Add support for delaying constants at T0.
...
This patch adds support for delaying constants at time zero. It also
cleans up the code in elab_net.cc to use this capability instead of
building it with an extra BUFZ to carry the delay information.
2008-02-13 20:10:55 -08:00
40064b3181
Catch that we do not currently support unsigned bit based power.
...
This patch adds a check and prints a warning message when the power
operator is used with unsigned bit based values. It also fixes a couple
of typos and adds an asserts if the above power operator happens to
get to the tgt-vvp back end.
2008-02-04 13:35:44 -08:00
5e8a1bd8cc
Add power operator (**) for real values in a continuous assignment.
...
This patch adds the power operator for real values in a continuous
assignment.
2008-01-31 16:48:52 -08:00
d9ac146b8f
Spelling fixes
...
only comments and documentation
some punctuation and capitalization for good measure
Changelogs are purposefully untouched
2008-01-29 20:24:24 -08:00
47d65034db
Spelling fixes
...
mostly comments, but includes some identifiers and message text
2008-01-27 18:18:13 -08:00
10d25d2b88
Support delays for all operators in a continuous assignments.
...
Previously only the logical operators (~, &, |, ^, etc.) supported a
delayed value in a continuous assignment. This patch should extend this
to all operators. An extensive check of real values was done. The same
will be done shortly for bit based nets.
Checks for constructs currently unsupported in continuous assignments
provide a more explicit message (** operator, real user functions,
{!, && and ||} operators with a real argument).
2008-01-21 18:21:31 -08:00
eb5e7b792b
Spelling fixes
...
Sorry, I can't help myself. :-p
2008-01-08 17:26:55 -08:00
21730ab228
Fix definition missing in include file and missing UINT64_FMT.
...
This fixes the missing include file definitions and fixes three
cases that needed to us UINT64_FMT.
2008-01-03 14:14:54 -08:00
08752453b4
File line information for expressions
...
Add ivl_target support for file and line numbers of expressions.
2007-12-22 17:19:45 -05:00
1db19b8703
Make statement file lineno available to targets.
...
Make the Verilog file/lineno of statements available to loadable
code generators. Make sure the information is properly set for
system task calls.
2007-12-22 09:31:24 -05:00
0d9ed65e8c
Give delay paths scope.
...
Delay paths need a scope. This helps the code generators bind the
modpaths to the correct scope. This patch doesn't actually make use
of the information, it just makes it available to code generators.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-31 21:39:29 -07:00
3258b7726b
Pass local scope precision from compiler to vvp/etc.
...
This patch adds ivl_scope_time_precision() to the compiler which can
be used to extract the local scope precision. tgt-stub and tgt-vvp
have been modified to use this new function and output a value that
is appropriate. The vvp runtime has been altered to use this new
data which is accessed with the vpip_time_precision_from_handle()
function. vpiTimePrecision uses this function to return the correct
precision.
2007-09-28 15:08:02 -07:00
7c852aa075
Add cmos/rcmos primitives.
...
This patch adds the cmos and rcmos primitives.
2007-09-06 18:46:22 -07:00
d883979fd8
Seperate arrayness from word count
2007-04-02 01:12:34 +00:00
611d2c81b3
Spelling fixes from Larry
2007-03-22 16:08:14 +00:00
fc9a90c9e0
Add support for edge sensitive spec paths.
2007-03-02 06:13:22 +00:00
243cf94165
Add support for conditional specify delay paths.
2007-03-01 06:19:38 +00:00
6804732b9e
Spelling fixes (larry doolittle)
2007-02-26 19:49:48 +00:00
d2ba78559a
Process Verilog escape sequences much earlier.
2007-02-25 23:08:24 +00:00
6d91be5b19
Use inttypes.h instead of stdint.h for portability.
2007-02-02 04:33:00 +00:00
d175eb17f1
Clarify the use of ivl_scope_def for not-functions.
2007-01-29 01:52:51 +00:00
6f3ddce7c4
Dead code for memories in scopes.
2007-01-17 05:00:12 +00:00
f5a7ee0736
Remove dead code related to memories.
2007-01-17 04:39:18 +00:00
91d84e7dc7
Major rework of array handling. Memories are replaced with the
...
more general concept of arrays. The NetMemory and NetEMemory
classes are removed from the ivl core program, and the IVL_LPM_RAM
lpm type is removed from the ivl_target API.
2007-01-16 05:44:14 +00:00
0edb5a7547
Basic support for specify timing.
2006-09-23 04:57:19 +00:00
fc0695beb6
Handle 64bit delay constants.
2006-08-08 05:11:37 +00:00
06d6ac4b33
Fix/implement signed right shift.
2006-07-30 02:51:35 +00:00
80f30be9d0
Add support for system functions in continuous assignments.
2006-06-18 04:15:50 +00:00
707af782b3
Fix part selects in l-values.
2006-04-16 00:15:43 +00:00
f001d0001a
Add support for generate loops w/ wires and gates.
2006-04-10 00:37:42 +00:00
d434dd7296
Allow part selects of memory words in l-values.
2006-02-02 02:43:57 +00:00
58f182a159
Node delays can be more general expressions in structural contexts.
2006-01-02 05:33:19 +00:00
1721799050
Document binary expression use.
2005-12-22 15:44:29 +00:00
244844c067
Document the IVL_ST_DELAY statements.
2005-11-20 15:58:25 +00:00
be73be8c98
Spelling patches from Larry.
2005-09-19 21:45:35 +00:00
c39976fbf1
Generate code to handle real valued muxes.
2005-09-01 04:11:37 +00:00
4a8be3db9c
Implement bi-directional part selects.
2005-08-06 17:58:16 +00:00
b9799cf6ec
Remove NetVariable and ivl_variable_t structures.
2005-07-11 16:56:50 +00:00
75ad90534b
Generalize signals to carry types.
2005-07-07 16:22:49 +00:00
a0dce80eba
Document ivl_logic_delay function.
2005-06-13 22:25:37 +00:00
739a1839ed
Do sign extension of structuran nets.
2005-05-24 01:44:27 +00:00
7dd0d255a6
Add support for variable part select.
2005-05-08 23:40:14 +00:00
06816e79fe
Clarify internal delays for assignments.
2005-05-07 03:14:00 +00:00
365cfedd55
Update DFF support to new data flow.
2005-04-24 23:44:01 +00:00
6244dc1194
Make logic aware of strength.
2005-04-13 06:35:11 +00:00
e8a6835d36
Make clear that memory addresses are cannonical.
2005-04-08 04:52:31 +00:00
65c7ec00e7
Rework NetRamDq and IVL_LPM_RAM nodes.
2005-04-06 05:29:08 +00:00
236ff2b278
Clean up handle of UDPs.
2005-04-01 06:04:30 +00:00
53da6e9a33
Add support for LPM_UFUNC user defined functions.
2005-03-18 02:56:03 +00:00
53af2949b4
Generate code for new form of memory ports.
2005-03-09 04:53:40 +00:00
0fb1fd36ee
Handle memory words in l-value concatenations.
2005-03-05 05:47:42 +00:00
85286cc086
Rearrange how memories are supported as vvp_vector4 arrays.
2005-03-03 04:33:10 +00:00
257e1f9516
Support shifts and divide.
2005-02-19 02:43:38 +00:00
aaf35ab1a9
Handle bit selects in l-values to assignments.
2005-02-14 01:51:39 +00:00
1d7235b4f1
Replace supply nets with wires connected to pullup/down supply devices.
2005-02-13 01:15:07 +00:00
d74177634c
Restructure NetMux devices to pass vectors.
...
Generate NetMux devices from ternary expressions,
Reduce NetMux devices to bufif when appropriate.
2005-02-12 06:25:40 +00:00
ee5bb5fcaf
Add the NetRepeat node, and code generator support.
2005-02-08 00:12:36 +00:00
97f83ffbe3
laborate reduction gates into LPM_RED_ nodes.
2005-02-03 04:56:20 +00:00
609b6a7baa
Netlist boolean expressions generate gate vectors.
2005-01-29 18:46:18 +00:00
695718d691
Clarify width of nexus.
2005-01-29 16:47:20 +00:00
99ace10774
Simplified NetMult and IVL_LPM_MULT.
2005-01-28 05:39:33 +00:00
dfb7c7ba6f
Remove the NetEBitSel and combine all bit/part select
...
behavior into the NetESelect node and IVL_EX_SELECT
ivl_target expression type.
2005-01-24 05:28:30 +00:00
cb4e0d4724
stub dump signed flags of magnitude compare.
2005-01-22 17:36:59 +00:00
e28636776a
Change case compare from logic to an LPM node.
2005-01-22 01:06:55 +00:00
9e94afe399
Use PartSelect/PV and VP to handle part selects through ports.
2005-01-09 20:16:00 +00:00
8f2d679c8a
Unify elaboration of l-values for all proceedural assignments,
...
including assing, cassign and force.
Generate NetConcat devices for gate outputs that feed into a
vector results. Use this to hande gate arrays. Also let gate
arrays handle vectors of gates when the outputs allow for it.
2004-12-29 23:55:43 +00:00
5eb25e44e1
Add ivl_event_scope, and better document ivl_event_X methods.
2004-12-18 18:56:18 +00:00
4444079409
Fixup force statement elaboration.
2004-12-15 17:10:40 +00:00
65e9b6be12
Rework of internals to carry vectors through nexus instead
...
of single bits. Make the ivl, tgt-vvp and vvp initial changes
down this path.
2004-12-11 02:31:25 +00:00
e4ae832153
Clean up spurious trailing white space.
2004-10-04 01:10:51 +00:00
94647be1f0
Some commentary on ivl_logic_pin.
2004-09-25 01:58:12 +00:00
e56b77a43f
Add support for wait on list of named events.
2003-12-03 02:46:23 +00:00
bc0ead2842
Spelling fixes in comments.
2003-11-08 20:06:21 +00:00
64d795c53a
Preserve variable ranges all the way to the vpi.
2003-08-22 23:14:26 +00:00
e561819179
Add synthesis support for synchronous reset.
2003-08-15 02:23:52 +00:00
d653a7e88d
Add support for triand and trior.
2003-07-30 01:13:28 +00:00
bad861dba3
Module attributes make it al the way to ivl_target.
2003-06-23 01:25:44 +00:00
2a29c4fd62
Support real expressions in case statements.
2003-05-14 05:26:41 +00:00
f1cc9d865b
Support event names as expressions elements.
2003-04-22 04:48:29 +00:00
5d1d99a89f
Handle signed magnitude compare all the
...
way through to the vvp code generator.
2003-04-11 05:18:08 +00:00
1222153cdf
Keep parameter constants for the ivl_target API.
2003-03-10 23:40:53 +00:00
22d392a75c
Obsolete the ivl_event_name function.
2003-03-06 01:24:37 +00:00
badad63ab4
All NetObj objects have lex_string base names.
2003-03-06 00:28:41 +00:00
a275133ff9
LPM objects store only their base names.
2003-02-26 01:29:24 +00:00
e941e7e805
Spelling fixes.
2003-01-30 16:23:07 +00:00
46253ed873
Rework expression parsing and elaboration to
...
accommodate real/realtime values and expressions.
2003-01-26 21:15:58 +00:00
c2070777b2
The $time system task returns the integer time
...
scaled to the local units. Change the internal
implementation of vpiSystemTime the $time functions
to properly account for this. Also add $simtime
to get the simulation time.
2002-12-21 00:55:57 +00:00
9ce2806710
Fix synth2 handling of aset/aclr signals where
...
flip-flops are split by begin-end blocks.
2002-10-23 01:45:24 +00:00
166621bcb3
Generate vvp code for asynch set/reset of NetFF.
2002-09-26 03:18:04 +00:00
dac99b9374
Add support for binary nand operator.
2002-09-12 15:49:43 +00:00
bd9e66d333
Missing declaration of ivl_memory_scope.
2002-08-24 05:03:40 +00:00
52bf4e613f
conditional ident string using autoconfig.
2002-08-12 01:34:58 +00:00
693e9e5ad0
Store only the base name of memories.
2002-08-05 04:18:45 +00:00
89314d4772
Do not use hierarchical names of memories to
...
generate vvp labels. -tdll target does not
used hierarchical name string to look up the
memory objects in the design.
2002-08-04 18:28:14 +00:00
301040a67a
Avoid emitting to vvp local net symbols.
2002-07-05 21:26:17 +00:00
5eca5d9948
Carry integerness throughout the compilation.
2002-06-21 04:59:35 +00:00
d6c946f390
Spelling patch (Larry Doolittle)
2002-06-11 03:34:33 +00:00
422754f36f
Support carrying the scope of named begin-end
...
blocks down to the code generator, and have
the vvp code generator use that to support disable.
2002-05-27 00:08:45 +00:00
bfad382fd1
Carry Verilog 2001 attributes with processes,
...
all the way through to the ivl_target API.
Divide signal reference counts between rval
and lval references.
2002-05-26 01:39:02 +00:00
700887d657
Verilog 2001 attriubtes on nets/wires.
2002-05-24 04:36:23 +00:00
e6c0629626
Add language support for Verilog-2001 attribute
...
syntax. Hook this support into existing $attribute
handling, and add number and void value types.
Add to the ivl_target API new functions for access
of complex attributes attached to gates.
2002-05-23 03:08:50 +00:00
828ca0ef9d
Add API to support user defined function.
2002-03-17 19:30:20 +00:00
b7c2bd4f72
Add the NetUserFunc netlist node.
2002-03-09 02:10:22 +00:00
364ffc9024
Add support for bit select of parameters.
...
This leads to a NetESelect node and the
vvp code generator to support that.
2002-01-28 00:52:41 +00:00
dd79885f6d
Add structural modulus support down to vvp.
2002-01-03 04:19:01 +00:00
da09d4c6e6
The IVL_SIT_WIRE type does not exist, it is a
...
synonym for IVL_SIT_TRI.
2001-12-15 02:13:17 +00:00
c8319bcc02
Add ivl_logic_delay function to ivl_target.
2001-12-06 03:11:00 +00:00
08f0f5a1f7
DLL target support for force and release.
2001-11-14 03:28:49 +00:00
ab9a853d52
ivl_target support for cassign.
2001-11-01 04:25:31 +00:00
75e78e86d3
ivl_target support for assign/deassign.
2001-10-31 05:24:52 +00:00
d350620315
Support multiple root modules (Philip Blundell)
2001-10-19 21:53:24 +00:00
177fa4062b
Support IVL_LPM_DIVIDE for structural divide.
2001-10-16 02:19:26 +00:00
cbd501b865
Fix some Cygwin DLL handling. (Venkat Iyer)
2001-09-30 16:45:10 +00:00
e99059e001
Support attributes to logic gates.
2001-09-16 22:19:42 +00:00
0253f92e7e
pin down some enumerated constants.
2001-09-09 22:21:57 +00:00
d762a320dc
Make constants available through the design root
2001-09-01 01:57:31 +00:00
e79a371f76
Support DFF CE inputs.
2001-08-31 22:58:39 +00:00
2002c03cef
Add some ivl_target convenience functions.
2001-08-28 04:07:17 +00:00
e35ed6e91c
Change the NetAssign_ class to refer to the signal
...
instead of link into the netlist. This is faster
and uses less space. Make the NetAssignNB carry
the delays instead of the NetAssign_ lval objects.
Change the vvp code generator to support multiple
l-values, i.e. concatenations of part selects.
2001-08-25 23:50:02 +00:00
2802601c44
tgt-vvp generates code that skips nets as inputs.
2001-08-10 00:40:45 +00:00
becc7cb56a
Handle part select expressions as variants of
...
NetESignal/IVL_EX_SIGNAL objects, instead of
creating new and useless temporary signals.
2001-07-27 04:51:44 +00:00
629a02cccf
Fix binding of dangling function ports. do not elide them.
2001-07-27 02:41:55 +00:00
ce589da58a
Support the NetESubSignal expressions in vvp.tgt.
2001-07-22 00:17:49 +00:00
cd8e491028
Support calculated delays in vvp.tgt.
2001-07-19 04:55:06 +00:00
bcaa122fb9
handle left shifter in dll output.
2001-07-04 22:59:25 +00:00
ab7b353ace
support fast programming by only writing the bits
...
that are listed in the input file.
2001-06-30 23:03:16 +00:00
81536481cc
Add structural EEQ gates (Stephan Boettcher)
2001-06-19 03:01:10 +00:00
4b82d26f5e
Add support for structural multiply in t-dll.
...
Add code generators and vvp support for both
structural and behavioral multiply.
2001-06-16 23:45:05 +00:00
bf42772995
Generate code to support memory access in continuous
...
assignment statements. (Stephan Boettcher)
2001-06-16 02:41:41 +00:00
b3a5a0e5ab
Generate vvp code for GT and GE comparisons.
2001-06-15 04:14:18 +00:00
2f2657b765
support subtraction in tgt-vvp.
2001-06-07 03:09:37 +00:00
f480943649
Support structural addition.
2001-06-07 02:12:43 +00:00
61991e6367
stub ivl_expr_parms for sfunctions.
2001-05-20 01:06:16 +00:00
0872ad34cf
Behavioral ternary operators for vvp.
2001-05-17 04:37:02 +00:00
2292751fc3
Make sure LPM devices have drives on outputs.
2001-05-12 03:18:44 +00:00
Cary R
Stephen Williams
Larry Doolittle
steve