337eb3f8e7
V0.9: Fix spacing issues
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Fix space before tab and space/tab before EOL.
2011-03-08 19:21:56 -08:00
34c34e33cf
V0.9: back port of SunPro compiler support.
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This patch combines all the changes needed to back port support for
the SunPro compilers to the stable branch.
2010-06-18 15:57:52 -07:00
2115e87f78
Fix VHDL naming collisions with modules
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This fixes a bug where the renaming rules for modules
would generate entity names that collided with already
existing module names.
2009-02-05 14:40:47 -08:00
f89f3dcbaf
More VHDL naming fixes
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This handles the cases where:
* Instance names contain leading/trailing underscores
* Instance names contain consecutive underscores
* Module names contain consecutive underscores
* Module names contain leading/trailing underscores
* Ports may be inconsistently renamed
2009-02-02 19:41:50 -08:00
501106dc92
Support named blocks with local variables in VHDL target
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This patch adds code to generate process-local variables
for scopes of type IVL_SCT_BLOCK. This also handles using
the correct assignment operator (:=) for the local VHDL
variables.
2009-02-01 07:08:55 -08:00
ee5302cf33
Fix some more errors when reading from VHDL outputs
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I forgot to modify the LPM generating code with the
last patch. This *should* now always ensure a signal
is readable before code is generated to read from it.
2009-01-25 07:50:03 -08:00
f1f9274bb9
Move VHDL global state management to a single file
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The new state.cc/hh file now manages all the global
state that we maintain while generating VHDL. This
should make the code a bit tidier.
2009-01-17 09:19:58 -08:00
ede6acca77
Store only a single VHDL entity for each Verilog module
2009-01-17 09:19:57 -08:00
3c2080e502
Start improving performace of VHDL hierarchy generation
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This should prune a large amount of the visits to scopes
in the hierarchy. In particular, only one instance of each
scope type should be visited.
2009-01-17 09:19:57 -08:00
651d208451
Remove some uneccessary zero-time waits from VHDL outputs
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This patch optimises away straight line sequences like:
wait for 0 ns;
wait for X ns;
to:
wait for X ns;
This tidies up the output a bit.
It also has the effect of removing all code from initial
processes where the assignments have been extracted as
VHDL signal intialisers. (c.f. pr2391337)
2008-12-07 16:53:47 -08:00
1cc5586c4d
Add debugging output to VHDL target
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Prints progress when -pdebug=1 specified.
Adds a new debug_msg function to print progress messages.
2008-11-29 20:16:09 -08:00
e01e038cf9
Avoid generating useless `wait for 0ns' statements
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If the final statement in a process is a non-blocking
assignment then there is no point adding a `wait for 0ns'
after it since it will be immediately followed by another
wait. This case is suprisingly common, so this patch helps
generate much cleaner output without breaking the cases
where the 0ns wait is actually required (e.g. to implement
non-blocking assignment properly).
2008-08-05 11:02:36 +01:00
baa2363e85
Split logic device code into separate file
2008-07-30 10:13:08 +01:00
744fbed783
Finish re-writing nexus code
2008-07-29 19:33:40 +01:00
48c1a7982c
Make seen_nexus private
2008-07-29 14:24:04 +01:00
f8034d69ef
Fix constants in nexuses
2008-07-29 13:30:54 +01:00
d94dac28a8
Remove redundant lpm_output
2008-07-29 13:08:13 +01:00
8a5f129e56
Draw nexus in multiple passes
2008-07-29 12:00:26 +01:00
e4c2400eb2
Refactor the expression->time code into a single function
2008-07-23 16:18:49 +01:00
af3ee49f57
Refactor support function code a bit
2008-07-19 20:49:55 +01:00
b6df73d3b9
Support functions for converting (un)signed -> boolean
2008-07-19 15:15:16 +01:00
2d79e1a2e0
Store the currently active entity
2008-07-19 14:45:00 +01:00
b8e758edf0
Refactor LPM code
2008-07-15 14:09:24 +01:00
0b48f69b4e
Tidy up blocking assignment code
2008-07-15 10:44:48 +01:00
e331e4831b
Fix nexus_to_expr where nexus has IVL_LPM_SELECT_PV
2008-07-14 11:53:38 +01:00
3bd480a375
Allow ouput to be read if connected to child output
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If output P of A is connected to output Q of B (and A is
instantiated inside B) then VHDL does not allow B to read
the value of Q (also P), but Verilog does. To get around
this the output Q is mapped to P_Sig which is then connected
to P, this allows B to read the value of P/Q via P_Sig.
2008-07-13 12:41:02 +01:00
860a74ddd8
Allow LPMs in port maps
2008-07-07 20:41:29 +01:00
4e73b1b133
Fix bug when resolving nexus to VHDL signal
2008-06-30 17:47:45 +01:00
44aa8a6b91
Associate signals with scopes rather than entities
2008-06-25 18:12:57 +01:00
bf95d77562
Finish replacing vhdl_process with vhdl_procedural
2008-06-24 20:01:06 +01:00
db992e808f
Start using vhdl_procedural instead of vhdl_process
2008-06-24 19:54:22 +01:00
63b1887ff2
Refactor code to use the new vhdl_scope class
2008-06-24 18:52:25 +01:00
469036990a
Output blocking assignments in the right place
2008-06-23 12:30:48 +01:00
404c22ac86
Improved implementation of $display
2008-06-20 11:51:13 +01:00
e0f41198d6
Blocking assignment working correctly
2008-06-18 13:49:03 +01:00
fb31a88c51
Blocking assignment nearly working
2008-06-18 13:30:19 +01:00
254ccb9ccb
First passing at blocking assignment
2008-06-18 13:06:27 +01:00
d2bebee9d9
Refactor before adding blocking assignment
2008-06-18 12:51:11 +01:00
af8c08e6a7
Allow optional VHPI $finish implementation
2008-06-17 20:16:16 +01:00
561953e494
Minial LPM to support continuous assignments
2008-06-16 19:41:01 +01:00
b8c1f9ab67
A system for linking ivl_signal_t to entities
2008-06-12 20:26:23 +01:00
a7cfdc3a87
Add VHDL if statement to AST types
2008-06-11 14:11:37 +01:00
1d28b935e8
Split vhdl_element.cc into multiple files
2008-06-08 13:27:48 +01:00
9f035108e1
Stub code for translating expressions
2008-06-04 14:59:04 +01:00
4bf2e1669d
Store packages required with entity rather than globally
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Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
2008-06-04 13:52:56 +01:00
fe80da362c
Collect required packages as compilation progresses
2008-06-03 19:14:47 +01:00
4211e651d0
Stub file for processing statements
2008-06-03 18:26:36 +01:00
9292a087e8
Generate VHDL processes from Verilog processes
2008-06-02 16:17:01 +01:00
8189c4ee43
Generate VHDL entities and architectures for all module scopes
2008-05-31 15:28:25 +01:00
e38494a10c
Pretty-print VHDL output
2008-05-29 16:24:16 +01:00
Cary R
Nick Gasson